A 3 Mpixel ROIC with 10 m Pixel Pitch and 120 Hz Frame Rate Digital Output

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1 A 3 Mpixel ROIC with 10 m Pixel Pitch and 120 Hz Frame Rate Digital Output Elad Ilan, Niv Shiloah, Shimon Elkind, Roman Dobromislin, Willie Freiman, Alex Zviagintsev, Itzik Nevo, Oren Cohen, Fanny Khinich, Amnon Adin, Ron Talmor, Yaakov Milstain SCD Semiconductor Devices (Israel) ABSTRACT A 1920x1536 matrix ROIC (Readout IC) for 10x10 m 2 P-on-N InSb photodiode array is reported. The ROIC features several conversion gain options implemented at the pixel level. A 2-by-2 pixel binning feature is implemented at the pixel level as well, improving SNR and enabling higher frame rates by a factor of four. A new column ADC is designed for low noise and low power consumption, while reaching 95 ksps sampling rate. Since 3840 column ADCs are integrated on chip, the total conversion rate is over 360Mpxl/sec. The ROIC achieves 120 Hz frame rate at the full format, with power consumption of less than 400mW. A high speed digital video interface is developed to output the required data bandwidth at a reasonable pin count. Keywords: ROIC, IR, column parallel ADC, Sub-LVDS, InSb, 10 m pixel 1. INTRODUCTION Infra-red (IR) image sensors of large formats (several million pixels) are required to improve spatial resolution (more pixels on the same target area), or conversely, cover a larger field of view (FOV) by a single image sensor (replacing multiple image sensors in the system). As a result of this demand the pixel pitch is pushed smaller as the various IR pixel technologies enable. The reduced pitch and increased image format present several challenges to the ROIC design, such as: achieving the required charge storage capacity, maintaining pixel functionality, reading and processing the pixel signals to achieve the required frame rate and image quality. The ROIC should achieve these goals while keeping power consumption at a minimum level since many of the IR photodiodes require cooling to cryogenic temperatures and the ROIC power consumption will affect the cooler size, power, reliability and cost. 2. ARCHITECTURE The functional block diagram of this new ROIC by SCD is shown in figure 1, detailing the pixel circuit matrix which is built for hybridization with a photodiode array, as well as the column-parallel analog to digital converters (ADC), digitizing the matrix outputs. The ADCs' outputs are multiplexed in the proper sequence to send an ordered image data through the video driver outputs. All of these blocks are regulated by a central controller which is connected to the serial communication port. The ROIC is controlled through a standard serial communication protocol, as well as frame-sync. The pixel can operate in several gain modes which are detailed in section 3. Image data can be readout from the ROIC in several modes which are termed full-rate, half-rate and quarter-rate. These modes enable a tradeoff per application of frame rate, power, and number of video lines. For example, in full-rate mode all column-parallel ADCs are operated, digitizing 2 pixel rows simultaneously, and all video lines are used to achieve the required bandwidth. However, for a video application at 30 frames per second (fps), quarter-rate mode can be used which operates only a quarter of the ADCs (reducing power consumption) and a quarter of the video lines (reducing pin count).

2 ROIC Main Reference FPA Hybridization Pixel Matrix ADC Readout Mux Video Driver VIDEO OUTPUT Comm. Control Test pattern fsync clock sdat sclk Figure 1. ROIC functional block diagram 3. PIXEL MATRIX DESIGN The ROIC pixel circuit design is a key factor in setting the image sensor radiometric performance. In thermal imaging the natural contrast in the scene is very low (compared to the SWIR or visible spectrum ranges), and therefore a high signal to noise ratio (SNR) is required. This implies collecting as many photo-electrons as possible, taking into account the available photo-current, which is a function of the spectral range, system and detector optics and quantum efficiency of the photodiodes. The traditional voltage readout pixel design relies on capacitors for collection of photo-generated electrons. The capacitor size defines the effective well capacity and hence the achievable SNR (the square root of the number of collected photo-generated electrons). With smaller pitch pixels the available capacitor area is reduced, while the photo-current may not scale proportionally. In this work, in order to increase the available well capacity, a part of the pixel circuit is shared between four neighboring pixels. The shared circuit includes the output buffer and the switch connecting it to the column wire, shown in figure 2. Sharing this circuit saves pixel real estate and enables larger capacitors. 4 pixels P-on-N photodiode direct injection stage detector common integration pixel select shared circuit output buffer buffer select column wire gain control Figure 2. Pixel block diagram depicting 4 pixels and the shared circuit block Another feature added to further increase the well capacity is in-pixel "frame averaging": the required integration time is split in two. Then the 1st half integration result is stored in the pixel. After the 2nd half integration is over, the results are averaged inside the pixel. The resulting SNR is equivalent to that of a double well capacity. On the other hand there are applications in which the signal is weak due to constraints on integration time, spectral range or optical conditions such as F#. In these cases the readout noise may limit the SNR. To reduce readout noise such that shot noise will dominate the SNR, a high gain mode is designed in the pixel, with a much lower well capacity (roughly 10x smaller than nominal).

3 Pixel binning is a known feature which combines the signals of neighboring pixels to improve SNR. While binning can be implemented off the focal plane (e.g. in the system), there is an advantage to design it at the pixel level. Namely, by connecting four neighboring pixels, which share the same output buffer as mentioned before, we reduce the output data bandwidth by x4 and reduce the power consumption accordingly. Alternatively, we can maintain the same bandwidth and increase the frame rate by x4. This frame rate increase (at the cost of spatial resolution) is required by some applications, especially in a large format ROIC. The pixel matrix structure is shown below in figure 3. In addition to the image pixels (1920 x 1536) there are rows above and below the image area, as well as columns to the left of the image area, with reference pixels. These reference pixels are not connected to the photodiode array, but generate a reference voltage which is digitized and output through the video channel. The data of these reference pixels can be used to remove various artifacts which may appear across an entire row or column, and thereby improve image quality. Figure 3. Pixel matrix structure 4. COLUMN PARALLEL ADC DESIGN The pixel output voltages are digitized using two rows of column parallel ADCs, above and below the pixel matrix. Each ADC is designed into the 10um pitch, such that two pixel rows are digitized simultaneously. As in previous digital ROICs by SCD 1, the designed ADC type is dual ramp which enables relatively high resolutions at a low power consumption. The ADC is designed to support the 120 Hz frame rate at full frame readout, which dictates conversion frequency of ~100 khz. Additionally, the ADC noise level should ideally be negligible compared to the pixel output noise in all modes. A table summarizing the designed ADC performance follows. Table 1. Designed Column Parallel ADC Performance (77K) Resolution Parameter Conversion Frequency Input-Referred Noise Integral Non-Linearity (INL) Power Consumption Layout Area 13 bit > 95 khz < 160 V Value < 0.02% of full range < 35 W 10 x 800 m^2

4 V[mV] dy = 200mV 5. VIDEO OUTPUT DESIGN To output 1920 x 1536 pixels, 13 bit each, at a frame rate of 120 Hz a data bandwidth greater than 4.6 Gbps (without taking into account headers and status bits) is required. The ROIC is designed to operate with cryogenically cooled arrays, which imposes severe constraints on power consumption and the number of data pins in the Dewar. In addition, the packaging of cryogenically cooled detectors includes wire bonds with large inductance and resistance, which limits the possible frequency of operation. After a tradeoff of these constraints and requirements, sub-lvds electrical standard was chosen for the video output. Supported by many FPGAs, the sub-lvds has relatively low power consumption and due to its differential structure generates a low level of interferences on chip and off chip. Each sub-lvds pair will output 560 Mbps. The sub-lvds driver was designed to operate from a 1.8V supply, to reduce power consumption. The 3-D mechanical structure of the detector package (Dewar) was extracted to get an electrical model, taking into account the different materials and geometries. The model was simulated with the driver circuit to predict the performance. The output waveform on the receiver's 100 ohm termination was extracted from this simulation and is shown as an Eye Diagram in figure 4. dx = 1.28ns Figure 4. Sub-LVDS simulated Eye Diagram at the receiver Time[ns] To prepare the data for sub-lvds transmission a serializer is designed, clocked at 560 MHz which is generated by a low-jitter low-power Phase Locked Loop (PLL). The logical protocol of the video output packs 2 pixels with status bits into a 32 bit word, to be transmitted through 4 sub-lvds pairs (32 to 4 serializer). Every 4 pairs of data are accompanied by 1 pair of clock to assist data sampling at the receiving end. In the current ROIC there are a total of 16 data pairs and 4 clock pairs, which output a total of 8.96 Gbps, representing 560 Mega pixels per second. 6. MEASURED RESULTS The ROIC is now in silicon validation phase. Initial results from the first samples are reported below. As described above, a sub-lvds video output was designed. The electrical performance of this output is now characterized in a test dewar. An eye diagram of a sub-lvds pair transmitting a test pattern at 560 Mbps, measured using a high frequency differential probe and scope is shown below.

5 # of Pixels # of Pixels # of pixels Figure 5. Sub-LVDS output eye diagram Floor noise histograms at 300K (room temperature) and 77K are shown, with median values of 1.94 DL and 0.95 DL, respectively. These values represent input-referred noise levels of 500uV-rms at 300K and 200uV rms at 77K, which are within the specifications for the measured gain mode. 12 x 104 Floor 77K 5 x 104 Floor 300K Floor 300K Noise [DL] noise[dl] Noise [DL] Figure 6. Floor Noise histograms at 77K (left) and 300K (right)

6 7. SUMMARY A 3 Mpxl with 10 m pitch ROIC was designed and fabricated, including a 10 m pixel with multiple gains, new low power-low noise dual ramp column ADCs, and a high speed serial video interface. Early measurements of the ROIC show expected noise values and power consumption, although detailed data is not available yet. The various ROIC features and modes were verified in silicon as well. Further testing and characterization is required to explore the full performance and capabilities of this ROIC. The reported chip is the first 10 m pixel pitch ROIC in SCD, and can be easily adapted to other formats, such as XGA or VGA. ACKNOWLEDGEMENTS The authors would like to thank Ernesto Kuznitzky, Miriam Geva, and Anat Liran for their intensive work on the ROIC; SCD electronics team for developing the required test equipment; the IMOD for support of this project. REFERENCES [1] Shimon Elkind, Amnon Adin, Itzhak Nevo and Arkady B. Marhasev, "Focal plane processor with a digital video output for InSb detectors", Proc. of SPIE vol. 4820, Infrared Technology and Applications XXVIII Conference, pp (2002).