Design and Implementation of an Ultra-high Speed Data Acquisition System for HRRATI

Transcription

1 Design and Implementation of an Ultra-high Speed Data Acquisition System for HRRATI Bi Xin Du Jinsong Fan Wei Abstract - Data Acquisition System (DAS) is a fundamental functional part in every radar application, especially when used for high range resolution radar system. This paper presents a high speed and reliable DAS of a High range Resolution Radar used for Acquiring Traffic flow Information (HRRATI). The system uses high performance Field Programmable Gate Array (FPGA) to cope with the data transformed by the high speed 8-bits Analog-to-Digital Converter (ADC08D500), which performs digitization of the dual channels radar echo signals with sampling rate at 500MHz. The signal bandwidth up to 180MHz in each channel, then the system preprocesses all the data onboard in real time. In view of the broad bandwidth of the signal and high sampling rate, clock jitter, signal integrity and EMI/EMC issues assume great importance and pose a great challenge to the Printed Circuit Board (PCB) design. This paper gives a thorough investigation of such problems. Finally, clock jitter and ENOB test experiment results show that the DAS is capable of sampling the radar signal effectively. Index Terms - High range Resolution Radar; Data Acquisition System; FPGA; LVDS I. INTRODUCTION The general concept of automatic vehicle identification was proposed in the late 1960 s [1] and was extended to road vehicles during the 1970 s with the publication of various reports [2],[3]. While these systems were revolutionary in concept, technology could not provide the necessary accuracy and flexibility. With the recent advances in microwave and integrated circuit technology, the most effective systems for detecting high speed vehicles generally employ microwave or millimeter wave radar[4][5]. Since traditional radars cannot provide more information of targets because of deficiency of resolution, the technology of High Range Resolution Radar has been increasingly getting broader application after the pulse compression technique was introduced into the radar signal processing domain. For these applications, we are faced with the problem of how to sample broad bandwidth radar returns precisely. In recent years, the rapid development of the FPGA [6] and the advances of ADC architectures and technology [7] make taking advantage of these devices possible and thus eliminate the need for special purpose hardware that is unnecessarily cost prohibitive. On the basis of the previous considerations, a low-cost, portable, and reliable system was designed and built, featuring no constraints in sampling rate to some extent ( 500MSPS). Moreover, evaluation results show the availability of this proposal. In this sense, the goal of this paper is to highlight the feasibility of the DAS for HRRATI. This paper is organized as follows. In Section II, the design considerations are discussed. In Section III, DAS structure and data interconnect are introduced briefly. In Section IV, key techniques in ultra high speed data /09/$ IEEE 89

2 acquisition system are studied. In section V, evaluation of system performance is engaged. Finally, conclusions are made in Section Ⅵ. II. DESIGN CONSIDERATIONS We ve considered several key points to this system while designing a high-speed two-channel data acquisition system. 8-bits ADC resolution is required by High Range Resolution Radar signal characteristics and SNR performance. ADC sampling rate requirement is determined by radar signal bandwidth. Considering the maximum bandwidth of 180MHz in each channel, ADC sampling rate was fixed at 500MHz. In view of the realization aspects, the orthogonal sampling approach was adopted. Input analog signals and clock signals of the ADC chip would be differential in order to improve the SNR performance. New FPGA de-serializing technique is adopted to reduce data rate for data transmission. The Cyclone III series FPGAs of Altera Incorporated have programmable LVDS interface and the transceiver can work properly at 840Mbps. So FPGA is chosen to realize the high-speed interface with ADC. Another major aspect of the design is to synchronize I and Q channels of the data acquisition system. In order to minimize the imbalance between I channel and Q channel, star topology is used in PCB design, and the EDA software could guarantee the uniformity of track length between different drivers and receivers. III. DAS STURCTURE AND DATA INTERCONNECTION This onboard digital subsystem has to cater to the DAS control timing and buffer storage requirements of the radar system. The system mainly consists of an ADC chip and an FPGA chip. Buffer memory and timing logic were all realized in the FPGA module. Figure 1 shows the block diagram of the whole system. Figure 1. Block diagram of the whole system The demodulated and base-band radar echoes (0~180MHz for both I and Q channels) available from the radar receiver are digitized with an 8-bits resolution ADC chip, ADC08D500 [7]. The ADC08D500 is an ultra-high speed, folding and interpolating, dual channel, low power, high performance ADC that digitizes signals with 8bits resolution at sampling rates up to 500MSPS. Each channel has 1:2 de-multiplexers that feed two LVDS buses and reduce the output data rate on each bus to half the sampling rate. The de-multiplexed data are stored in a high speed asynchronous First-In First-Out (FIFO) buffer, thus reducing the average data rate in subsequent data interface with digital signal processor because the time was extended. The 500MHz source clock is supplied by the programmable PLL synthesized clock generator, NBC The PLL loop filter is fully integrated and does not require any external components to generate 50MHz to 800MHz differential PECL outputs. The ADC08D500 has LVDS clock outputs, which supply the clock for the FPGA as its system clock. IV. STUDY OF KEY TECHNIQUES IN HIGH SPEED DATA ACQUISITION SYSTEM With the sample speed increasing, new difficulties appeared. In this chapter, a few significant techniques are studied. A. Design of Clock Module Jitter is a common parameter associated with clock generation and distribution. Clock jitter can be defined as the deviation in a clock s output transition from its ideal position. Cycle-to-Cycle Jitter is the period variation between adjacent periods, see Figure 2. The period jitter is the variation over a defined number of observed cycles. The number of cycles observed is application dependent, but the JEDEC [8] specification is 1000 cycles. 90

3 Figure 2 Cycle-to-Cycle Jitter When any circuitry is added after a signal source, some jitter is always added to that signal. Jitter in a clock signal, depending upon how bad the jitter is, can degrade dynamic performance of the clock. Clock jitter is the sample-to-sample variation in the encode process. From Figure 3a we can see the effects of jitter in the frequency domain as leakage or spreading around the input frequency. Compared with the more desirable plot of Figure 3b, we could easily find that dynamic performance is improved by eliminating clock jitter. Figure 3a. Jitter causes a spreading around the input signal, as well as undesirable signal spurs. generator, NBC12439, to provide the differential PECL clock outputs. A differential translator (SY89325) is used to transform the PECL clock to the 400mV output swing LVDS clock because the ADC08D500 has LVDS clock inputs. Differential signals have many advantages, including the following: a) Small voltage swing of the differential signals means there will be less inter-trace coupling, thereby reducing the signal integrity issue. b) The differential signals used current-mode, which can drive data transmission at very high speed. B. Design of FPGA Module FPGA module is made up of a clock unit, a data de-serialization unit, a signal process unit, and a global control unit. We use Cyclone III series FPGA (EP3C25) of Altera Incorporated. Data rate of the ADC s output is 250MHz when the sampling rate is set at 500MSPS.This ultra-high speed stream is still difficult to process directly using FPGA. In order to implement the data process, a de-multiplexer unit is designed to reduce data rate. Combined with the 1:2 de-multiplexer in ADC08D500, an equivalent 1:4 de-multiplexer is realized in each data channel in the end. Finally, data speed is decreased from 500MHz to 125MHz while data width is increased from 8bits to 32bits. The block diagram of FPGA de-serialization unit is given in Figure 4. Figure 3b. Eliminating or minimizing clock jitter results in a more Figure 4. Block diagram of FPGA de-serialization unit desirable FFT that is more representative of how the ADC actually performs. The above two figures illustrates that accurate clocks are extremely important for high speed ADC applications. In our application, clock jitter is a critical factor to the SNR of the system performance as clock skew to SFDR of the system. So we centered our attention on minimizing clock jitter and clock skew. We select the programmable PLL synthesized clock Each channel output is fed into an ALTLVDS mega-function for conversion from serial to parallel. The ALTLVDS module makes an output of 16 bits in phase parallel data each time, which is twice of the original data width. The logic is implemented to synchronize the different phase data from two channels and arrange the data in sampling order. Finally, a 32-bit-parallel data with 125MHz rate is ready for buffering. An ALTPLL mega-function is used to generate the system clock in 91

4 FPGA. C. Design of PCB The high-speed real-time data acquisition system circuits consist of analog circuits and digital circuits. Electromagnetic radiation will be generated when the high-speed real-time data acquisition system works, which can bring us more risks, for electromagnetic interference (EMI) will degrade the system performance. In this design, the following EMC techniques are used in printed circuit board (PCB) design to reduce the EMI of the system. 1) Four-layer boards with separated ground and power planes produce the highest level of signal integrity. Signal traces are routed on the top and bottom planes, and they are vertical to avoid EMI caused by inducting each other. 2) Ground plane and power plane have been spilt to match the physical location of the analog ground and the digital ground, as well as the analog power and the digital power. Splitting the digital power plane was arranged to match the physical location of the 5V, 3.3V, 1.2V and 2.5V (FPGA core and I/O voltage), 1.9V (ADC supply voltage). The analog ground and digital ground were joined at a single point, such that the noisy digital ground currents cannot interfere with the analog ground plane. High-speed digital signal traces are routed away from sensitive analog traces, such as reference input traces and inter reference voltage output traces. 3) The analog and digital lines should cross each other at 90 o to avoid digital noise entering into the analog path. Clock lines should be isolated from all other lines, analog and digital. The generally accepted 90 o crossing should be avoided as even a little coupling can cause problems at high frequencies. Best performance at high frequencies is obtained with a straight signal path. The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input. This is especially important to the low level driver requirement of the ADC08D500. Any external component (e.g., a filter capacitor) connected between the converter input and ground should be connected to a very clean point in the analog ground plane. All analog circuitry (input amplifiers, filters) should be separated from any digital components. 4) Table 1 gives the routing rules of PCB design: Table1. The Routing rules of PCB design Routing rules of PCB design Distance of Distance to Line Type Line With differential pairs others lines LVDS 13mil 7mil 25mil PECL 9mil 7mil 64mil LVTTL 7mil N/A 16mil V. SYSTEM PERFORMANCE EVALUATION A. Test of Clock Jitter Differential clock signals generated by NBC12439 are collected with an oscilloscope. The Tektronix TDS-series oscilloscope (TDS7404B) has superb jitter analysis capabilities on non-contiguous clocks due to functions of histogram and statistics. The sampling frequency is 40GSPS and the sampling bandwidth is 5GPSP. After being sampled, the data can be transferred to the computer or be calculated by the TDSJIT3 jitter analysis software of TDS7404B. In the experiment, we use the oscilloscopes with sampling rates of 1GSPS. Figure 5 gives the 500 MHz clock signal captured by TDS7404B oscilloscope. We use two channels, CH1 and CH3, connected to the differential output clock signal. MATH signal is equivalent to CH1 subtract CH3, which is the ADC input clock waveform. As we can see from the waveform, the clock signal frequency and amplitude are satisfied. The SMA coaxial cable and socket delivered some waveform distortion, but no overage. There will be no problems for ADC triggering, so the design of high speed clock signal module is successful. Figure 5 500M Clock signal captured by oscilloscope 92

5 B. Evaluation of SNR and ENOB High-quality LFM (0~180MHz for both I and Q channels) signal feed to the circuit. After sampling, we made the fast Fourier transform, and then analyzed the spectrum. This system is tested at 500Msps sampling rate. In order to facilitate FFT, the sampling number is preferable to be 2 N, so we choose N=9. Figure 6 gives the waveform of time domain; and Figure 7 gives the frequency spectrum of the sampled signal. Figure 6 Waveform of Time Domain Figure 7 Spectrum of the signal The figure shows that the signal is obviously contaminated and there are some serious high frequency harmonics in the signal spectrum, including system thermal noise and digital switching noise, which result in SNR performance decreased. After calculation, the system SNR = 26.5dB, so we can calculate ENOB from the Equation (1). ENOB = 3.39bits. f s ( SNR 1.76) 10 lg( ) ENOB = 2 B 6.02 (1) Figure 8 gives the spectrum of the signal that is accumulated 10 times. System Gaussian noise has been suppressed, but the high frequency harmonics is still difficult to be removed. Though the system SNR and ENOB has been improved, the high frequency harmonics depraved the system performance all the same. So we need to optimize the PCB design, for instance, by selecting the joint of analog ground and digital ground reasonable in the future. Figure 8 Frequency spectrum VI. CONCLUSION This paper presents a high speed dual channel data acquisition system based on FPGA. Some key techniques are studied and analyzed, as well as some measures are given. In the end, the system performance is evaluated by experiment tests. The data acquisition system is proven to be reliable and has been successfully used for the high range resolution radar for acquiring traffic flow information. REFERENCES [1] AVI Network Embraces Chicago Terminal Area, progressive Railroading, September October 1973, pp [2] Report of the Organizing Conference on Automatic Vehicle Identification (AVI), Washington, DC, September 17, [3] Robert A. Hansen. The Promise of Automatic Vehicle Identification. IEEE transactions on Vehicular Technology, Vol. VT-26, no. 1, February [4] J. K. Hwang, K. Y. Lin, Y. L. Chiu, et al. Automatic Target Recognition Based on High-Resolution Range Profiles with Unknown Circular Range Shift. The 6th IEEE International Symposium on Signal Processing and Information Technology, August 27 30, 2006, Listel Vancouver Hotel, Vancouver, BC, Canada. [5] Xuan Yi-Guang, Meng Hua-Dong, et al. A High Range Resolution Microwave Radar System for Traffic Flow Rate Measurement. Proceedings of the 8th International IEEE Conference on Intelligent Transportation Systems Vienna, Austria, September 13-16, 2005, pp [6] Cyclone FPGA family data sheet. Altera Corporation, 2006 [7] [8]NBC12439 data sheet, ON Semiconductor, 2003-rev.2 93