Overview of the ALPIDE Pixel Sensor Chip with focus on Readout Features. Gianluca Aglieri Rinella, CERN

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1 Overview of the ALPIDE Pixel Sensor Chip with focus on Readout Features Gianluca Aglieri Rinella, CERN

2 New ALICE ITS Layout 27 cm 4 Outer Barrel layers (OB) 1% X 0 10 m 2 sensitive area ~24000 CMOS Pixel Sensors 12.5 Gpixels 150 cm 40 cm 3 Inner Barrel layers (IB) 0.3% X cm 14/9/2017 # STAVES: gianluca.aglieri.rinella@cern.ch 2

3 ITS Chip General Requirements Parameter Inner Barrel Outer Barrel Chip size (mm x mm) 15 x 30 Chip thickness (mm) Spatial resolution (mm) 5 10 (5) Detection efficiency > 99% Fake hit rate < 10-5 evt -1 pixel -1 (ALPIDE << 10-5 ) Integration time (ms) < 30 (< 10) Power density (mw/cm 2 ) < 300 (~35) < 100 (~20) TID radiation hardness (krad) (**) NIEL radiation hardness (1 MeV n eq /cm 2 ) (**) 1.7 x x Readout rate, Pb-Pb interactions (khz) 100 Hit Density, Pb-Pb interactions (cm -2 ) (*) In color: ALPIDE performance figure where above requirements (**) 10x radiation load integrated over approved program (~ 6 years of operation) 14/9/2017 gianluca.aglieri.rinella@cern.ch 3

4 Detector Modules with ALPIDE Chips ITS Inner Barrel Module 9 chips, common clock and control, independent data lines Clock + Control + Trigger ITS Outer Barrel Module 2 groups of chips, Master + 6 Slaves Only the Master interfaces to the external world and bridges control and data transfer Serial Outputs (1200 Mbps) Clock + Control + Trigger Clock, Control, Local Data Serial Out (400 Mbps) 14/9/2017 Clock, Control, Local Data gianluca.aglieri.rinella@cern.ch Serial Out (400 Mbps) Clock + Control + Trigger 4

5 Inner Barrel Stave Flexible PCB ~1.5 g Power density: < 40 mw/cm 2 Material: < 0.3% X 0 9 Sensors Cold Plate Space Frame 15 mm Fitting Connector 6/9/2016 CERN EP-ESE Group Meeting - gianluca.aglieri.rinella@cern.ch 5

6 Outer Barrel Stave Power bus FPC 2x7 sensors Cold Plate Cold Plates Space Frame Space Frame 6/9/2016 CERN EP-ESE Group Meeting - gianluca.aglieri.rinella@cern.ch 6

GBT links NO RADIATION Readout System 1 Mrad 10 13 1 MeV n eq /cm 2 Central Trigger Processor (CTP) < 10 krad < 10 12 1 MeV n eq /cm 2 < 1 khz/cm 2 Hadrons (>20 MeV) Cavern Counting Room Detector

7 GBT links NO RADIATION Readout System 1 Mrad MeV n eq /cm 2 Central Trigger Processor (CTP) < 10 krad < MeV n eq /cm 2 < 1 khz/cm 2 Hadrons (>20 MeV) Cavern Counting Room Detector Control System (DCS) First Level Processor (FLP) PCIe x 192 GBT links Common Readout Units (CRU) ~6m Copper Links One READOUT UNIT for each STAVE GBT links ~150 m Optical Links 14/9/2017 gianluca.aglieri.rinella@cern.ch 7

8 15 mm palpide-3 Chip 30 mm 14/9/2017 8

9 ALPIDE Pinout 40 MHz 1.2 Gb/s 14/9/2017 9

15 mm 512 x 26.88 um = 13.76 mm ALPIDE Chip Floorplan 30 mm 1024 x 29.24 um = 29941.

10 15 mm 512 x um = mm ALPIDE Chip Floorplan 30 mm 1024 x um = um Matrix ( pixels) Analog DACs Soldering pads Digital Periphery mm Regular Pads + Custom Blocks 14/9/2017 gianluca.aglieri.rinella@cern.ch 10

11 1.208 mm Priority encoder Priority encoder Front End Layout Features Pixel layout Collection Diode Matrix (detail) μm Digital Pixel Section 9.66μm μm μm Periphery (detail) Matrix - Pixels and Priority Encoders Analog DACs Digital Periphery Regular pads + Custom blocks Sea of gates Soldering pads over circuits SRAM blocks 14/9/2017 gianluca.aglieri.rinella@cern.ch 11

12 ALPIDE Technology Pixel Sensor CMOS 180 nm Imaging Process (TowerJazz) 3 nm thin gate oxide, 6 metal layers NWELL DIODE NMOS TRANSISTOR PWELL PWELL NWELL Epitaxial Layer P- h e e h h e e h PMOS TRANSISTOR DEEP PWELL N A ~ cm -3 N A ~ cm -3 SUB pwell A) deep pwell deep pwell PIX_IN p + n + p + p + p + p + p + n + pwell nwell nwell Collection electrode Spacing Diameter PIX_IN SUB Spacing Diameter Spacing B) C) p + p -- n + p -- p + VRESET_P deep pwell IRESET VRESET IRESET VRESET_P nwell deep pwell p -- epitaxial layer p substrate PMOS Reset AVDD epitaxial layer p substrate Not to scale M0b Substrate P++ Not to scale N A ~ cm -3 IRESET AVSS Collection electrode SUB High-resistivity (> 1kW cm) p-type epitaxial layer (18 mm to 30 mm) on p-type substrate Deep PWELL shielding NWELL allowing PMOS transistors (full CMOS within active area) Small n-well diode (2 mm diameter), ~100 times smaller than pixel => low capacitance => large S/N Reverse bias can be applied to the substrate to increase the depletion volume around the NWELL collection diode 14/9/2017 gianluca.aglieri.rinella@cern.ch 12

512 rows Readout (zero suppression) Readout (zero suppression) Readout (zero suppression) Readout (zero suppression) ALPIDE Architecture 1024 pixel columns AMP COMP THR In pixel: Amplification

13 512 rows Readout (zero suppression) Readout (zero suppression) Readout (zero suppression) Readout (zero suppression) ALPIDE Architecture 1024 pixel columns AMP COMP THR In pixel: Amplification Discrimination 3 hit storage registers (MEB) Bias, Readout, Control 29 mm x 27 mm pixel pitch Continuously active front-end Global shutter Zero-suppressed matrix readout Triggered or continuous readout modes 14/9/2017 gianluca.aglieri.rinella@cern.ch 13

14 Pixel C det ~ V bb C in ~1.6 ff v PIX_IN t f ~= 10 ns v OUT_A ~2 ms peaking time OUT_D 5-10 ms DV=Q/C t r > 100 us t threshold t STROBE Analog front-end and discriminator continuously active Non-linear and operating in weak inversion. Ultra-low power: 40 nw/pixel The front-end acts as analogue delay line Test pulse charge injection circuitry Global threshold for discrimination -> binary pulse OUT_D Front End Characteristics Gain (small signal) [mv/e] 4 ENC [e] 3.9 Threshold [e] 92 ± 2 Digital pixel circuitry with three hit storage registers (multi event buffer) Global shutter (STROBE) latches the discriminated hits in next available register In-Pixel masking logic 14/9/2017 gianluca.aglieri.rinella@cern.ch 14

15 VALID SELECT ADDR VALID SELECT ADDR Pixels Priority Encoder Pixels Pixels Priority Encoder Pixels Matrix Readout STATE STATE STATE STATE 512 RESET 512 RESET 512 RESET 512 RESET Clock Periphery Control + trigger The Priority Encoder sequentially provides the addresses of all hit pixels in a double column Combinatorial digital circuit steered by peripheral sequential circuits during readout of a frame Data No free running clock over matrix. No activity if there are no hits Energy per hit: E h ~= 100 pj -> ~3 mw for nominal occupancy and readout rate Buffering and distribution of global signals (STROBE, MEMSEL, PIXEL RESET) 14/9/2017 gianluca.aglieri.rinella@cern.ch 15

16 VALID SELECT/ADV ADDRESS STROBE MEMSEL FLUSH PULSE CFG_SEL CFG_DAT A Pixel left Column (512 pixels) Pixel right Column (512 pixels) Priority Encoder Encodes ADDRESS of first hit pixel of input STATE vector STATE RESET Priority Encoder (1 of 512) 512 STATE RESET 512 Forwards RESET to hit pixel STROBE MEMSEL FLUSH PULSE STROBE MEMSEL FLUSH PULSE Buffers global signals STROBEs, MEMSELs, FLUSHs, PULSEs CFG_SEL CFG_DAT A CFG_SEL CFG_DAT A Buffers pixel configuration signals 10 Digital Periphery 14/9/2017 gianluca.aglieri.rinella@cern.ch 16

17 ALPIDE Block Diagram Matrix 32 readout regions 16 double columns 8b DACs Pixels Config 11b ADC Bandgap + Temp Sens Differential Control Port (40 Mbps) Configuration Registers Control Bus Logic Triggers Single Ended Control Port Region Readout (1) 128x24b DPRAM Readout Sequencing RR (2) RR (3) RR (32) 24b 40MHz 32:1 DATA MUX Chip Data Formatting 24b 40MHz Module Data Management 30b 40MHz Serial Data Transmission PLL 8b/10b Serializer Driver Parallel Data Port (4 80 Mbps) Serial Out Port (1200 Mbps / 400 Mbps) 14/9/2017 gianluca.aglieri.rinella@cern.ch 17

18 Readout ports Serial output port 1.2 Gbps max line rate Optional operation at 600 Mbps and 400 Mbps line rate 960 Mb/s max output data throughput (8b10b encoding applied) Differential signaling, current mode driver, pre-emphasis Parallel data port 320 Mb/s max data throughput only CMOS signaling, 8 bit bus or 4 bit bus 40 MHz clock Can be used to group chips for readout Up to 14 slave chips connected to one master chip forwarding all data on serial link 14/9/2017 gianluca.aglieri.rinella@cern.ch 18

19 DTU Serial Data Transmission Unit DTU INPUT: 3 40 MHz = 960 Mb/s Programmable Line Rate 1200 Mbps/600Mbps/400 Mbps Implemented in the DTU Logic periphery module PLL Phase Locked Loop 40 MHz -> 600 MHz DTU Serializer 30 bits parallel input 2 Serial outputs (600 Mbps) to driver stage 1.2 Gbps serial stream made in Driver stage with fast muxes controlled by PLL clock Semi-custom (standard cells) implementation LVDS Driver Programmable drive current and pre-emphasis current Tailored to ITS application 1.2 Gb/s over 30 cm Al FPC + 5 m twinax cables 400 Mb/s over 1.5 m Cu FPCs + 5 m twinax cables Digital Periphery Output line rate must be tailored to physical channel characteristics (medium, losses, distance) 14/9/2017 gianluca.aglieri.rinella@cern.ch 19

20 14/9/

21 Stolen from Simon Voigt Nesbo 14/9/

22 Matrix readout and Data transmission Matrix readout to periphery Region Readout Units Parallel readout processes reading 32 regions (sub-matrices) 16 Priority Encoders in each region readout sequentially Time: 2 clock cycles (50 ns) to transfer one active pixel hit from in-pixel MEB to region FIFOs in periphery Compression of data (by proximity of hits) before writing in region FIFOs Transmission of data off-chip Top Readout Unit fetches region data packets from the 32 Region Readout FIFOs in round-robin and forwards to Data Transmission Unit Internal parallel data bus between RRUs and TRU: MHz (960 Mb/s) 14/9/2017 gianluca.aglieri.rinella@cern.ch 22

23 Simulation Conditions Event rate : 100 khz Trigger Filtering Window: 800 ns Total Occupancy: 19.5 cm -2 Noise Pixel Probability : 10-6 Cluster Size Average : 4 Pixels fired per event: Front end active time : 6 μs Min Busy Duration : 8 cycles * Total Occupancy = 13 cm -2 (hit density min bias Pb-Pb) cm -2 (integrated QED) 14/9/2017 gianluca.aglieri.rinella@cern.ch 23

24 Dead Time, Missed Triggers, Readout Efficiency Run 1 Run 2 Dead Time % % Missed Triggers 0.17 % (13 out of 7633) 0.14 % (14 out of 9760) Readout Efficiency 99.83% % Bandwidth Used : 35.4 % of available Dead Time = Missed Triggers = Busy Time Total Time Readout Efficiency = Triggers not sent due to Busy asserted Total Number of Triggers that should have been sent Total Number of Triggers Sent Total Number of Triggers that should have been sent 14/9/2017 gianluca.aglieri.rinella@cern.ch 24

25 14/9/

26 Digital Periphery Modules (1) Pixels Configuration Management Decoding and Writing into In-Pixel configuration registers Top Registers Configuration registers of all modules Command register CMU Control Management Unit Implementation of the control interface and protocol Both on the link to the offdetector electronics and locally between OB Master and Slaves Receiving of broadcast commands Triggers, synchronize, resets 14/9/

27 Digital Periphery Modules (2) FROMU Framing and Read Out Management Unit Sequencing of frames strobing and readout phases Multi-event memory handling Programmable readout modes (triggered, continuous) Strobe duration control Time stamping of frames Flagging of anomalous conditions RRU Region Readout Unit (32) Transfer of pixel hit data from in-pixel MEB memories to periphery memory Sequencing of Priority Encoders Data formatting and data reduction TRU Top Readout Unit Chip Data Frame assembly and formatting Sequential reading of up to 32 Region Data Frames 14/9/

28 Digital Periphery Modules (3) BMU Busy Management Unit Driving and sampling of BUSY line (configurable) Requests of transmission of BUSYON/BUSYOFF code words on the output data stream DMU Data Management Unit Data exchange between OB Slaves and OB Master chips OB module local DATA bus sharing protocol (token passing) Double Data Rate logic DTU Logic 8b/10b encoding Implementation of multi-rate serial transmission DTU monitoring functions PLL monitoring and control DTU test features 14/9/

29 Full Custom Blocks MLVDS Transceiver Differential ports (DCLK, MCLK, DCTRL) Fully controllable drive current CMOS I/O pads Single ended CMOS bidirectional, tri-state ESD protections Analog DACs 11 internal DACs for the Analog Front-Ends Decoding inside digital periphery Bandgap Voltage Reference ADC Temperature Sensing Power On Reset 14/9/

30 Data rate expected physics rates The actual data throughput generated by the ITS has been estimated by simulating the full behaviour of the detector with a system-c model (sensors and readout electronic) fed with actual data from the physics simulations. Pb-Pb p-p Layer Radius Prim. & sec. particles avg a Prim. & sec. particles max a QED electrons b Prim. & sec. particles avg c Prim. & sec. particles max c [mm] [cm -2 ] [cm -2 ] [10 5 cm -2 s -1 ] [cm -2 ] [cm -2 ] a) hit densities in a single Pb-Pb collision (minimum bias event, including secondaries due to material) max is for chip at η=0. b) for an integration time of 10 µs, a Pb-Pb interaction rate of 50 khz, a magnetic field of 0.2 T (worst case scenario) and p T > 0.3 MeV/c. c) hit densities in central p-p collision (including secondaries produced in material). ALICE ITS UPGRADE 30

31 Data rate Pb-Pb 100 khz, 10-6 px -1 noise sensor output Data rates from master chips. Rates are layer averages (max for η = 0 ). Simulation (entire ITS) in system-c and verification (single chip) with cycle-accurate System Verilog chip model. Layer Average fired pixels per event per sensor Total (η = 0 ) Physics (η = 0 ) (326) (224.1) (192.6) (141.0) (127.2) 71.0 (95.3) 4.8 (5.8) 3.0 (4.0) 3.3 (4.1) 2.7 (3.5) 1.9 (2.3) QED (1.8) 1.6 (1.8) 1.1 (1.3) Noise Average data rate per master [Mbit/s] Data rate breakdown Avg (η = 0 ) H & F 1% 1% 2% 24% 31% 42% 45% Region H 7% 9% 11% 17% 17% 15% 15% short/long 40% 43% 45% 57% 62% 69% 72% Cluster size/shape changes accordingly to the layer and the sensor position in the Data throughput from a single The data throughput from Middle and Outer layer chips is stave, ranging from 2.2 avg pixel (layer 6) master sensor. Available link that one of the data link connecting the master, i.e. to 3.7 avg pixels (layer 0). capacity is 960 Mb/s. represents the data flow of a group (master + 6 slaves). Available link capacity is 320 Mb/s. ALICE ITS UPGRADE 31

32 Triggered and Continuous Readout Modes Triggered Mode Short and randomly distributed strobing (integration) intervals Typical scenario: external trigger commands and duration Θ(100 ns) Strobe interval not generated on new triggers when MEBs are full. Priority to earliest triggers Busy violating trigger command acknowledged with Chip Empty Frame Continuous Mode Longer and periodic strobing intervals Duration Θ(1 us) or longer Flush oldest event when MEBs are becoming full and start new strobe interval. Give priority to latest framing interval Generation of STROBE Duration programmable 50 ns -> 1.6 ms (both modes) External commands or internal sequencer (both modes) BUSY status Triggered mode: MEBs full or periphery FIFOs almost full Continuous mode: MEBs almost full or periphery FIFOs almost full 14/9/

33 Chip Data Format Length Binary coding IDLE 8 bits 1111_1111 CHIP HEADER 16 bits 1010_<chip_id[3:0]>_<time_stamp[7:0]> CHIP TRAILER 8 bits 1011_<readout_flags[3:0] CHIP EMPTY FRAME 16 bits 1110_<chip_id[3:0]>_<time_stamp[7:0]> REGION_HEADER 8 bits 110_<region_id[4:0]> DATA_SHORT 16 bits 01_<hit_position[13:0]> DATA_LONG 24 bits 00_<hit_position[13:0]>_0_<hit_map[6:0]> BUSY_OFF 8 bits 1111_0000 BUSY_ON 8 bits 1111_0001 chip_id[3:0] Indexing of the chip in a module. time_stamp[7:0] BUNCH_COUNTER[10:3] region_id[4:0] Index of the region readout_flags[3:0] 0 BUSY_TRANSITION 1 FATAL (panic mode) 2 FLUSHED_FRAME (in continuous mode) 3 BUSY_VIOLATION (in triggered mode) hit_position[13:0] Location of pixel hit in the matrix hit_map[6:0] Topoogical hit map when clustering is used Refer to User Guide section in ALPIDE Operations Manual 14/9/2017 gianluca.aglieri.rinella@cern.ch 33

34 Chip Data Streams INNER BARREL (1200 Mbps) Chip Header HEA DER 0 HEA DER 1 IDL E REGIO N HEADE R IDL E IDL E TIME Hit Data Data Short DS 0 DS 1 IDL E Data Long DL 0 DL 1 DL 2 DS 0 DS 1 IDL E Chip Trailer TR AIL ER IDL E IDL E OUTER BARREL (400 Mbps) or IB (600/400 Mbps) Time Chip Header HEA DER 0 HEA DER 1 REGIO N HEADE R TIME Data Short DS 0 DS 1 Data Long DL 0 DL 1 DL 2 DS 0 DS 1 Chip Trailer TR AIL ER IDL E Data Bytes Refer to User Guide section in ALPIDE Operations Manual 14/9/2017 gianluca.aglieri.rinella@cern.ch 34

35 Bandwidth and Protocol utilization Bandwidth Used : 35.4 % of available Word Percentage of Bandwidth Used CHIP HEADER 0.28 % CHIP TRAILER 0.28 % DATA SHORT % DATA LONG % CHIP EMPTY FRAME 0 REGION HEADER 8.08 % BUSY ON % BUSY OFF % IDLE % 14/9/2017 gianluca.aglieri.rinella@cern.ch 35

36 Slow Control Refer to User Guide section in ALPIDE Operations Manual 14/9/

37 Inner Barrel Module 14/9/

38 Outer Barrel Modules (2) 14/9/

39 Outer Barrel Module (3), Local Buses 14/9/

40 Power [mw] ALPIDE Power Estimates mw mw Local Bus 21.8 DTU Digital Analog mw Inner Barrel Mode Master Chip Mode Slave Chip Mode Inner Barrel: 34 mw/cm 2 Outer Barrel: 18.5 mw/cm 2 Digital power estimates with highest design occupancy and readout rate Low Power Techniques Front-end transistors operating in weak inversion Clock gating in digital periphery Clock enabled on detection of SEU errors for synchronous correction 14/9/2017 gianluca.aglieri.rinella@cern.ch 40

Priority Encoders, PAD cells Double columns and PEs connected by abutting

41 Priority Encoder Double Column Priority Encoder Matrix Integration Matrix implemented with digital-on-top flow Building blocks: Double Pixel Columns, Priority Encoders, PAD cells Double columns and PEs connected by abutting Placement, power mesh, routing of pixels configuration wires 14/9/

arxiv: v1 [physics.ins-det] 26 Nov 2015

arxiv: v1 [physics.ins-det] 26 Nov 2015 arxiv:1511.08368v1 [physics.ins-det] 26 Nov 2015 European Organization for Nuclear Research (CERN), Switzerland and Utrecht University, Netherlands E-mail: monika.kofarago@cern.ch The upgrade of the Inner