Applications. Package Code. Temp. Range. I : - 40 to 85 C. Handling Code. XXXXX - Date Code. XXXXX - Date Code

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1 Class AB Stereo Headphone Driver with Mute Features Applications High Signal-to-Noise Ratio High Slew Rate Low Distortion Large Output Voltage Swing Flexible Mute Function Excellent Power Supply Ripple Rejection Low Power Consumption Short-circuit Elimination Wide Temperature Range No Switch ON/OFF Clicks Integrated Voltage Divider ( /) to Eliminate External Resistors Portable Digital Audio General Description The APA354/4 is an integrated class AB stereo headphone driver contained in an SO-8 or a DIP-8 plastic package with Mute feature. Besides the common Mute feature, the APA354/4 further integrates a voltage divider inside the chip. Thus, the external resistors can be eliminated. The APA354 has a fixed gain of 0dB and the APA3544 has a fixed gain of 6dB so that external gain setting is unnecessary. The device is fabricated in a CMOS process and has been primarily developed for portable digital audio applications. Ordering and Marking Information APA354/4 Handling Code Temp. Range Package Code Package Code J : PDIP - 8 K : SOP - 8 Y : Chip From Temp. Range I : - 40 to 85 C Handling Code TU : Tube TR : Tape & Reel APA354/4 J : APA354/4 XXXXX XXXXX - Date Code APA354/4 K : APA354/4 XXXXX XXXXX - Date Code ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Rev. B. - Apr., 003

2 Block Diagram MUTE Out A 8 Mute 0dB (6dB) A + B + 0dB (6dB) 7 Out B Input A 3 80kΩ (90kΩ) 80kΩ (90kΩ) BIAS V SS BIAS Input B * The values in parenthessis are for the APA3544. Function Pin Description Pin Name I/O Function Description Out A O A channel output pin Mute I Chip disable control input, low active and high for normal operating Input A I A channel input terminal V SS Power ground pin Input B I B channel input terminal BIAS I Right channel bias input pin OUT B O B channel output pin Power input pin Absolute Maximum Ratings Symbol Parameter Rating Unit Supply Voltage 7 V t SC(O) Output Short-circuit Duration, at T A =5 C, P tot =W 0 S T A Operating Ambient Temperature range -40 to 85 C T J Maximum Junction Temperature 50 C T STG Storage Temperature Range -65 to +50 C T S Soldering Temperature,0 seconds 300 C V ESD Electrostatic Discharge to 3000 * V Note:. Human body model : C=00pF, R=500Ω, 3 positive pulses plus 3 negative pulses

3 Thermal Characteristics Symbol Parameter Rating Unit R THJA R THJC Thermal Resistance from Junction to Ambient in Free Air DIP-8 SOP-8 Thermal Resistance from Junction to Case DIP-8 SOP K/W K/W Electrical Characteristics V IN =0dBV, V CC =5V, T A =5 C, f=khz, (unless otherwise noted) Symbol Parameter Test Condition APM354/4 Min. Typ. Max. Unit VDD Supply Voltage V IQ Quiescent Current VIN= 0 Vrms ma Imute Mute Current 00 µa VTM Mute Terminal Voltage V GVCL Differential Channel Voltage Gain db GVCL Voltage Gain Vin=Vrms,f= khz,rl APA354-0 Vin=0.5Vrms, f=khz,rl APA db THD Total Harmonic Channel Distortion Factor BW<80kHz % PU Rated Output Power RL,THD+N=0.%,BW<8 APA kHz APA mw PU Rated Output Power RL=6Ω,THD+N=0.%,BW<8 APA kHz APA mw VNO Output Noise Voltage BW=0~0kHz, Vin=0Vrms dbv CS Channel Separation F=kHz APA APA db ATT Mute Attenuation VIN=Vrms,f=kHz,Mute=L db RR Ripple Rejection FRR=00Hz,VRR=-0dBV db 3

4 Test and Application Circuit µ F 0µ F V INB 0µF Input B BIAS Out B µ F BIAS + B 0dB(6dB) APA354 (APA3544) + A 0dB(6dB) MUTE 4 3 V SS Input A Mute Out A 0µ F µ F 00kΩ V INA V MUTE µ F H : Speaker Action L : Mute on 4

5 Typical Characteristics Quiescent Current : I Q (ma) MUTE : OFF MUTE : ON Bias DC Voltage :V bias (V) Figure : Supply Voltage : (V) Figure : Supply Voltage : (V) APA354 Output Voltage : V OUT (dbv) =5V V IN =0dBv f = khz Voltage Gain : G VC (db) =5V V IN =0dBv k 0k 00k Figure 3 : Mute Control Voltage : V TM (V) Figure 4 : Frequency :f (Hz) 5

6 Typical Characteristics Cont. Total Harmonic Distortion : THD+N (%) = 5V BW< 80kHz f =0kHz f =khz, 00Hz Figure 5 : Output Voltage : V OUT (dbv) Total Harmonic Distortion : THD+N (%) 0 5 = 3V R L BW< 80kHz f =0KHz f =KHz, 00Hz Output Voltage : V OUT (dbv) Figure 6 : Total Harmonic Distortion : THD+N (%) 0 5 = 5V R L =6Ω BW< 80kHz f =0kHz f =khz, 00Hz Total Harmonic Distortion : THD+N (%) = 3V =6Ω BW< 80kHz f =0kHz f =khz, 00Hz Figure 7 : Output Voltage : V OUT (dbv) Figure 8 : Output Voltage : V OUT (dbv) 6

7 Typical Characteristics Cont. Channel Separation : CS (db) =5V k 0k 00k Mute Attenuationt : ATT(dB) +0-0 =5V V IN =0dBv k 0k 00k Figure 9 : Frequency :f (Hz) Figure 0 : Frequency :f (Hz) 0 Ripple Rejection : RR (db) f RR =00Hz V RR =-0dBv Figure : Supply Voltage : (V) 7

8 Application Note Input Capacitor, Ci In the typical application an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, the external capacitor Ci and the internal resistance Ri form a high-pass filter with the corner frequency determined in the follow equation: fc (highpass)= / (πrici) () The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the APA354 where Ri is 80kΩ and APA3544 is 90kΩ internal fixed. Equation is reconfigured as follow: Ci= /(π*80kω*fc) for APA354 Ci= /(π*90kω*fc) for APA3544 () And the ceramic capacitor is recommanded. Bias Capacitor, Cb As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger half supply bias capacitor is improved PSRR due to increased half-supply stability. Typical applications employ a 5V regulator with 0µF and a 0. µf bias capacitors which aid in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA354/4. The selection of bias capacitors, especially Cb, is thus dependent upon desired PSRR requirements, click and pop performance. The capacitor is fed from a 95kΩ source inside the amplifier. To keep the start-up pop as low as possible, the relationship shown in equation should be maintained. /(Cb*95kΩ) /{Ci*Ri} (3) As an example, consider a circuit where Cb is 4.7µF, Ci is µf and APA354 Ri is 80kΩ. Inserting these values into the equation we get which satisfies the rule. Bias capacitor, Cb, values of.µf to 0µF ceramic or tantalum low-esr capacitors are recommended for the best THD and noise performance. Output Coupling Capacitor, Cc In the typical single-supply SE configuration, an output coupling capacitor (Cc) is required to block the DC bias at the output of the amplifier thus preventing DC currents in the load. As with the input coupling capacitor, the output coupling capacitor and impedance of the load form a high-pass filter governed by equation. fc(highpass)= /(π Cc) (4) For example, a 0µF capacitor with an 3Ω speaker would attenuate low frequencies below Hz. The main disadvantage, from a performance standpoint, is the load impedance is typically small, which drives the low-frequency corner higher degrading the bass response. Large values of Cc are required to pass low frequencies into the load. Optimizing Depop Circuitry When the amplifier is in mute mode, both of the output stage and input bypass continues to be biased. And no pop noise will be heard during the transition out of mute mode. Power Supply Decoupling, Cs APA354/4 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different type capacitors that target on different type of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.µF placed as close as possible to the device V lead works best. For filtering lowerfrequency noise signals, a large aluminum electro- DD lytic capacitor of 0µF or greater placed near the audio power amplifier is recommended. 8

9 Packaging Information PDIP-8 pin ( Reference JEDEC Registration MS-00) D E E A L A A E3 e e 3 e Dim Millimeters Inches Min. Max. Min. Max. A A A D e.54bsc 0.00BSC e e E 7.6 BSC BSC E E L φ 5 5 9

10 Packaging Information SOP-8 pin ( Reference JEDEC Registration MS-0) E H 0.05X45 e e D A A 0.004max. L Dim Millimeters Inches Min. Max. Min. Max. A A D E H L e e.7bsc 0.50BSC φ 8 8 0

11 Physical Specifications Terminal Material Solder-Plated Copper (Solder Material : 90/0 or 63/37 SnPb) Lead Solderability Meets EIA Specification RSI86-9, ANSI/J-STD-00 Category 3. Reflow Condition (IR/Convection or VPR Reflow) Reference JEDEC Standard J-STD-00A APRIL 999 temperature Pre-heat temperature 83 C Peak temperature Classification Reflow Profiles Time Convection or IR/ VPR Convection Average ramp-up rate(83 C to Peak) 3 C/second max. 0 C /second max. Preheat temperature 5 ± 5 C) 0 seconds max Temperature maintained above 83 C seconds Time within 5 C of actual peak temperature 0 0 seconds 60 seconds Peak temperature range 0 +5/-0 C or 35 +5/-0 C 5-9 C or 35 +5/-0 C Ramp-down rate 6 C /second max. 0 C /second max. Time 5 C to peak temperature 6 minutes max. Package Reflow Conditions pkg. thickness.5mm and all bgas pkg. thickness <.5mm and pkg. volume 350 mm³ pkg. thickness <.5mm and pkg. volume < 350mm³ Convection 0 +5/-0 C Convection 35 +5/-0 C VPR 5-9 C VPR 35 +5/-0 C IR/Convection 0 +5/-0 C IR/Convection 35 +5/-0 C

12 Reliability test Program Test item Method Description SOLDERABILITY MIL-STD-883D C, 5 SEC HOLT MIL-STD-883D Hrs 5 C PCT JESD--B, A0 68 Hrs, 00 % RH, C TST MIL-STD-883D C ~ 50 C, 00 Cycles ESD MIL-STD-883D VHBM > KV, VMM > 00V Latch-Up JESD 78 0ms, I tr > 00mA Carrier Tape & Reel Dimensions t E Po P P D W F Bo Ao D Ko T J A C B T Application A B C J T T W P E SOP ± ± ± 0. ± 0. ± ± 0..75±0. F D D Po P Ao Bo Ko t 5.5± ± 0..0 ± ± 0. 5.± 0..± ±0.03

13 Cover Tape Dimensions Application Carrier Width Cover Tape Width Devices Per Reel SOP Customer Service Anpec Electronics Corp. Head Office : 5F, No. Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : Fax : Taipei Branch : 7F, No. 37, Lane 35, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : Fax :

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