APL431L. General Description. Applications. Symbol. Functional Diagram. Low Voltage Adjustable Precision Shunt Regulator

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1 Low Voltage Adjustable Precision Shunt Regulator Features Precise Reference Voltage to 1.24V Guaranteed.5% or 1% Reference Voltage Tolerance Sink Current Capability, 8uA to 1mA Quick Turn-on Adjustable Output Voltage, V O = V REF to 2V Low Operational Cathode Current, 8µA Typical.1Ω Typical Output Impedance SOT-23-3, SOT-23-5, TO-92 and SOT-89 Packages Lead Free Available (RoHS Compliant) General Description The APL431L is a 3-terminal low voltage adjustable precision reference with specified thermal stability over applicable commercial temperature ranges. Output voltage may be set to any value between V ref (1. 24 V) and 2 V with two external resistors (see Figure 2). When used with an photocoupler, the APL431L is an ideal voltage reference in isolated feedback circuits for 3V to 12V switching-mode power supplies. This device has a typical output impedance of.1ω. Active output circuitry provides a very sharp turn-on characteristic, making the APL431L excellent replacements for zener diodes in many applications, including on-board regulation and adjustable power supplies. ANODE 3 NC 5 NC 4 Applications Linear Regulators Adjustable Power Supply Switching Power Supply Symbol 1 2 REF CATHODE SOT-23-3 (Top View) 3 CATHODE 2 ANODE 1 REF TO-92 (Top View) REF ANODE CATHODE SOT-23-5 (Top View) REF ANODE CATHODE SOT-89 (Top View) REF Functional Diagram Anode Cathode Cathode REF + _ Vref ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Anode 1

2 Ordering and Marking Information APL431L APL431L A/B : 431L Lead Free Code Handling Code Temp. Range Package Code Elec. Grade Elec. Grade A :.5% Reference Voltage Tolerance B : 1% Reference Voltage Tolerance Package Code A : SOT-23-3 B : SOT-23-5 D : SOT-89 E : TO-92 Y:Chip Form Temp. Range C : to 7 C I : -4 to 85 C Handling Code PB : Plastic Bag TB : Tape & Box TR : Tape & Reel Lead Free Code L : Lead Free Device Blank : Original Device APL431L E : APL 431L XXXXX XXXXX - Date Code APL431L D : APL431L XXXXX XXXXX - Date Code Notes: ANPEC lead-free products contain molding compounds/die attach materials and 1% matte in plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-2C for MSL classification at lead-free peak reflow temperature. Absolute Maximum Ratings Symbol Parameter Rating Unit Cathode voltage 2 V I K Continuous cathode current range 1 ma I REF Reference current range 3 ma θ JA Thermal Resistance from Junction to Ambient in Free Air C/W SOT-23-3 SOT-23-5 SOT-89 TO T J Operating Junction Temperature Range -4 to 15 C T STG Storage Temperature Range -65 to 15 C T SOL Lead temperature range, T s (Soldering, 1sec) 26 C 2

3 Figure 2. Test Circuit for V >V, APL431L Electrical Characteristics T A = 25 C ( unless otherwise noted) APL431L Symbol Parameter Test Conditions Min. Typ. Max. =V REF, I K =1mA APL431LA T A =25 C, (Fig. 1) APL431LB V REF Reference voltage T A =full range(see APL431LA Note1), (Fig.1) APL431LB V DEF V DEF Temp Deviation T A =full range (see Note1) =V REF, I K =1mA (Fig. 1) 5 15 Unit V mv V REF / I REF(DEV) Ratio of Change in V REF to Change in Cathods Votage I K =1mA, =16V to V REF (Fig. 2) mv/v I REF Reference Input Current I K =1mA,R 1 =1kΩ,R 2 = (Fig. 2).15.5 µa T K =full range (see Note 1), I REF Temp Deviation R 1 =1kΩ, R 2 =, I K =1mA,.5.3 µa (Fig. 2) I K(off) off-state cathode current V REF =V, (Fig. 3) V K =6V.1.1 V K =16V.1.5 µa Z KA Dynamic Output =V REF, I K =1mA to 1mA, Impedance f 1kHz (Fig. 1).1.4 Ω I K(MIN) Minimum Operating Current =V REF (Fig. 1) 8 1 µa Notes : 1.Full temperature range is C to 7 C for APL431LXXC,and -4 C to 85 C for APL431LXXl. Test Figures VIN Vo VIN Vo IK IK(off) VREF Figure 1. Test Circuit for =V REF, V O = =V REF Figure 3. Test Circuit for I K(off) 3

4 Test Figures (Cont.) Application Schematic VIN R1 IREF IK Vo Precision Voltage Reference V IN R B V o R2 VREF R 1 V REF.1µ F R 2 Figure 2. Test Circuit for >V REF, V O = = V REF (1+R 1 /R 2 ) + I REF R 1 Precision High-Current Series Regulator V IN V o R B R 1.1µ F V REF R 2 Notes for Application Circuits: 1) To improve the stability of output voltage, a.1µf capacitor between cathode and anode of APL431L is strongly recommended. 2)Set VOUT according to the following equation: VOUT = VREF(1+R1/R2)+lREF R1 3)Choose the value for RB as follows: A)The maximum limit for RB should be such that the cathode current(lk) is greater than the mini mum operating current (8µA) at VIN(MIN). B)The minimum limit for RB should be such that the cathode current (lk) does not exceed 1mA under all load conditions, and the instantaneous turnon value for lk does not exceed 15mA. Both of the following conditions must. be met: VIN(MAX) RB,Min 15mA (to limit instantaneous turn-on lk) VIN(MAX)-VOUT RB,Min lout(min)+1ma (to limit lk under normal operating conditions) 4

5 Typical Characteristics Cathode Current vs. Cathode Voltage Cathode Current vs. Cathode Voltage 25 1 Cathode Current (µa) =V REF T A =25 C Cathode Current (ma) 5-5 =V REF T A =25 C Cathode Voltage (V) Cathode Voltage (V) Reference Voltage (V) I KA =1mA Referemce Voltage vs. Junction Temperature Reference Input Current (µa) Reference Input Current vs. Junction Temperature I KA =1mA R 1 =1kΩ, R 2 = Junction Temperature ( C) Junction Temperature ( C) 5

6 Typical Characteristics Ratio of Delta Reference Voltage to Delta Cathode Voltage (-mv/v) V REF / vs. Junction Temperature -.1 I KA =1mA V -.2 KA =V REF to 2V Junction Temperature ( C) Off State Cathode Current (µa) Off State Cathode Current vs. Junction Temperature.5 V REF =V =16V =6V Junction Temperature ( C) 3V Input I KA =1mA T A =25 C 3V Input I KA =.1mA T A =25 C 1V Output 1V Output µ S 5µ S µ S 5µ S 6

7 Typical Characteristics Gain vs. Phase Shift vs. Frequency Zka vs. Frequency Gain (db) I KA =1mA T A =25 C Phase Shift (degree) Zka (Ω) I KA =1mA =V REF T A =25 C Frequency (Hz) Frequency (Hz) Stability Boundary Conditions 1 9 Unstable =V REF T A =25 C Ik (ma) =2.5V =3.3V Stable Load Capacitance (µf) 7

8 Package Information SOT-23 D B 3 E H 1 2 e A A1 L C Dim Millimeters Inches Min. Max. Min. Max. A A B C D E e 1.9/2.1 BSC.75/.83 BSC H L

9 Package Information SOT-23-5 e1 5 4 E1 E e b D A2 A a L 1 A1 L 2 L Dim Millimeters Inches Min. Max. Min. Max. A A A b D E E e.95bsc.37bsc e1 1.9BSC.74BSC L L1.2 BSC.8 BSC L N 5 5 α 1 1 9

10 Package Information TO-92 3 J e e1 2 D 1 S L1 b2 b Q S A L E SEATING PLANE Millimeters Inches Dim Min. Max. Min. Max. A φ b φ b φ D E e e J L L Q S

11 Package Information SOT-89 (Reference EIAJ ED-75A Reg stration SC-62) D D1 a H E L B1 e B C e1 A a Dim Millimeters Inches Min. Max. Min. Max. A B B C D D e 1.5 BSC.59 BSC e1 3. BSC.118 BSC E H L α

12 Physical Specifications Terminal Material Solder-Plated Copper (Solder Material : 9/1 or 63/37 SnPb), 1%Sn Lead Solderability Meets EIA Specification RSI86-91, ANSI/J-STD-2 Category 3. Reflow Condition (IR/Convection or VPR Reflow) T P Ramp-up tp Critical Zone T L to T P T L Temperature Tsmax Tsmin t L Ramp-down ts Preheat 25 t 25 C to Peak Classificatin Reflow Profiles Time Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Large Body Small Body Large Body Small Body Average ramp-up rate (T L to T P ) 3 C/second max. 3 C/second max. Preheat - Temperature Min (Tsmin) 1 C 15 C - Temperature Mix (Tsmax) 15 C 2 C - Time (min to max)(ts) 6-12 seconds 6-18 seconds Tsmax to T L - Ramp-up Rate 3 C/second max Tsmax to T L - Temperature(T L ) - Time (t L ) 183 C 6-15 seconds 217 C 6-15 seconds Peak Temperature(Tp) 225 +/-5 C 24 +/-5 C 245 +/-5 C 25 +/-5 C Time within 5 C of actual Peak Temperature(tp) 1-3 seconds 1-3 seconds 1-3 seconds 2-4 seconds Ramp-down Rate 6 C/second max. 6 C/second max. Time 25 C to Peak Temperature 6 minutes max. 8 minutes max. Note: All temperatures refer to topside of the package. Measured on the body surface. 12

13 Reliability Test Program Test item Method Description SOLDERABILITY MIL-STD-883D C, 5 SEC HOLT MIL-STD-883D Hrs C PCT JESD-22-B,A Hrs, 1%RH, 121 C TST MIL-STD-883D C~15 C, 2 Cycles ESD MIL-STD-883D VHBM > 2KV, VMM > 2V Latch-Up JESD 78 1ms, 1 tr > 1mA Carrier Tape & Reel Dimensions t E Po P P1 D W F Bo Ao D1 Ko T2 J A C B T1 13

14 Carrier Tape & Reel Dimensions Application A B C J T1 T2 W P E 178 ±1 7 ± ±.15 3 ± ± ± ± ±.1 SOT-89 F D D1 Po P1 Ao Bo Ko t 5.5 ±.5 1.5±.1 1.5±.1 4. ±.1 2. ± ±.1 4.5±.1 1.8±.1.3±.13 Application A B C J T1 T2 W P E 178±1 6 ± ± ± SOT-23 F D D1 Po P1 Ao Bo Ko t 3.5 ± φ.1min ± ±.3 Application A B C J T1 T2 W P E 178 ±1 72 ± ± ± ±.3 8. ±.3 4 ± ±.1 SOT-23-5 F D D1 Po P1 Ao Bo Ko t 3.5 ±.5 1.5±.1 1.5±.1 4. ±.1 2. ± ±.1 3.2±.1 1.4±.1.2±.33 Carrier Tape & Reel Dimensions H2 H2 H2A H2 D2 A L L1 H3 W2 H4 H W1 H1 W D T2 T T1 F1F2 P1 P P2 D1 Application A D D1 D2 F1,F2 H H1 H2 H2A 3.18~12 4.±.2.36~ MAX ±.5 9±.5.5 MAX.5 MAX H3 H4 L L1 P P1 P2 T T1 TO MAX 2. MAX 11. MAX 2.5 MIN 12.7± ±.4 5.8±.5.55 MAX 1.42 MAX T2 W W1 W2.36~ ~19 5.~7..5 MAX 14 (mm)

15 Cover Tape Dimensions Application Carrier Width Cover Tape Width Devices Per Reel SOT SOT SOT TO ~19 5.~7. 2 Customer Service Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : Fax : Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : Fax :