Mixed-Signals Integrated Circuits for Physical Experiments

Transcription

1 Università degli Studi di Pavia Facoltà di Ingegneria Dipartimento di Ingegneria Industriale e dell Informazione Doctoral Thesis in Microelectronics XXVIII Cycle Mixed-Signals Integrated Circuits for Physical Experiments Supervisor: Chiar.mo Prof. Andrea Baschirotto Chiar.mo Prof. Piero Malcovati Coordinator: Chiar.mo Prof. Franco Maloberti Author: Tommaso Vergine October 2015

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3 UNIVERSITÀ DEGLI STUDI DI PAVIA Abstract Facoltà di Ingegneria Dipartimento di Ingegneria Industriale e dell Informazione Doctor of Philosophy Mixed-Signals Integrated Circuits for Physical Experiments by Tommaso Vergine CMOS integrated circuits are more and more used in High-Energy Physics experiments. Even though this approach is characterized by lacking of reconfigurability and portability, it brings several advantages. First of all, costs reduction and performance improvement. Nevertheless, the electronic circuits which are exposed to high radiation levels may suffer some undesirable effects. In some cases they can even undergo breakdown events. Some radiation-hard technologies are already available but they are generally very expensive. For example, hardened integrated circuits are manufactured using insulated substrates rather than usual semiconductor wafers. Silicon on insulator (SOI) and sapphire (SOS) are often used. While normal commercial-grade chips can withstand between 50 and 100 gray (5 and 10 krad), space-grade SOI and SOS chips can survive doses many orders of magnitude greater. Furthermore, the package shielding can reduce the radiation exposure of the bare device[1]. Alternatively, another approach to design hardened circuits in commercial-grade technologies is adopting specific methodologies, involving both design and layout techniques[2]. In this work, high-accuracy mixed-signals radiation-hard ICs for physical experiment are presented. In particular, a 12 bit Single-Slope digitally calibrated A/D converter and a BandGap voltage reference will be shown. They will be part of the next LHC (Large Hadron Collider) experiments upgrades, at CERN in Geneva (Switzerland)[3]. In particular, they are going to be part of a radiation tolerant, monitoring and controlling ASIC, called GBT-SCA (Giga Bit Transceiver - Slow Control Adapter)[4]. The aim of this ASIC is to provide real-time information about the status of silicon detectors.

4 Indeed, monitoring quantities like temperature, leakage currents, supply voltages and so on can significantly increase lifetime and performance of HEP (High Energy Physics) experiments integrated circuits.

5 Acknowledgements I would like to express my gratitude to both Prof. Piero Malcovati and Prof. Andrea Baschirotto, for the professional and constant support at all stages of my Ph.D. I would like to thank Marcello De Matteis for his advices during the research activity carried on in the laboratory of Microelectronics at the University of Milano Bicocca. Thanks also to all people of the Microelectronics Section of CERN, in particular I have to thank Alessandro Marchioro, Kostas Kloukinas, Sandro Bonacini, Stefano Michelis and Alessandro Caratelli for their precious support. I take this opportunity to thank also all the people which I worked with during these three years of professional and personal growth. Thank you all! Tommaso. v

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7 Contents Abstract Acknowledgements iii v Contents List of Figures List of Tables vi ix xi Introduction 1 1 System Overview GBT-SCA Architecture Radiation-matter interaction Charged Particles Neutral Particles Radiation Effects on CMOS transistors Threshold Voltage shift Leakage Current Radiation effects in microelectronic circuits Radiation-hard electronics by design A digital-calibrated rad-hard ADC for CMS Central Tracker Introduction ADC Architecture Input Biasing and multiplexing Ramp Generator Clocked Comparator Digital Calibration Offset Error Correction Gain Error Correction Experimental Results The ADC Technology Porting vii

8 Contents viii Clocked Comparator Offset Calibration Ramp Generator Simulation Results Rad-Hard BandGap Voltage Reference Introduction Rad-hard Layout: Enclosed vs. Conventional Approach BandGap Voltage Reference Circuit Operational Amplifiers Design Bias and Startup Circuits Simulation Results BandGap Programmability Experimental Results Conclusions 59 A Automatic Calibration for Single-Slope A-to-D Converters A.1 Introduction A.2 Calibration Circuit A.3 Simulation Results A.4 Conclusions Bibliography 69

9 List of Figures 1.1 GBT-SCA block scheme [4] Ionizing radiation effects on a MOS device when the gate is positive biased Radiation effects on leakage currents in a linear transistor. Top-view (on the left) and along the line A-B (on the right) Ionizing particle inside a memory element.[5] CMOS parasitic thyristor, susceptible to SEU.[5] Radiation tolerant layout of an NMOS transistor Drain current for straight and enclosed gate transistors [5] Threshold voltage shift as function of device sizing and TID [6] Leakage current as function of device sizing and TID [6] SEU hardening with redundancy Single-Slope ADC block scheme Input Biasing circuit Channels input multiplexer Rad-Hard complementary switch Low Voltage Regulated Current Mirror (left) and Ramp Generator Circuit (right) Charging current vs Ramp Voltage A Class opamp Loop Gain and Phase Clocked comparator schematic Comparator offset for 15 mv input voltage Comparator offset for 500 mv input voltage Comparator offset for 985 mv input voltage Single slope ADC and calibration full block diagram Offset Cancellation block functionalities Positive Offset Digital Conversion Negative Offset Digital Conversion Positive Offset correction Negative Offset correction Gain correction basic principle Ramp Signals suitable for Digital Gain Correction ADC characteristics vs ramp slope nm ADC Layout SCA Chip with ADC analog part highlighting ix

10 List of Figures x 2.23 ADC Linearity Performance ADC Radiation Performance nm Clocked Comparator Complementary input stage for rail-to-rail operation Offset Voltage vs Input Signal Conversion Modified Ramp Generator Circuit Ramp Signal under PVT and Mismatch nm ADC Layout (analog part only) nm ADC Coarse Quantization Error nm ADC Transient Noise Simulation Bench with SEIFERT RP149 X-ray generator and probe station Enclosed-Layout Diode (3-D view) Enclosed-Layout Diode (Vertical view) Conventional Diode I-V Characteristic Enclosed-Layout Diode I-V Characteristic BandGap Voltage Reference Circuit Opamp Offset Contribution Symmetrical Operational Amplifier Biasing & start-up circuit BandGap output voltage - Nominal Conditions BandGap output voltages - Process and supply variations BandGap output voltage - Mismatch and supply variations BandGap Noise PSD Transient - process and supply variations Transient - mismatch and supply variations BandGap reference circuit layout BandGap output voltage vs. R 1 value BandGap output voltage vs. R 3 value Output voltage vs. temperature (for different configurations) Output mean voltage (for different configurations) Maximum output voltage deviation (for different configuration bit) Pre-Rad output voltage percent variation Output percent variation vs. TID A.1 Single-Slope A-to-D converter with automatic calibration circuit.. 63 A.2 Comparator s output duty-cycle vs. ramp signal slope A.3 Automatic Calibration algorithm A.4 Array Capacitor A.5 Example of Calibration A.6 Quantization error in ss, 120 o C corner A.7 Quantization error in ff, 120 o C corner A.8 Quantization error in ss, -40 o C corner A.9 Quantization error in ff, -40 o C corner

11 List of Tables nm ADC specifications Performance comparison nm ADC specifications BandGap reference performance comparison with similar radiationhard reference circuits A.1 Simulation Corners xi

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13 Dedicated to my wife Selenia and my parents Francesco and Leonarda, for their endless love and support... xiii

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15 Introduction Chapter 1 presents a brief overview of the application field and all those aspects related to the radiation exposure which arise in integrated circuits. Starting from these problematics, and their comprehension, it s possible to reach a certain level of radiation hardness, acting at both schematic and physical levels. Chapter 2 shows the design of a Single-Slope ADC in two different technology nodes (in order to follow the upgrading trend which characterizes the LHC experiments). This design has been characterized by the introduction of a digital calibration procedure which mitigates both the offset and the gain errors of the ADC. Acting in digital it allows a better radiation immunity, preserving power consumption and area wasting. However, in the Appendix A an alternative fully automatic procedure is shown. Chapter 3 shows the design of a BandGap voltage reference. It s characterized by a very strong radiation-hardness and gives the possibility to trim both the output absolute value and the temperature coefficient, in order to further compensate the variations introduced by process, mismatch and radiation effects. Conclusions will be drawn at the end of this book. 1

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17 Chapter 1 System Overview Semiconductor electronic devices can undergo significant changes in their performance and reliability if exposed to very high radiation level environment. This is what happens, for example, in outer space, high-altitude flight and near particle accelerator. Thus, it is very important to understand, basing on the different type of radiation-matter interaction, the effects generated inside semiconductor components and how to design circuits minimizing them. There are mainly two categories of radiation-induced effects: those related to long radiation-exposure (deterministic and caused by the radiation received during the device life-time) and those due to single events (stochastic and dependent on the energy of the hitting particle). This chapter will present, after a brief introduction on the system, an overview of the main effects which the radiation exposure generates inside integrated circuits and those mechanisms which are responsible. Highlighting the consequences of radiation on the main electrical parameters it s possible to identify the best way to obtain radiation-hardness by design. 1.1 GBT-SCA Architecture The rad-hard ICs which are going to be shown in this thesis have been thought as building blocks of a larger VLSI circuit, designed for the CMS central tracker, inside the LHC (Large Hadron Collider) experiment. Its name is GBT-SCA (Giga Bit Transceiver - Slow Control Adapter) and it is aimed to distribute control sequences and collect status information from the embedded peripheral electronics in the detector[4]. Fig. 1.1 shows the block scheme of the GBT-SCA. It s built up 3

18 Chapter 1. Radiation effects on integrated circuits 4 Figure 1.1: GBT-SCA block scheme [4]. on several blocks with different functions. The first work, which will be shown in the Chapt. 2, has been already integrated in the latest version of the GBT-SCA whereas its porting in a more scaled technology node (shown at the end of Chapt. 2) and the BandGap voltage reference (reported in Chapt. 3) will be integrated in the next system upgrades. Since the GBT-SCA will be placed very close to the detectors, it s evident that its design has to stand the huge amount of radiation produced by the LHC activity. For this reason it s very important to analyze the effects which radiation induces in electronic devices in order to find the better way to face them. All these aspects will be covered in the next paragraphs. 1.2 Radiation-matter interaction The effects which radiation induces inside a material depend on several parameters, related both to the incident particle and the material itself; the type, the kinetic energy, the mass and the charge are some examples. The radiation particles which

19 5 Chapter 1. Radiation effects on integrated circuits move inside a semiconductor structure can be divided in two groups: charged and neutral particles Charged Particles The particles which belong to this category are: protons, heavy ions and electrons. In this case, the interaction with the target particles takes place mainly thanks to the Coulomb attraction or repulsion. The following are the main interaction forms, organized according to the particle type. Protons and Heavy Ions: Coulomb interaction: it can induce ionizing or atomic excitation. Collision with nuclei: it can cause excitation or displacement. Nuclear reaction: it can occur for energy higher then 10MeV. Electrons: Coulomb interaction: the effects are the same highlighted for the Protons. Scattering with nuclei: it can cause the displacement of the matter s nuclei, if the energy of the incoming electron is high enough Neutral Particles The particles that instead belong to this category are: Neutrons and Photons. The main different between neutral and charged particles is that the formers don t experience the Coulomb force. The main interactions between neutral particles and the matter are: Neutrons: Nuclear reaction: the nuclei, absorbing neutrons, emits other particles (for example protons, α particles and γ photons). Elastic collisions: it happens when an incident neutron collides with a nucleus and continues its path. If the energy acquired by the nucleus is sufficiently high it can undergo a displacement, causing ionization.

20 Chapter 1. Radiation effects on integrated circuits 6 Inelastic collision: it s similar to the elastic collision with the addition that the excited nucleus emit gamma rays on its decay.. Photons: Photoelectric effect: the incident photon is completely absorbed by the ionized target atom while a photoelectric electron is emitted. Compton effect: the incoming energy is divided between the generated free electron and an emitted photon. Annihilation: creating an electron-positron pair 1.3 Radiation Effects on CMOS transistors The CMOS transistors, being devices which base their conduction on the flow of majority carriers, are almost insensitive to displacement damage. Indeed, the main effect related to this phenomena is a reduction of minority charges lifetime. On the other hand, the electron-hole pairs generated by ionizing particles inside oxides can significantly change the device behavior [7]. Although some of these pairs can quickly disappear in the gate and substrate (basically due to the quantum tunneling which facilitates the recombination process), some other can be kept separated and follow different paths inside the gate oxide, under the influence of the electrical field (which can be present also without an applied external biasing). Indeed, the electrons, highly movable charges, are easily swept out from the oxide whereas the holes, being slower, move towards the SiO 2 -Si interface. Some of these holes can be trapped in the lattice imperfections, originating this way a fixed positive charge in the oxide. But, another effect of the ionizing radiation is the creation of traps at the SiO 2 -Si interface, as shown in Fig. 1.2 [8]. The probability of having trapped positive charge in the oxide next to the silicon interface depends directly on the number of defect in the oxide and the holes capture cross-section. For this reason, radiation hardened electronic process give special attention to the quality of the gate oxide. The purpose of this paragraph is to highlight the consequences on MOS transistors electrical parameters generated by the trapped holes inside oxides and the interface traps generation.

21 7 Chapter 1. Radiation effects on integrated circuits Figure 1.2: Ionizing radiation effects on a MOS device when the gate is positive biased Threshold Voltage shift After the irradiation, the threshold voltage of a MOS transistor can change and this change is due to both the positive charges trapped in the oxide ( V OX ) and to the charge of the interface traps ( V IT ). This threshold voltage shift is mainly due to the shift in the flat-band voltage. The threshold voltage shift can be expressed as in Eq. 1.1 [9] V OX = 1 C OX tox 0 x t OX ρ(x)dx (1.1) where t OX is the thickness of the gate oxide, C OX is the capacitance per unit area and ρ(x) is the charge distribution in the oxide per unit volume, as function of the distance from the gate-oxide interface (x). As it can be seen, 1.1, the voltage shift is negative when the trapped charges are positive. In a PMOS transistor these positive trapped charges repel the holes in the channel so, to establish the same inversion condition, a more negative gate potential is needed. This means that the threshold voltage is lower (higher in absolute value). On the other hand, NMOS devices experience a reduction of the threshold voltage. Regarding the threshold voltage shift due to the radiation-induced traps at the interface between SiO 2 and Si ( V IT ) it is increased, both for PMOS and NMOS. The charge distribution at the oxide can be considered bi-dimensional and expressed as V IT = Q IT C OX, where Q IT is the charge difference, per unit area, which fills the interface states

22 Chapter 1. Radiation effects on integrated circuits 8 Figure 1.3: Radiation effects on leakage currents in a linear transistor. Top-view (on the left) and along the line A-B (on the right). before and after the irradiation. Since the interface state creation is anyway a slower phenomena the NMOS transistors experience an initial threshold voltage reduction followed by a definitely increase. It s worth to be said that, especially in more scaled technologies, the thinner gate oxide makes the radiation-induced charge contribution negligible if compared with the effects of the interface states. For this reasons the NMOS transistor threshold voltage tends to increase in any case Leakage Current Another issue that arises when charges are trapped in the oxides is the generation of leakage currents (or their worsening). Generally, CMOS transistors are surrounded (for isolation reasons) by the STI (Shallow Trench Isolation) oxide, which doesn t scale with deeper technological nodes like the gate oxides[10]. Being the STI a relative thick oxide it can collect a large amount of positive charges, induced by radiation, and in particular for NMOS transistors, this can create a leakage current path between source and drain, as shown in Fig. 1.3 [11]. Adopting particular layout techniques, as it will shown in the next paragraphs, it is possible to remove any perimetral effect. For narrow channel transistors, the induced charge at the edges influences not only the conditions of the parasitic lateral transistor but also the electric field of the main one. This effect is known as narrow channel effect and it is more and more evident in deep submicron technologies. A way to reset the transistor at its original state is using the thermal annealing which can de-trap the radiation-induced positive traps and restore the damaged interface states.

23 9 Chapter 1. Radiation effects on integrated circuits 1.4 Radiation effects in microelectronic circuits The effects afore mentioned, i.e. the threshold voltage change and the leakage currents increase for CMOS transistors, are generally referred as Total Ionizing Dose (TID) effects. They arise by the aggregate interactions of a very large number of charged particles (protons or electrons) because the charge of a single particle is quite low. The radiation dose is generally indicated in rads, a measure unit defined as 0.01 J/kg, which quantify the amount of energy absorbed per unit of mass. The microelectronics pixel detectors inside the CMS are exposed, for example, to a dose of 10 Mrads/year. For this reason all the electronic circuits are designed with the aim to be robust up to more than 100 Mrad. This guarantee the right behavior for several years. The integrated circuit radiation exposure can also have effects other than the performance degradation, seen in the previous paragraphs. If an accumulated charge is collected in a sensitive node, inside a memory cell for example, the information stored can be lost [12]. Fig. 1.4 shows the core of a memory cell, storing an information; an accumulation of charge, if greater than a certain threshold value, on a sensing node can reverse the logic state of the cells. This is called soft error and represents a recoverable error, performing data rewriting or periodical resets. It can lead to invalid data or complete system failure, due to upsets in the state bits of the state machine. Nevertheless the charge accumulation, induced by ionizing particle, can be seriously dangerous. In Fig. 1.5 it is possible to see how the CMOS fabrication process creates parasitic structures (called thyristors) which are susceptible to single event [5]. If a small current, due to accumulation of induced charges, is injected on a base region can feed the positive loop with dramatic consequences: short-circuit current from voltage supply to ground that can easily damage the integrated circuits. These effects are generally referred Single Event Effects (SEE) or Single Event Upset (SEU). The probability of a bit upset is determined by two things: the energy of the hitting particle and the minimum amount of charge, needed to flip state for a storage element. SEU robustness is strongly dependent on the CMOS technology. A more downscaled technology implies more functionalities and, as a consequence, smaller devices. Thus, for a radiation particle is more difficult to hit a sensible node, due to its smaller area. On the other hand, the parasitic capacitances on these nodes is a smaller and then a less energy is required to cause a bit upset.

24 Chapter 1. Radiation effects on integrated circuits 10 Figure 1.4: Ionizing particle inside a memory element.[5] Figure 1.5: CMOS parasitic thyristor, susceptible to SEU.[5] 1.5 Radiation-hard electronics by design The radiation effects afore mentioned need different approach to be mitigated. In particular, the TID and SEU effects can be mainly seen as analog and digital issues, respectively. Indeed, the former tends to modify the device characteristics (e.g. the threshold voltage or the leakage current) whereas the latter becomes problematic when the charge which the radiation generates is collecting on critical nodes (for example in memory cells). However, it is possible to mitigate them acting both at schematic and layout level. As shown in Section 1.3, the main contributor the TID effects is the STI (Shallow Trench Isolation) thick oxide and the parasitic transistors which it creates at the edges of the main device. A possible solution is to enclose the drain/source diffusion within the gate oxide and the edge of channel, in what s called ELT (Enclosed Gate Transistor), as shown in Fig The advantage of such a structure is that the STI thick oxide doesn t touch both the transistor diffusions, forming this way a parasitic device. Obviously the radiation induced charge can generate leakage current between two ELT devices but this can be prevented using guardrings. Fig. 1.7 shows a performance

25 11 Chapter 1. Radiation effects on integrated circuits Figure 1.6: Radiation tolerant layout of an NMOS transistor. comparison between a conventional linear transistor and an ELT transistor. Fig. 1.8 and Fig. 1.9 compare an ELT NMOS transistor with several core devices, both in terms of threshold voltage and leakage current variations. It s clear that the wider is the transistor the lower is the contribution due to the STI and that the best performance is guaranteed by the enclosed devices. The ELT transistors have been widely used in High Energy Physics experiments, including CERN ([2]). Nevertheless the capability to be a rad-hard device, an ELT transistor pose a number of issues to the designer. First of all, the enclosed structure doesn t allow every W/L ratio and sometimes this isn t usually recognized by standard EDA tools (parasitic extraction can fail). Regarding the SEU the approach to mitigate them has to be different. At the schematic level there are several solution that can be adopted. For example it s possible to increase the parasitic capacitance of the sensitive nodes, paying in power consumption and area obviously. This increases the minimum amount of charge needed to upset a stored value. Another approach is to create circuital structure with several nodes that must be upset at once or, more diffusely, it s to add redundancy. This technique is generally referred as Triple Modular Redundancy (TMR) and consists in triplication the number of cells that store the information and then using a voter, so that a single upset will not corrupt the data. It s however important to take care about the layout; the redundant elements should not be placed close to each other, avoiding this way that an hitting particle can upset more than one cell at once. This approach is shown in Fig This technique is helpful especially for those systems in which periodical reset signals are frequent.

26 Chapter 1. Radiation effects on integrated circuits 12 Figure 1.7: Drain current for straight and enclosed gate transistors [5]. Figure 1.8: Threshold voltage shift as function of device sizing and TID [6].

27 13 Chapter 1. Radiation effects on integrated circuits Figure 1.9: Leakage current as function of device sizing and TID [6]. Figure 1.10: SEU hardening with redundancy.

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29 Chapter 2 A digital-calibrated rad-hard ADC for CMS Central Tracker Chapter 1 has shown how severe the radiation induced effects inside silicon devices can be. Indeed, CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. These consequences can be often followed by breakdown events. Thus, it s extremely important, in a radiation environment, to take care about the status and the right behavior of the integrated circuits. The ADC presented in this chapter is part of a bigger system in charge of sensing and monitoring of the particle detectors electrical/physical parameters, inside the LHC experiments at CERN. The ADC has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, especially considering the required conversion accuracy and the critical physical scenario. 2.1 Introduction Integrated microelectronic circuits are more and more used in high-energy physics experiments like those inside the LHC, at CERN.[13][14] Even thought this approach is characterized by reconfigurability and portability lacking, it brings several advantages. In fact, if compared with PCB-based circuits and programmable logic devices, the main advantages of integrated circuits are costs reduction, performance 15

30 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 16 improvement, better immunity to parasitic capacitance and EMI (ElectroMagnetic Interference). Although the technological scaling down process improves the radiation immunity, as shown in Chapter 1, a real-time monitoring of the environment in which the integrated devices work can be significantly helpful. An electrical/physical quantities monitoring (i.e. temperature, voltages and leakage currents) can increase by far the life-time and the performance of integrated circuits. The dedicated monitor system, the GBT-SCA (Giga Bit Transceiver - Slow Controller ASIC) shown in chapter 1, includes the ADC here presented to digitize this information. This approach can significantly increase lifetime and performance of integrated circuits. A single-slope (Wilkinson) architecture has been chosen for the ADC design. Although the quite long conversion time, typically required by this kind of converters, this choice appears the most reasonable for accuracy. Indeed, Wilkinson ADCs, first introduced in 1950 and widely used in precision pulse digitization systems, offer excellent differential linearity performance, efficient use of hardware and low power consumption.[15] The required conversion time does not represent an issue for this application because supply voltages, temperature and leakage currents variations (the quantities we want to digitize) are slower than the required conversion rate of 1 ks/s. Notice that, as it happens for detectors, also the ADC and the GBT-SCA are exposed to radiation. For this reason, they have to be radiation-hard. Combining the inherently radiation tolerant of the scaled CMOS technologies with some design solutions (both at circuital and layout level), it is possible to make an integrated circuit resistant to radiation exposure. Even if in this application the conversion time is not critical, the accuracy in terms of linearity, gain and offset are mandatory. This is because in this measurement path there is no control-loop for gain-error and offset (as in many receiver structures). For this reason, the proposed ADC has been designed as follows. High-accuracy analog design effort has been applied to the ramp generator in order to guarantee the target linearity (DNL<0.5b), while the offset and gain-error are compensated by a digital correction. Notice that this approach can be more expensive in terms of power consumption respect to an alternative system with a control-loop because the property of inaccuracy reduction performed by the loop itself is here lost.

31 17 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.1: Single-Slope ADC block scheme. 2.2 ADC Architecture In a Wilkinson ADC, the conversion is performed comparing the input value with a ramp signal, in a kind of voltage-to-time conversion. The longer is the time needed by the ramp to overcome the input signal, the higher is the conversion result. This ramp can be created in both continuous and discrete time. A very simple way is charging an integrating capacitor (C) with a fixed charging current (I charge ). If I charge is accurate and C is stable, the conversion result is proportional to the time needed to charge the capacitor from the ramp starting voltage (V start ) to the input voltage amplitude Vin. The conversion result is then proportional to Eq T conv = C (V in V start )/I charge (2.1) This kind of converters generally guarantees very high differential linearity, in particular with more precise clocks (for example low jitter) [5]. In this ADC topology, the ADC performance is strongly affected by ramp signal imperfections. In particular, there are mainly three contributors to the ADC performance: the afore-mentioned ramp signal linearity (that introduces non-linearity in terms of poor DNL/INL) and slope (that introduces gain error) and the offset voltage of the comparator (that introduces overall offset). These design aspects are then critical. In several applications, offset and gain errors are generally corrected by an overall feedback loop (like in telecommunication transceivers) while this is not the case of this application. Thus, it is important to calibrate the ADC as stand-alone device. The ramp slope and the comparator offset voltage are often compensated

32 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 18 Parameter Value # of channels 32 Resolution (bit) 12 Input Full Scale (V) 0 1 DNL (bit) < 1 INL (bit) < 2 Conversion Time (s) < 1m Power Consumption (mw) < 2 Supply Voltage (V) 1.5 Table 2.1: 130 nm ADC specifications. in the analog domain: tuning the external current or modifying the value of the integrating capacitance for the first (see Appendix A) and using the chopper or auto-zeroing techniques for the second [6][7]. Although these are relatively simple solutions, it could be the non-optimal choice for a scenario like that inside the LHC environment. Implementing the calibration in the digital domain can represent the solution, reducing the more radiation-susceptible analog circuitries. The block scheme of the proposed ADC is shown in Figure 1 whereas the most important ADC specifications are obtained by system-level considerations and are presented in Tab The ADC has to manage 32 different analog input signals with an input signal full-scale ranging from 0 V to 1 V. The maximum allowed power consumption is about 2 mw (from a single 1.5 V supply voltage) for a maximum DNL/INL lower than 1 bit and 2 bit, respectively. A multiplexer allows to handle a large number of input signals, as generally required by High-Energy Physics experiments. The Control Logic is in charge of the overall timing and control. As shown in the next paragraphs, swapping the comparator inputs helps to manage its offset voltage: this is the purpose of the Offset Cancellation block. The SOC signal is asynchronous and starts the digital conversion whereas the BUSY signal is an ADC activity flag Input Biasing and multiplexing The quantities that are being measured are mainly leakage currents and temperatures; it means that a way to convert this information into a voltage (the suitable signal to be converted by this kind of ADC) is needed. Regarding the leakage current it can be used to directly bias a resistor, providing this way the current to voltage conversion. Instead, for the temperature sensing a Negative Temperature

33 19 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.2: Input Biasing circuit. Figure 2.3: 32 Channels input multiplexer. Coefficient (NTC) thermistor can be used but, in this case, it needs to be biased. From system level consideration, it has been decided to bias this resistor with a 100 µa current. In Fig. 2.2 the overall biasing network is shown. It takes and mirrors an external current (with the appropriate mirroring factor) toward the ramp generator, the comparator circuit and 31 (of 32) multiplexer inputs. A set of switches allows to turn on and off this biasing functionality, giving the possibility to the final user to arrange the inputs in the most suitable way. The current mirror have been designed in their low-voltage cascode version, in order to increase their accuracy also with low value voltage supplies. The 32 Channel Input multiplexer has been realized with 31 2:1 demultiplexers, in a 5-bit controlled decoder structure, which

34 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 20 Figure 2.4: Rad-Hard complementary switch. minimizes the unwanted effects of the unselected channels (i.e. leakage currents and noise). Each demultiplexer has been designed as a network of complementary switches, in order to minimized the on-resistance and, consequently, the input settling time. This is show in Fig In Fig. 2.4 is instead show the realized layout of each 2:1 demultiplexer. All the PMOS devices and the digital cells (like the inverters) have been laid out as linear structure whereas the NMOS transistors (those which undergo significant radiation-induced effects) with an enclosed-gate layout Ramp Generator The ramp generation represents one of the most critical aspects in a single-slope (Wilkinson) ADC. Fundamentally, the number of clock periods needed by the ramp signal to overcome the input signal constitutes the digital conversion result. It s evident that any deviation from the ideal characteristic in the ramp generator can easily degrade the ADC accuracy (both a different slope and a poor linearity). Being the input signal to be converted ranges from 0 V to 1V a ramp signal ranging from 0V to 1V is needed too. The simplest way to obtain such a signal is charging a grounded (reset) capacitor with a very accurate current. The current source has to exhibit an output resistance in the GΩ order to minimize the charging current lost (in the output impedance) and the ramp non-linearity. To obtain such a value, a low-voltage regulated cascode current mirror has been designed, as shown on the left in Fig [16] The introduced negative loop increases the output resistance

35 21 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.5: Low Voltage Regulated Current Mirror (left) and Ramp Generator Circuit (right). and keeps stable the operating point of the transistor M3, when M4 drain changes between 0 V and 1 V. This approach guarantees an output resistance of about 6GΩ over the full ramp swing. Indeed, the charging current, shown as function of the M 4 drain voltage, has only a 0.029% variation for all the input full-scale. This guarantees a very high ramp linearity which directly determines the ADC linearity performance. The operational amplifier (A Class) has been designed with 55 db and 2 MHz of DC-gain and bandwidth, respectively (see Fig. 2.7). The former parameter further increases the output resistance in the opamp bandwidth whereas the second reduces the settling time of the internal nodes, during the startup procedure. Fig. 2.5 shows also the whole ramp generator circuit, on the right part. A NMOS switch deviates the charging current and resets the 100 pf integrating capacitor. The capacitance value is such that the non-linear parasitic capacitance of the comparator inputs does not degrade the ramp linearity. In addition, the charge injection occurring at the switch-opening, at the beginning of the ramp generation, is negligible; it would be a residual offset, eventually corrected by the offset cancellation. A lower parasitic capacitance is always better than a lower offset voltage because it would generate an uncorrectable distortion on the ramp signal and, consequently, on the overall ADC performance. To comply with this requirement the transistors sizing of the comparator input stage has been kept relative small (30 µm/300 nm). To evaluate the correct value of the charging current Eq. 2.1 has to be rearranged taking into account the capacitance value, the ADC number of bit, the clock frequency and the input range. For a 100 pf

36 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 22 Figure 2.6: Charging current vs Ramp Voltage. Figure 2.7: A Class opamp Loop Gain and Phase. integrating capacitor, I charge has to be 500 na. This results in a full scale of 1 V, covered in about 205 µs. Being the offset voltage converted using the same algorithm, the conversion time dedicated to its digitization can be made shorter than that of the input signal conversion, with the benefit of speed. Only few clock cycles (enough to convert the maximum offset voltage, lower than 10 mv) have been reserved for this phase.

37 23 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Clocked Comparator To stop the counting process and determine the conversion result a circuit able to know when the ramp signal overcomes the input value is needed. The easiest way to implement this function is to use a comparator. There are several architectures which can be used to design a comparator block but one of the most common is based on the use of a latch-type sense amplifier. The main characteristics of this structure are a rail-to-rail output swing and a negligible static power consumption. The drawback of this solution is that it may suffer more from kickback noise, during the switching activity. In order to reduce this effect, the input stage has been drawn in a continuous time version. In this way the input signals are shielded from the comparator output (clocked) stage [9]. Fig. 2.8 shows the schematic of the comparator. The sizing of the input stage transistors plays a key role in terms of the comparator offset, parasitic capacitance and gate leakage current (see Sect ). As it will be shown in the calibration section, it is important that the comparator offset voltage is independent from the input signal value. To check this assumption, the comparator has been then tested as follow: one input has been connected to three different values of the input full-scale (namely 15 mv, 500 mv and 985 mv) and the other input to a saw-tooth signal that starts 10 LSB (Least Significant Bit) below the DC signal and ends 10 LSB beyond the input signal. In correspondence of each setup, 1000 Montecarlo mismatch iterations have been performed, sampling the output waveforms to be processed in Matlab R. It has been evaluated the moment in which the comparator changed its output polarity. Fig. 2.9, Fig and Fig show the statistics of the offset voltage as function of the input signal. It can be seen that the offset is quite constant in all cases. In addition, for a given iteration number, the offset voltage has exactly the same value. 2.3 Digital Calibration The aim of the introduced digital calibration is to compensate both the offset and the gain errors directly into the digital domain. Look at Fig. 2.12; the idea is to provide, at the output of the ADC control logic block - the node 1 -, an offset-free conversion result (but still affected by gain error) and than, through a simple multiplication, to complete the calibration procedure - node 2.

38 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 24 Figure 2.8: Clocked comparator schematic. Figure 2.9: Comparator offset for 15 mv input voltage Offset Error Correction The comparator offset voltage is here referred as the main reason of the ADC overall offset error but there are at least two other contributions that should be taken into account: the residual error in the ramp reset (due to the non idealities of the reset switch of Fig. 2.5) and the charge injections. Nevertheless, without a lost of generality, a DC voltage source in series with one of the two comparator inputs can resume all these contributions. Two functionalities, required by this offset error correction, are the grounding and the polarity swapping of the comparator inputs, as shown in Fig This is done by the Offset Cancellation block, shown in Fig It basically consists of a network of CMOS switches controlled

39 25 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.10: Comparator offset for 500 mv input voltage. Figure 2.11: Comparator offset for 985 mv input voltage. by the control logic. Furthermore, to avoid radiation-induced unwanted effects during the inactivity periods, an additional configuration makes a short circuit between the input nodes of the comparator. The calibration consists of two main operations: the digital conversion of the offset voltage (digitizing its absolute value and its sign) and its cancellation done directly in the digital domain. Consider, for example, a positive offset condition, as shown in Fig If the comparator positive input is grounded, the negative one is connected to the ramp signal and an A-to-D conversion is performed, it s possible to digitize the offset voltage. This sign assumption (a positive offset in this case) is confirmed or not directly by the conversion result. Indeed, if the offset voltage is negative the right comparator

40 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 26 Figure 2.12: Single slope ADC and calibration full block diagram. Figure 2.13: Offset Cancellation block functionalities.

41 27 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.14: Positive Offset Digital Conversion. inputs configuration is that shown in Fig Since the calibration starts always assuming a positive offset voltage, a negative one would require an additional phase with the reversed inputs polarity. The second phase starts if the first conversion result is an all zeros word. If the second phase provides an all-zeros word too, the offset is then considered null. Once that the logic has digitized the offset voltage sign, it is possible to set the set of switches inside the offset cancellation block in order to obtain V in [LSB] +V offset [LSB] as conversion result of the actual input signal (see Fig and Fig. 2.17). At this point, the offset error can be canceled by subtracting its value directly into the digital domain. Since the offset is digitized periodically, it s extremely important, as said in the previous paragraph, that it is constant and independent from the input signal. It s worth to be said that this offset correction still works also when the ramp slope is different from its nominal value. The residual error would be a gain error, whose correction is in charge of the gain calibration, shown in the next paragraph. Finally, considering that the ADC has to be able to digitize V in [LSB] +V offset [LSB] also with Vin = 1V, the charging period (remember that the greater is the input signal to be converted the longer is the time required) has been extended and the internal counting registers have been made using 13 bits, avoiding in this way counting overflows Gain Error Correction With a given time reference t step = 1/f clk (1/f clk is the system frequency clock), an input full scale V FS and a resolution of N bits, the value of the integrating

42 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 28 Figure 2.15: Negative Offset Digital Conversion. Figure 2.16: Positive Offset correction. Figure 2.17: Negative Offset correction.

43 29 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.18: Gain correction basic principle. capacitor C and the charging current I charge should be chosen to comply with V FS = (I charge) /C) (2 N 1) t step. In this design, the following nominal values are defined: f clk = 20 MHz, V FS = 1 V, N = 12, C = 100 pf, I charge = 500 na. Unfortunately, the values of the integrated capacitor and charging current cannot be controlled under process and mismatch variations; their spread can easily be in the range of ±20 % with respect to the nominal value. As a consequence, the resulting slope (I charge) /C) has wide variability and it can be larger or smaller than its nominal value, as shown in Fig A larger slope value results in lower conversion values, whereas a smaller slope value results in larger conversion values. As previously said, a possible solution could be the change of I charge or C but this approach could be risky, especially in terms of radiation performance. The basic idea of this gain correction is to map the actual set of measured results on the ideal one, using a simple operation, as a digital multiplication. Indeed, as shown in Fig. 2.18, for a given ramp slope, a certain counting window is given and if the time-scale changes also the conversion result would change. So, being changing the clock frequency an unfeasible solution, we can move this idea into the result domain. Now the accuracy of this procedure is function of the actual ramp slope. In the case of a slope higher than the nominal one, a set of results lower than 2 N 1 have to be mapped into a set of 2 N 1 numbers. This gives necessarily missing codes (i.e. DNL = -1 LSB). For this reason, it is mandatory to force the system to stay in the case with a ramp slope lower than the ideal value. The easiest way is to use an

44 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 30 Figure 2.19: Ramp Signals suitable for Digital Gain Correction. integrating capacitor slightly larger than the nominal value to ensure the correcting operating zone. As already said for the offset correction, also in this case, it is necessary that the internal counting register needs to be increased by 1 more bit (from 12 bit to 13 bit) and the conversion period to be extended. Fig shows all the possible ramp signals obtained under process and mismatch variations. It s very important that each input value (from 0 V to 1 V, on the vertical axis) is reached by the ramp signals within the charging period. The bold red line represents the ideal ramp (reaching 1 V exactly after 2 N 1 t step ). As it can be seen, all the ramps stay below the ideal one. These are the main drawbacks of this solution. Hereafter the superscripts represent the size of digital registers. The final N bit calibrated word, X [N] cal, can be calculated from the measured conversion result, X[N] meas, as X [N] real = (R[N] X [N] meas)/2 [N], where R is a correcting factor, evaluated off-line as R [N] = (X i deal/x meas ) 2 N, and X ideal is the ideal expected conversion result for the given input signal. Note that X ideal /X meas is a quantity less than 1 and that the 2 N terms are N-positions bit-shifting operations (left and right) which allow to perform multiplications with integer numbers. This procedure is thus able to align the actual ADC characteristics with respect to the ideal one, canceling the error gain and keeping almost the same linearity performance. The correction word is stored in a E-fuses based non-volatile memory and then loaded during power-up procedure. The correcting factor can be evaluated for any input signal amplitude but it is preferable to use the input full-scale because this choice guarantees the best precision in the approximation with discrete numbers. The multiplication between the raw conversion result and the correcting factor is performed by a serial binary multiplier, based on a single one-bit full-adder and a pair of shift registers.

45 31 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.20: ADC characteristics vs ramp slope. Figure 2.21: 130 nm ADC Layout. Figure 2.22: SCA Chip with ADC analog part highlighting. Exploiting the quite low variation speed of the input variables (temperature and leakage currents) it s possible to use such a structure which, although it takes n2 + n additional clock cycle to compute the correct value (an increase of about a 2% on the conversion time), guarantees a lower power consumption and a lower number of logic gates (i.e. a lower silicon area exposed to radiation).

46 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Experimental Results The 12 bit ADC has been fabricated in a 130 nm CMOS technology. In Fig it s possible to see the designed layout whereas in Fig the overall GBT-SCA 3.6 mm x 3.6 mm die photo, with a zoom on the analog part of the ADC is shown. The first measurement step has been done in normal environment conditions (in order to check the implemented calibration procedure). After that, the radiation test has been performed. The linearity performance, expressed in terms of DNL and INL, is shown in Figure The maximum measured DNL is LSB whereas the maximum INL is 1.87 LSB. Note that the highly linearity is still guaranteed, as expected from this kind of converter, provided by the high-accuracy ramp generation. Table 2.2 summarizes the performance of the proposed design with a comparison with other works in literature. Regarding the radiation test, it s shown in Fig Each curve is the digital conversion result of a different input signals (ten values, spaced by 100 mv) as function of radiation. The dose rate at which the ADC has been exposed is 400 krad/h. As it can be seen, all curves follow a similar trend. In particular, there is a radiation region in which the conversion result diverges from its nominal value (it becomes greater) and this behavior starts from about 0.5 Mrad and ends around 3.5 Mrad. This is a well known region and represents the radiation range in which the NMOS transistors start to leak current. Although the NMOS devices of the input multiplexer and the ramp current generator have been designed with an annular layout (for the reasons shown in chapter 1) the reset transistor of the ramp generator block (see Fig. 2.5) has a conventional (linear) layout. Unfortunately this choice exposes the device to heavier radiation effects, in particular to the creation of leakage currents. If the reset switch starts to leak a rad-dependent amount of current, the equivalent charging current is less than the nominal one. This produces, for a fixed integrating capacitor value, a ramp signal with a lower ramp slope. Recalling the ADC conversion principle, this means that the time required by the ramp to overcome the input signal becomes longer with the consequence of a higher conversion result. The higher is the input value to be converted the heavier is the error introduced by the rad-dependent leakage current. This aspect represents the weak point of this design which is going to be fixed in the next release.

47 33 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.23: ADC Linearity Performance. Figure 2.24: ADC Radiation Performance. This work Magazzù[14] Beikahmadi[? ] Gao[17] Ferragina[18] Process (CMOS) 0.13 µm µm 0.35 µm 0.35 µm Resolution (bit) Dynamic Range (V) f clk (MHz) Conv Time (s) 700µ <1n 20.48µ 0.4µ 42µ DNL (bit) < < < 0.58 < 0.5 INL (bit) < < 0.95 < 0.63 < 1 Supply Voltage (V) Power Consumption (W) < 800µ <40 m (overall) 631µ 24.3 m 4.8 m Area (mm 2 ) (die) (no pads) 2.138(die) - Table 2.2: Performance comparison. 2.5 The ADC Technology Porting The LHC is probably the greater and the most powerful particle accelerator built up until now. Nevertheless it s regularly maintained and updated, in order to increase its luminosity (the HL-LHC project, for example, aims to push the luminosity up to cm 2 s 1 )). This upgrading process generally involves a technological scaling down for the detector electronics; this ensure better (radiation) performance, offered by the newer technological nodes. The Wilkinson ADC, shown in the previous paragraphs, has been thought to be part of the upgrades of the coming

48 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 34 Parameter Value # of channels 32 Resolution (bit) 12 Input Full Scale (V) QE (bit) 1.5 Conversion Time (s) < 1m Power Consumption (mw) < 2 Supply Voltage (V) 1.2 Table 2.3: 65 nm ADC specifications. Figure 2.25: 65 nm Clocked Comparator. years. For this reason, its design has been ported in a different, more scaled, technology (namely the 65 nm CMOS tech.). It has been preferred to keep the same architecture, the same of Fig The aim of the following paragraphs is to highlight the main differences, between the two ADC versions, basically related to the technological change. Tab. 2.3 resumes the specifications that the new ADC has to comply. They are quite similar to the parameters of Tab. 2.1, a part those written in bold characters. As well known, a more scaled technology implies a lower voltage supply value; in this case it has been pushed from 1.5 V (130 nm CMOS tech.) down to 1.2 V (65 nm CMOS tech.). As a consequence of this change, the input full-scale has been reduced too (from 1 V down to 0.8 V). Indeed, a current generator like that in Fig. 2.5 is needed to ensure a very accurate ramp signal but, especially when the voltage supply is 10 % lower (a commonly used corner definition), some biasing problems could arise.

49 35 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.26: Complementary input stage for rail-to-rail operation Clocked Comparator As it happens for the ramp generator sub-circuit, some biasing issues can arise if the comparator design isn t carefully done. Consider, for example, the comparator circuit of Fig. 2.8; if it was used in 130 nm 65 nm technological porting, it should have to survive to a very limited headroom. The tail current, the PMOS input pair and the active load should be correctly biased with a 1.2 V - 10% voltage supply and an input common mode close to 1 V. It s evident that the comparator design needs a significant modification. Fig shows the chosen architecture.[19] It s composed by two complementary input stages that share the same latched output. The advantage which this structure brings is that it s able to cover the entire input full-scale. In particular, for input common mode voltage close to either supply voltage VDD or VSS, only one input pair is active, while in the middle voltage range, both input pairs work. Therefore, there is a large overlap region where both complementary pairs are active and the total transconductance is doubled, as shown in Fig Generally this could represent a problem for analog blocks like the operational amplifiers: the DC gain and the UGBW (Unity Gain Band Width) are generally g m -dependent quantities. But, is this a problem for a comparator circuit? For a clocked-comparator, the ratio g m /I d determines the input referred noise, the sampling aperture, the regeneration gain and the offset voltage[20][21]. Even though all these quantities are worth to be carefully handled, the latter is the one of most important parameters if the same ADC calibration procedure is maintained.

50 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 36 Figure 2.27: Offset Voltage vs Input Signal Conversion Offset Calibration As shown, the proposed offset correction needs a constant offset voltage, independent from the input signal which is under conversion. Unfortunately the g m variability, introduced by the complementary input stage structure, makes this assumption not longer true and the offset voltage needs to be converted before and as a function of each input signal. In Sect , the offset has been converted grounding one of the comparator inputs and performing an A-to-D conversion. In this case, this procedure would generate a residual uncorrected offset error. To solve this issue a ramp signal with a variable starting point is needed. Indeed, as Fig shows, this allows to correctly digitize the offset voltage as a function of the analog input, which is constantly connected to one of the comparator inputs. After this phase the calibration goes ahead as reported in Sect , resetting the ramp starting point to 0 V and finally performing the gain error correction Ramp Generator Fig reports the ramp generator circuit. It is similar to the previous one: a very accurate current (as shown in Fig. 2.5) has been used to charge a grounded 100 pf capacitance. In addition, a set of switches has been introduced in order to comply with the new requirements shown in Sect When φ is low the charging current is deviated to ground and the capacitor is pre-charged to the input value (V in ), in the offset conversion phase, or discharged to ground, in the

51 37 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.28: Modified Ramp Generator Circuit. Figure 2.29: Ramp Signal under PVT and Mismatch. input signal conversion phase. The sizing of switches has been chosen as trade-off between the settling time and the charge injection. Being the gain correction based on a compression of results it s again necessary that the coarse conversion result complies with Eq. 2.2 or, in analog terms, that all the possible ramp signals, under process and mismatch variations, have to stay within 400 mv and 800 mv after 2 12 t clk charging period. (2 12 1) < X coarse < (2 13 1) (2.2) Simulation Results Fig shows the layout of the analog part of the ADC, highlighting its dimensions. As in Fig. 2.21, the most of the area is occupied by the 100 pf integrating capacitor. Being the simulation time, needed to perform one analog to digital conversion,

52 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker 38 Figure 2.30: 65 nm ADC Layout (analog part only). very long (several hours), the ADC has been simulated in two different setups: the first with the aim to obtain a coarse quantization error curve and the second one to estimate the noise performance. For the first setup, 9 different input values (separated by 100 mv) has been provided to the ADC and their digital conversion result has been compared to the ideal counterpart, leading to the evaluation of the coarse quantization error graph shown in Fig It s possible to see that the maximum quantization error is equal to 1 LSB. Regarding, instead, the noise performance, it has been tested with the Transient Noise tool, running 10 noise iterations for three different input values; one in the lower part of the input fullscale, one in the middle and one in the upper part. The histograms of simulation results are shown in Fig. 2.32; the maximum error, due to thermal noise, is 1 LSB but statistically less observed (about the 70% of the simulation results coincide with nominal case).

53 39 Chapter 2. A digital-calibrated rad-hard ADC for CMS Central Tracker Figure 2.31: 65 nm ADC Coarse Quantization Error. Figure 2.32: 65 nm ADC Transient Noise Simulation.

54

55 Chapter 3 Rad-Hard BandGap Voltage Reference The ADCs shown in the previous chapters are just some examples of systems which need an external biasing voltage (or current), as much as possible stable. The aim of a voltage (or current) reference is just that: providing a very accurate voltage (or current), able to be constant under process, supply voltage and temperature variations. Sometimes, as it happens for high-energy physics experiment, additional stringent radiation-hardness specifications are required. In this chapter the design of a radiation-hard BandGap voltage reference is shown. 3.1 Introduction Historically, the BandGap reference circuits generated their output voltage stacking the silicon bandgap voltage (inversely proportional to the absolute temperature - IPTAT) to a voltage proportional to the absolute temperature (PTAT), like the thermal voltage kt/c. Combining, with suitable weights, the two opposite temperature dependence (by means of diode and MOS devices) made possible to obtaining a stable output reference, that is about 1.26V.[22] Unfortunately, the technological scaling-down process has made this approach unfeasible due the more and more limited voltage supply, since it would be very difficult to manage the 1.26 V Silicon BandGap voltage with supply lower than 1V. Alternative approaches have then been developed to overcome the low voltage supply issue. One solution is operating in the current domain, in which two currents, with two 41

56 Chapter 3. Rad-Hard BandGap Voltage Reference 42 opposite temperature dependencies, are combined together.[23] This approach is suitable for lower supply voltages, down to 1V and beyond. This design has been based on this approach, however adopting devices and layout solutions able to guarantee radiation hardness. This voltage reference circuit is intended to be used in environments exposed to extremely high Total-Ionizing-Dose (TID), as the future high-energy physics experiments at CERN require and even other aerospace activities.[14][24] The use of deep sub-micron technologies, which is required by the realization of complex System-on-Chip devices, is advantageous for rad-hard performance, since the reduced oxide thickness offers an higher inherently radiation tolerance for MOS devices, as explained in 1. In this design, suitable solutions for improving radiation hardness have been adopted, both at schematic and layout level. There are essentially two contributors in the radiation-hardness of a conventional BandGap reference circuit: those related both to transistors and to diodes. Quantum tunnelling fosters the recombination process on the radiationinduced charges then the impact of transistors, on the reference output, can be minimized choosing a proper sizing. For this reason, the BandGap design has been preceded by several measurements, at different radiation levels, on test transistors (both PMOS and NMOS types). These measurements have shown that the greater is the device area the lower are the radiation effects. Using these results, an ad-hoc section has been inserted in the model files of transistor provided by foundry in order to simulate (starting from schematic level) the radiation environment. Regarding diodes, a conventional diode is generally realized implanting a p + diffusion in n-well and surrounding the structure with Shallow Trench Isolation (STI) oxide. As reported in Chapter 1, trapping of positive charges in the STI leads to an increase in leakage currents. 3.2 Rad-hard Layout: Enclosed vs. Conventional Approach The radiation-induced charges shown in Section 1.3 increase not only the leakage current of transistor but affect also the behaviour of a diode. Fig. 3.4 reports the I-V characteristic of the conventional diode at different TID values (note: y axis is in logarithmic scale). The test has been done at the SEIFERT RP149 Xray machine, installed at CERN (see Fig. 3.1). As it can be seen, the characteristic is strongly modified by radiation effects. The smaller is the biasing current, the

57 43 Chapter 3. Rad-Hard BandGap Voltage Reference Figure 3.1: Bench with SEIFERT RP149 X-ray generator and probe station. larger is the damage on the I-V characteristic. This justifies why, in the past, the BandGap voltage reference for radiation environments were designed using very high biasing current. This reduced the impact of the radiation (mainly the leakage current grown), but led to higher power consumption. This effects can be mitigated by using the so-called enclosed-layout structures, where surrounding thick oxides are replaced by thin oxides. Fig. 3.2 shows how it is possible to obtain, for example, a PMOS transistor using an annular layout. The gate thin oxide completely surrounds the inner diffusion. Now the latter, jointly with the n-well below, can be seen as a diode with the STI oxide moved away.[25][26] Fig. 3.3 shows the vertical section of this radiation-hard diode. The source diffusion and the n-well represent the anode and the cathode of the diode respectively. To avoid any unwanted transistor effects, the gate contact is biased at the voltage supply (turning-off the PMOS transistor). This device has been tested in a radiation environment and compared with measurements of a conventional diode. Fig. 3.4 and Fig. 3.5 show, respectively, the I-V characteristics of a conventional diode and a diode with the enclosed layout. Although the different among curve with 0 Mrad (due to slightly different sizing), it is worth to highlight how the radiation effects are much lower on the enclosed layout diode. Using this solution allows to operate the diode with smaller bias current, while guaranteeing the same rad-hard performance.

58 Chapter 3. Rad-Hard BandGap Voltage Reference 44 Figure 3.2: Enclosed-Layout Diode (3-D view). Figure 3.3: Enclosed-Layout Diode (Vertical view). Figure 3.4: Conventional Diode I-V Characteristic. Figure 3.5: Enclosed-Layout Diode I-V Characteristic.

59 45 Chapter 3. Rad-Hard BandGap Voltage Reference 3.3 BandGap Voltage Reference Circuit After the description of the enclosed layout solution, which mitigates radiationinduced behavioral deviation, the circuit design of the rad-hard BandGap is here described. As previously anticipated, a current-mode approach will be used since it allows to operate at supply voltages in the order of 1V. In a current-mode BandGap reference circuit two currents, with opposite temperature dependencies (PTAT and IPTAT), are combined together in order to obtain a stable output voltage. In general, the voltage across a semiconductor diode has a temperature dependence that can be approximated by Eq. (3.1) V D = V BG αt. (3.1) Eq. (3.1) reports the voltage across a diode. It is a IPTAT (Inversely Proportional To the Absolute Temperature) quantity with the silicon BandGap voltage (V BG ) as maximum value, occurring at 0 o K, and a temperature proportional factor α given by α = k ln(const/j). So, assuming two diodes with different diffusion areas and biased with the same current level, they exhibit different temperature dependencies. This is due to the different current densities flowing through devices. In addition, this different temperature behavior can be enhanced making these devices working with different current levels. All these aspects are widely used in the design of low-voltage BandGap reference circuits. The BandGap reference circuit schematic is shown in Fig Eight replicas of D 1 have been used to realize D 2 while, to increase temperature sensitivity, the transistor M 1 has been sized eight time larger than the transistor M 2 (I M1 = 8 I M2 ). For the chosen biasing point the voltage across D 1 is around 800 mv so, to exploit the performance of an operational amplifier with the PMOS-type input stage, two resistive voltage dividers have been used. Indeed an operational amplifier with PMOS transistors as input stage guarantees better performance, if compared with the NMOS dual version, especially in terms flicker noise (the BandGap reference circuit works at low frequency). The opamp maintains the two nodes V a and V b at the same potential and consequently the V a and V b nodes (all resistors in the voltage dividers have the same value). Thanks to the virtual ground principle, it is possible to write the expression for the current flowing into the M 2 transistor, as reported in Eq. (3.2)

60 Chapter 3. Rad-Hard BandGap Voltage Reference 46 Figure 3.6: BandGap Voltage Reference Circuit. with V = V D1 V D2 I M2 = I Rs + I R2 + I D2 = 2 R s + R 2 2 R s R 2 V D1 + V R 3. (3.2) and where the first term of Eq. (3.2) is IPTAT while the second is PTAT (Proportional To the Absolute Temperature). Acting on the values of resistances, it is possible to compensate the two behaviors and obtain a temperature independent output voltage, at least in first approximation. To properly work, it is necessary for the ratio of the current densities (J 2 /J 1 ), flowing into the two diodes, to be temperature independent. Assuming the currents in M 1 and M 2 as independent on temperature and being the current flowing through D 2 (I D2 ) PTAT, the current in R 2 is thus IPTAT. The resistor R 1 deviates the current flowing into R 2 (multiplied by the current gain between M 1 and M 2 ) from D 1, making I D1 PTAT too. Considering a 1:1 mirroring factor between M 2 and M 3 the output voltage can be expressed as reported in Eq. (3.3): V OUT 3 = [ 2 Rs + R 2 V D1 + V ] R OUT. (3.3) 2 R s R 2 R 3 Three output resistors constitute a voltage divider to obtain three different output voltages while the output capacitance C OUT increases the PSR (Power Supply Rejection) and reduces noise. The additional capacitance C fb improves stability performance. Indeed, as it can be seen, there are two loops in the BandGap main sub-circuit (left part of Fig. 3.6). To ensure stability it is important to guarantee that positive loop is, at least, 3-4 times lower than the negative one

61 47 Chapter 3. Rad-Hard BandGap Voltage Reference - at all frequencies. The capacitor C fb introduces a pole at those frequencies where the positive loop gain was greater than the negative, restoring stability requirement. In order to increase the accuracy of the output current mirror gain, and consequently the precision of the output voltage, a regulated cascode current mirror has been designed for the output branch (right part of Fig. 3.6).[16] Contrarily to the operational amplifier in the main BandGap sub-circuit, the opamp for the regulated cascode has been designed with a NMOS transistor input stage because the voltage at node V b, in nominal conditions, is around 800 mv (critical for PMOS transistor, especially in the worst case scenario). 3.4 Operational Amplifiers Design Eq. (3.3) is essentially valid in an ideal scenario: perfectly matched current mirrors and resistors and operational amplifiers with infinite gain and zero offset voltage. If a proper sizing or biasing for current mirrors and resistors can easily make their contribution on the accuracy of the output voltage negligible, the design of the operational amplifiers requires a bigger effort to avoid performance degradation. The design of the operational amplifiers has been done essentially with the aim of noise and offset minimization. Regarding the gain at low frequency, it has been set sufficiently high in order to increase the virtual ground between its input nodes (very important for the BandGap accuracy). In absence of the offset voltage, it determines the precision in the V a = V b relation. Consider now Fig. 3.7, where the main BandGap sub-circuit with (right part) and without (left part) voltage dividers is shown. The opamp offset voltage is represented like a DC voltage generator in series with the positive input. In the circuit without the divider network, the nodes V a and V b represent the effective operational amplifier inputs. The output current, which flows through M 2, is reported by Eq. (3.4). I OUT = V D 1 R 2 + V R 3 ( 1 V offset + 1 ) R 2 R 3 (3.4) The V offset contribution can be negligible by increasing the ratio A 2 /A 1 (areas of diodes) or the mirroring factor between M 1 and M 2. Typically the latter is preferred, especially in radiation environments, because increasing the area of devices increases also the radiation hardness. Regarding instead the circuit with voltage dividers the output current is given by Eq. 3.5.

62 Chapter 3. Rad-Hard BandGap Voltage Reference 48 Figure 3.7: Opamp Offset Contribution. I OUT = 2 R s + R 2 V D1 + V ( 1 V offset ). (3.5) 2 R s R 2 R 3 R s R 2 R 3 This means that the opamp offset is more important in the output current value when the voltage dividers are used. Thus, it has to be minimized, if a certain precision on the output current is needed. A symmetrical operational amplifier, compensated by Miller technique, has been designed and its schematic is shown in Fig. 3.8.[27] This architecture allows to improve the BandGap overall power supply rejection since the opamp output node follows the voltage supply variation. This way, the V GS of transistors M 1, M 2 and M 3 of Fig. 3.6 remains constant. In addition, being the main contribution to the offset due to the threshold voltage mismatch of the input pair transistors (the current mismatch has been neglected), Eq. 3.6 has been used for sizing.[21] σ Vth = A VT W L (3.6) All transistors used in the BandGap circuit have been sized according to the radiation tests. PMOS transistors with W or L > 5µm guarantee a threshold shift of 60 mv while NMOS transistors with W or L > 3µm a shift of 20 mv.

63 49 Chapter 3. Rad-Hard BandGap Voltage Reference Figure 3.8: Symmetrical Operational Amplifier. 3.5 Bias and Startup Circuits A dedicated sub-circuit has been designed to generate biasing currents for operational amplifiers and to ensure the BandGap startup procedure. It s, indeed, very important to ensure the right start-up procedure because a BandGap voltage reference based on the architecture shown in Fig. 3.6 has potentially two operating points. The basic idea is to provide a small amount of current to the main BandGap circuit until internal nodes have reached their nominal value, pushing the system into the correct operating point. The schematic is depicted in Fig. 3.9.[28] The transistors M 1 M 2 M 3 and M 4 form a self-biased current generator, whose start-up is provided by M 7 M 8 and M 9. The transistors M 5 and M 6 mirror the current flowing through M 4 to the two operational amplifiers.[29] The right part of Fig. 3.9 constitutes the start-up section. The node V a (see Fig. 3.6) has been taken as sensing node and connected to the V in node. If V in is low the transistor M 11 is turned off and the transistor M 10 brings the input voltage of the following inverter (M 12 and M 13 ) to VDD. In this way M 17, M 18 and M 19 are turned on and the startup currents can flow. When the BandGap reaches the right operating point the sensing node (V in ) is sufficiently high to turn off the startup current generators. 3.6 Simulation Results In this section the simulation results (on the parasitic back-annotated schematic) of the BandGap voltage reference will be reported. Fig shows the nominal

64 Chapter 3. Rad-Hard BandGap Voltage Reference 50 Figure 3.9: Biasing & start-up circuit. simulation of the BandGap output voltage, for a temperature ranging from -10 o C to 50 o C. The output average value is about mv (though the absolute value is not so critical) and the TC (Temperature Coefficient, defined as V OUT / (V OUT T) is 9.8 ppm. Figure 3.10: BandGap output voltage - Nominal Conditions. In order to fully characterize the reference circuit performance it has been simulated also under process, mismatch and voltage supply variations. This test can easily highlight the robustness of an integrated circuit against the manufacturing process imperfections. Fig shows the results with process (ff, fs, sf, ss) and voltage (±10%) supply variations. Also in this case the maximum TC is less than 15 ppm for a shift in the output mean value less than ± 1.1%. Fig shows the BandGap output voltage under mismatch and supply variations. The maximum deviation is about ± 1.6%, mainly due to the offset voltage of the operational

65 51 Chapter 3. Rad-Hard BandGap Voltage Reference amplifier. This set of simulations concerns the regular flow of characterization of an integrated circuit; as said in the previous chapters, it s very important, for this kind of applications, to estimate the radiation effects; to ensure performance and lifetime. As explained in section 1.3, the main effect which a radiation exposure can generate inside a CMOS device is a threshold voltage modification. It is thus possible to simulate the effects induced by radiation creating an ad-hoc section in the model files (provided by the foundry) with modified threshold voltages. In particular, this modification has been made according to the set of radiation measurements on some test devices (up to 1 Grad), afore mentioned. In these conditions the TC is less than 22 ppm and the maximum variation in the average value is about ± 2%. Fig shows the output noise PSD (Power Spectral density) in nominal condition. The worst case scenario for integrated noise and power consumption has reported, respectively, about 180µV rms (integrated in 0.1 Hz 100 MHz) and about 240µW. Notice the effects of C OUT in the bandwidth reduction (it leads to a lower integrated noise). The right behavior of the start-up circuit has been verified through transient simulations. Fig and Fig demonstrate how the start-up sub-circuit, previously shown, forces the BandGap voltage reference to reach the correct operating point. Finally, Fig shows the layout of the BandGap voltage reference, highlighting dimensions. The occupied area is mm 2. Figure 3.11: BandGap output voltages - Process and supply variations.

66 Chapter 3. Rad-Hard BandGap Voltage Reference 52 Figure 3.12: BandGap output voltage - Mismatch and supply variations. Figure 3.13: BandGap Noise PSD. 3.7 BandGap Programmability Although the accuracy worsening, due to process and mismatch effects, is quite limited, introducing some programmability would be preferable. Consider again the schematic shown in Fig Acting, for example, on the values of resistors R 1 and R 3 it s possible to control the absolute value and the temperature coefficient of the output voltage, respectively. In particular, as shown in Fig. 3.17, reducing the R 1 value is possible to increase the mean value of the output voltage, keeping the temperature slope quite similar. On the other hand, modifying the value of resistor R 3 is possible to change the temperature coefficient. To implement these features the resistors R 1 and R 3 have been designed as 3-bit programmable

67 53 Chapter 3. Rad-Hard BandGap Voltage Reference Figure 3.14: Transient - process and supply variations. Figure 3.15: Transient - mismatch and supply variations. Figure 3.16: BandGap reference circuit layout.

68 Chapter 3. Rad-Hard BandGap Voltage Reference 54 elements. Therefore 64 configurations are possible and all of them have been tested with variation of T and TID irradiation. Figure 3.17: BandGap output voltage vs. R 1 value. Figure 3.18: BandGap output voltage vs. R 3 value. 3.8 Experimental Results The BandGap voltage reference has been first characterized in absence of radiation to validate the expected behavior. Fig shows the output voltage of the BandGap reference as function of the temperature, scanning the 64 configurations (8 R1 x 8 R3 ). Note that the BandGap reference circuit has been measured on a wider temperature range: from -40 o C to 80 o C. As already said, it s possible to change both the mean value and the temperature coefficient of the output voltage. The sample under measurement can be trimmed from about 400 mv to 300 mv

69 55 Chapter 3. Rad-Hard BandGap Voltage Reference (see Fig. 3.20), with a maximum deviation (V max V min ) starting from about 40 mv down to 5 mv (see Fig. 3.21). The equivalent percent variation is shown in Fig. 3.22, where it is possible to see how the maximum achievable percent error is lower than 2%. The sample has been irradiated in vacuum with 10 MeV proton beams at the SIRAD facility, located at the INFN National Laboratory at Legnaro, Italy. The facility takes advantage of a 15 MV Tandem accelerator, which can deliver proton and ion beams up to Au [30]. Fig shows the maximum percent deviation in the output voltage of the BandGap reference as a function of both the bit configuration and the radiation dose. The maximum error is about 10% up to 800 Mrad and represent a very good measurement result. The main performance is resumed in Tab. 3.1 where there is a comparison with other radiation-hard works present in literature. Figure 3.19: Output voltage vs. temperature (for different configurations). Figure 3.20: Output mean voltage (for different configurations).

70 Chapter 3. Rad-Hard BandGap Voltage Reference 56 Figure 3.21: Maximum output voltage deviation (for different configuration bit) Figure 3.22: Pre-Rad output voltage percent variation. Figure 3.23: Output percent variation vs. TID.

71 57 Chapter 3. Rad-Hard BandGap Voltage Reference Parameter This work Boufouss[31] Malcovati [32] Ivanovic[33] Gromov[34] Tech. (µm) CMOS 0.13 CMOS SOI 0.35 BiCMOS CMOS Bulk Supply Voltage (V) to 1.4 Ref. 25 o C (V) Temp. Range ( o C) -40 to to to to to 80 TC (ppm/ o C) o C (µw) V OUT 10% 25 ppm/krad ppm/krad 0.8 % shift due to Mrad (up to 40 Mrad) Table 3.1: BandGap reference performance comparison with similar radiationhard reference circuits.

72

73 Chapter 4 Conclusions In this thesis the design of mixed-signal integrated circuits for physical experiment has been detailed. In particular, the systems here developed have been thought to be part of the experiments inside the LHC (Large Hadron Collider) at CERN (Geneva). The presence of very high radiation levels constitutes the main reason of performance degradation and failure events. Thus, it has been extremely important to study the radiation-induced effects in order to face radiation and design radiation-hard blocks. The first project has concerned the design of an ADC in a commercial 130 nm CMOS technology, which is in charge of the digitalization of some environmental parameters (e.g. leakage currents, voltage supplies and temperature) inside a bigger monitoring ASIC. In fact, monitoring this quantities is important to improve performance and increase electronics life time. This design has been characterized by the introduction of a digital calibration procedure which mitigates both the offset and the gain errors of the ADC. Acting in digital it has allowed a better radiation immunity, preserving power consumption and area wasting. The achieved linearity performance has proved the quality of the introduced digital calibration. Lastly, to follow the continuous updating trend of the LHC s experiments, a porting (in a commercial 65 nm CMOS technology) has been done on the same ADC architecture. The second part of this thesis has concerned the design of a BandGap voltage reference. It has been characterized by a very strong radiation-hardness (a maximum 10% variation up to 800 Mrad), achieved with the use of a proper sizing and an ad-hoc layout of devices. An additional introduced feature is the possibility to trim both the output absolute value and the temperature coefficient, in order to further compensate the variations 59

74 Conclusions 60 introduced by process, mismatch and radiation effects. The prototype has been tested and results meet the specifications.

75 Appendix A Automatic Calibration for Single-Slope A-to-D Converters An automatic calibration circuit, for a Single-Slope A-to-D converter, is presented here. Its task is to automatically compensate the effects of process/mismatch and radiation, improving overall performance and equivalent number of bits of the Single-Slope A-to-D converter, acting directly on the ramp signal slope. Exploiting the A-to-D conversion result in its algorithm, the calibration circuit requires only few additional logic gates. This represents a key point for power saving because only a small extra power budget is required. This calibration is a foreground calibration example. Being performed at the power-on or occasionally, during the inactivity phases for example, this calibration algorithm slightly limits the definitive conversion rate. The ramp slope is controlled with a 12-bit control word. A 12-step binary search allows to evaluate the right control word and to calibrate the A-to-D converter, reducing its quantization error. A.1 Introduction As previously said in the Chapt. 2, the gain and offset errors of ADCs are often compensated in the analog domain but in the design presented in this thesis a digital correction has been preferred, in particular for radiation hardness purposes. This appendix is aimed to show an alternative analog solution for the single-slope ADC gain correction. Fig. A.1 reports the block scheme of the ADC, highlighting the automatic calibration section. As reported in the previous chapters, the accuracy of 61

76 Automatic Calibration for Single-Slope A-to-D Converters 62 single-slope converter strongly depends on the accuracy of the ramp signal. There are several ways to design a ramp generator circuit, both in continuous-time and discrete-time. The former solution is here preferred, charging a grounded capacitor with a constant current source as shown in Fig. A.1. Assuming a discharged capacitor at the start-up time, the ramp signal, function of time, can be expressed as reported by Eq. A.1. V out (t) = I ref C t (A.1) It easy to note that the ramp slope di/dc depends both on the value of charging current and the value of capacitor whereas the ramp linearity depends mainly by the charging current linearity (neglecting parasitic non linear capacitances). Here a charging current with sufficient linearity performance (but susceptible to technological process variations) has been considered. Unfortunately process and mismatch variations can make the actual values of the current and the capacitor very different from the nominal ones. This can lead to a wrong conversion result, as Fig. A.2 shows. The signal in the lower part of Fig. A.2, namely the output of the comparator, represent the enable/disable signal for the internal counters. In this example, being longer than the ideal one, it leads to a greater (wrong) conversion result. The more interesting characteristic of this calibration circuit is that it exploits the ADC converter output result in order to reduce the performance degradation, due both to the process/mismatch and to radiation. In particular it evaluates the information given by the difference between the real and the ideal (expected) conversion result and tries to correct the wrong ramp slope. This makes the calibration circuit smaller and composed only by a few additional digital logic gates; the overall power consumption is thus not dramatically increased. A possible way to realize a ramp signal with a programmable slope is to substitute the fixed integrating capacitance with a digital controlled array capacitor, whose value is set by control logic. In this design a 12-bit array capacitor has been used, as suggested by a Matlab model of the system. This kind of calibration lies in the foreground calibration techniques [? ]; it is performed interrupting the normal operation of the A-to-D converter. For this reason it isn t transparent from the speed performance point of view since, during calibration phase, the conversion from analog to digital domain of the input signals is forbidden. Typically it is performed at the power-on or during the inactivities periods or when the performance accuracy is getting

77 63 Automatic Calibration for Single-Slope A-to-D Converters Figure A.1: Single-Slope A-to-D converter with automatic calibration circuit. Figure A.2: Comparator s output duty-cycle vs. ramp signal slope. worse, due for example at environmental modifications (temperature of voltage supplies changes). In this case extra calibration cycles are required. A.2 Calibration Circuit As shown in Fig. A.1, the calibration circuit is essentially composed by three 12-bit registers, a digital comparator and some internal logic. First of all, a known suitable input signal is provided to A-to-D converter as an input. Its ideal conversion result is written by the user in a 12-bit register (B). The 12-bit register (A) stores the actual conversion result, provided by the A-to-D converter. This result is compared with the ideal one. After the comparison, the logic sets the array capacitor control word in the third 12-bit register (C). One way to set the calibration word could be starting from all zeros word, adding one bit at a time. It could be the simplest way, but such an approach would require too long time. Considering N b as the resolution of the A-to-D converter, 2 N b clock periods are needed to perform a single

78 Automatic Calibration for Single-Slope A-to-D Converters 64 Figure A.3: Automatic Calibration algorithm. Figure A.4: Array Capacitor. A-to-D conversion. For this reason the research of the right calibration word has been based on a binary search. The calibration word is set starting from the MSB (Most Significant Bit), bit by bit. It could be said that the A-to-D converter has been used to calibrate itself. To control the ramp slope a 12 bit grounded array capacitor, binary weighed, has been used [? ]. The circuit topology of the array capacitor is shown in Fig. A.4. Its resolution has given by equation (A.2), where C max = C nom / (1 ξ), C min = C nom / (1 + ξ) and ξ is the tecnological spread. The resolution of the array capacitor has been obtained from a Matlab model of the calibration circuit, assuming a technological spread of 35%, taking into account the variations both of the biasing current and of the array capacitor elements.

79 65 Automatic Calibration for Single-Slope A-to-D Converters δc = C max C min 2 N 1 (A.2) The calibration algorithm tends to reduce the error between the ideal conversion result and the real one pushing the ramp signal in a mask of ±0.5LBSB[V] (Least Significant Bit) around the ideal ramp. Indeed all ramps that stay in this range give the same conversion result. Thus the choice of the input signal (V calibration ) to use to perform calibration is most important. The equation (A.3) provides the difference, function of time, between two ramps knowing their distance at a given time (see Fig.?? ). V (t) = V (t calibration ) t t calibration (A.3) If the calibration algorithm is performed with V calibration = V FS /2 (Full Scale) all input signals, ranging from 0 to V FS /2, will see, after the calibration, the ramp in the mask of ±0.5 LSB [V] around the ideal ramp. Considering the conversion result dependent only from the ramp signal accuracy this would allow to obtain an ideal behavior. On the other hand, all the conversions of the input values from V FS /2 to V FS could provide wrong results.this is due to the distance between real and ideal ramps af the full scale that could reach 1 LSB, due to linearity of ramps. Thus the calibration has been performed using an input signal very close to the full scale (976.5 mv 4000 LSB ). Fig. A.5 shows an example of this calibration. The algorithm starts setting the MSB of the Calibration Word to 1, all the other bits to 0 and performs an A-to-D conversion. At the end, the conversion result is compared with the ideal one (stored in register B, see Fig. A.1 ). Being the conversion result greater than the ideal the MSB is hence set to 0, in order to reduce the array capacitor value and increase the ramp slope. The algorithm continues until the last bit is asserted. Note how the conversion result tends to match more and more the ideal conversion result (see lower part of Fig. A.5).

80 Automatic Calibration for Single-Slope A-to-D Converters 66 Figure A.5: Example of Calibration. Parameter Process Temperature Value slow-slow, fast-fast 40 o C, 120 o C Table A.1: Simulation Corners Figure A.6: Quantization error in ss, 120 o C corner. A.3 Simulation Results To validate the automatic calibration circuit performance a rough A-to-D converter Quantization Error (QE) has been evaluated. Due to very long simulation time required to perform just one conversion, only 391 points of the input range have been chosen. They have been chosen spaced by 10 LSB and as multiples of 1 LSB 4 and 3 LSB. The ideal QE, considering these kind of input values, should be between 4 ±0.25 LSB, being the distance between the input values and the corresponding ideal quantized voltage 1 LSB. The calibration has been performed in four different 4 corners (see table A.1). The maximum quantization error, in the worst case, has been of 1 LSB (see Fig. A.6 and Fig. A.6) whereas in some corners the obtained result have been close to the ideal ones (as shown in Fig. A.8 and Fig. A.9). These results have confirmed the validity of the calibration idea.

81 67 Automatic Calibration for Single-Slope A-to-D Converters Figure A.7: Quantization error in ff, 120 o C corner. Figure A.8: Quantization error in ss, -40 o C corner. A.4 Conclusions Figure A.9: Quantization error in ff, -40 o C corner. The study of the automatic calibration circuit shown in this appendix has been tought to work with a Wilkinson (Single-Slope) A-to-D converter. It can be a valid alternative to the gain calibration shown in the paragraph 2.3 if particular constrains, in terms of area occupation are present; indeed, this solution requires a discrete quantity of analog controls. To guarantee the required radiation hardness it s necessary to avoid narrow and short transistors, which grows the overall occupied area. Controlling the ramp signal slope it is able to compensate all process/mismatch effects. In general any non-ideality, introduced by process and

82 Automatic Calibration for Single-Slope A-to-D Converters 68 mismatch, can be referred to a ramp slope deviation. Regarding radiations, all those effects that could change the operating point of devices inside A-to-D converter can be also mitigated. The ramp slope programmability has been introduced with a 12-bit array capacitor and has been controlled with a digital word, provided by this calibration circuit. To reduce the calibration phase the control word has been searched in a binary way. The required time to complete calibration is 2.4 ms, 12 consecutive A-to-D conversions. The proposed solution, sharing several blocks with the main A-to-D converter, allows to keep the power consumption restrained. The maximum quantization error obtained using a calibrated ramp signal is 1 LSB in the worst case.

83 Publications

84 ICICDT 2013, Pavia, Italy Session H AMS A 32-Channel 12-bits Single Slope A-to-D Converter for LHC environment T. Vergine (1) (2), M. De Matteis (1)(3), S. D Amico (3), V. Chironi (3), A. Marchioro (4), K. Kloukinas (4), A. Baschirotto (1) (1) University of Milano Bicocca Italy. Department of Physics G. Occhialini. (2) University of Pavia Italy. Department of Electrical Computer and Biomedical Engineering. (3) University of Salento, Lecce Italy. Department of Innovation Engineering. (4) CERN, 1211 Geneve 23, Switzerland. tommaso.vergine, marcello.dematteis, andrea.baschirotto@unimib.it. Abstract The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments. The CMOS integrated circuits operating in high-energy environments experience large leakage current and voltage/temperature variations. For this reason in LHC experiments, a proper sensing and monitoring system has been designed with the aim to provide real time information about the electrical/physical scenario for the detectors in LHC. The A-to-D converter has a resolution of 12 bits, is based on single slope architecture and is able to manage 32 input analog channels. The design is challenging for several reasons, considering the required conversion accuracy and the critical physical scenario. The entire A-to-D converter has been fully characterized with process-voltage-temperature variations, obtaining a definitive 11bit accuracy in the worst-case simulation corner. The A-to-D has been designed in CMOS 0.13μm technology, consumes 350µW (including dynamic power due to the digital circuits) and operates at 20MHz clock frequency, for a definitive 2.3kHz sample rate. Keywords: A-to-D, Low-Power, Radiation Hardness, highenergy experiments. I. INTRODUCTION Integrated microelectronic circuits are widely used in highenergy physics experiments like that of the LHC (Large Hadron Collider) environment [1][2][3][4][5][6]. Comparing with PCBbased circuits and programmable logic devices, the main advantages are costs reduction, performance improvement and better immunity to parasitic capacitance and EMI. On the other hand, dedicated integrated circuits are scarcely reconfigurable, reducing portability. CMOS read-out circuits are placed and connected very close to the detectors and for this reasons they are exposed to hard radiations, degrading performance and increasing breakdown events. For this reason a proper sensing and monitoring system (called DCU, Detector Control Unit) has been used in CMS (Compact Muon Solenoid) central tracker, with the aim to provide real time data about the detectors temperature and the electrical parameters (leakage currents and supply voltage variations). In this way, the detectors and the correspondent electronics read-out is real-time monitored, reducing failure events and improving overall performance. Notice that the DCU circuits are also exposed to radiations, so that proper layout techniques have to be considered for better immunity. In addition, the integrated circuits performances must be evaluated also in case of large process, voltage, temperature (PVT) variations. The supply voltage variations and the leakage currents intensity is sensed by the DCU, and then converted into the digital domain by the A-to-D converter object of this paper. NTC are also used for temperature sensing, where the temperature variation vs. time is quite slower than the A-to-D sample rate. The A-to-D converter is based on a single ramp architecture, which appears the most reasonable solution for high accuracy. Notice that in DCU system, the large conversion time typically required by the single slope A-to-D architecture is not an issue. In fact, the parameters to be monitored are supply voltage and leakage currents (dc electrical parameters) and temperature, whose maximum variation vs. time is typically very much lower than the A-to-D conversion time. A very accurate ramp generator circuit has been implemented, suitable to provide a 0V/1V ramp signal. The comparator design is also challenging due to the 0V input signal, and for kickback noise that can critically affect the A-to-D converter performances. A proper offset rejection digital algorithm has been also integrated in the A-to-D architecture. This paper is organized as follow. In Section II the DCU system, where the A-to-D converter operates, is presented, while in Section III the most important A-to-D specifications are addressed. Section IV presents the circuital solutions adopted for the ramp generator and for the comparator. Section V includes the most important A-to-D simulations results, and at the end of the paper Conclusions are drawn. II. SYSTEM OVERVIEW The Detector Control Unit (DCU) is a dedicated integrated circuit for CMS-Tracker electrical/physical parameters monitoring. The CMS-Tracker is a system based on silicon micro-strip detectors that, when exposed to high level of radiation like that can be found in the LHC environment, can undergo a significant change in their leakage current and depletion voltage. A critical performance degradation has been also observed in electronic detectors read-out circuits. The CMS tracker system is composed by three main blocks: the micro-strip detectors, the read-out chips, and the DCU. To monitor the leakage current of the micro-strip sensors, sensing resistors have been used. In this way the leakage current is converted in a voltage signal and then is provided to the input of the A-to-D. The output converted word can be read on the I2C interface /13/$ IEEE 139

85 Paper H2 ICICDT 2013, Pavia, Italy III. Fig. 1 - Block Diagram of A-to-D Converter (left) and one conversion step time-diagram (right). A-TO-D CONVERTER SPECIFICATIONS The most important A-to-D converter specifications are obtained by system-level considerations and are presented in Tab. 1. The A-to-D manages 32 different analog input signals. The maximum quantization error is 1LSB, leading to a minimum required resolution of 11 bits. The analog input signal range is from 0V to 1V. The maximum allowed power consumption including the digital circuits is about 2mW, from a single 1.5V supply voltage. # of channel 32 Resolution 12 bits Input Range 0V 1V Quantization Error (max) 1 LSB Power Dissipation < 2mW Conversion Time < 1 ms Supply Voltage 1.5V Tab. 1 A-to-D Converter Specifications. IV. A-TO-D CONVERTER ARCHITECTURE The basic idea of the single slope architecture is to compare the analog input signal with a continuous time ramp between 0V and 1V, performing a voltage vs. time conversion. The duty-cycle of the digital comparator output is then proportional to the digital signal resulting from the conversion. The functional scheme of the A-to-D converter (on the left) and the time-diagram of the most important signals for one conversion step (on the right) are shown in Fig. 1. The first block is the ANALOG MUX, that allows to choice a particular analog input signal between the 32 connected inputs. Since the A-to-D conversion is here performed comparing the analog input signal with a continuous time ramp, every slope variation in the ramp signal can critically affect the overall A-to-D converter performance. For this reason a careful design of the RAMP GENERATOR circuit is here developed. In particular, the ramp is obtained by using a current source charging a capacitor with the bottom plate connected to ground. The choice of the ground-connected capacitor is motivated by the fact that the analog input signal to be converted has a dynamic range between 0V to 1V, so that the ramp signal swing goes from 0V to 1V too. This requires an additional design effort because the RAMP GENERATOR and the following blocks (see Fig. 1) have to manage an input signal up to 0V. The reference current can be tuned from the external in order to compensate the capacitor technological spread (about 20%). On the other hand, it is very important to design a current mirror able to manage the exact reference current without significant degradation due to the MOS transistor process spread and mismatch. As illustrated in Fig. 1 the AUTOMATIC OFFSET CANCELLATION block is placed between the analog input signals (analog mux output and ramp), with the aim to swap the comparator inputs. Performing two successive conversion steps (the second step has the inverted signals comparing to the first step), it is possible to cancel the comparator input offset [7]. The ramp signal behavior vs. time is plotted in the time diagram in Fig. 1, where the effect of the offset is highlighted. Assuming the offset can be represented like a dc voltage source connected to the comparator input, the output converted voltage, after two conversion steps, is determined by the (1) V out Vin Voffset Vin Voffset (1) 2 The comparator is based on a latched circuit, in order to improve the compatibility between analog and digital (clocked) part of the overall A-to-D converter and to reduce power. The last block is the A-TO-D CONTROL LOGIC, responsible of the overall timing and control. The external clock (EXT_CLK) and the asynchronous start of conversion signal (SOC) are provided to the A-to-D CONTROL LOGIC block that generates the ramp phases (reset, ramp and hold) during each conversion, controls the AUTOMATIC OFFSET CANCELLATION, provides a controlled (stopped) clock to the CLOCKED COMPARATOR and gives the 12 bits output converted value (DATA). The end of conversion signal (EOC) indicates that the result of conversion is available (see time-diagram in Fig. 1). A. 32 Channel Input MUX The 32 Channel Input MUX has been realized with 32 complementary switches. This choice has allowed to obtain a very low on resistance value with every input signal. Remember that the input signal ranges from 0V to 1V. The obtained settling time is 140

86 ICICDT 2013, Pavia, Italy Session H AMS about 15ns. Since every conversion starts with a reset phase, whose duration is 1µs, this settling time is not problematic. B. RAMP GENERATOR The main task of the ramp generator circuit is to realize a precise current mirror that keeps the current value constant during the ramp generation phase and whose variations, under process and mismatch, are in the tuning range of the external biasing current. Since the voltage swing at the output node of the current mirror is about 1V, the current mirror output resistance would be carefully evaluated. For this reason a simple Matlab model of the current mirror has been implemented and simulated for several output resistance values (the output resistance is defined as the total resistance connected between the current source and the capacitance, see fig1). In order to avoid A-to-D conversion performance degradations, Matlab simulations have demonstrated that the minimum required output resistance for the RAMP GENERATOR circuit is about 5GΩ. Such value is problematic using a simple transistor, so that an improved current source circuit is used [8]. The circuital topology is shown in Fig. 3, where the current mirror has been improved adding a negative loop. This loop involves the operational amplifier and the output transistor M4. The aim of this loop is to increase the output resistance and to fix the operating point voltage of the M3 transistor drain, when M4 drain changes between 0V and 1V. 6.5GΩ are obtained as output resistance. As reported in Fig. 1, the switch connected at M4 transistor drain switches during each conversion step. For this reason step response, and as a consequence stability of the improved current mirror in must be carefully evaluated. In addition, for low power operation, current operational amplifier current consumption should be minimized [10]. As shown in Fig. 2 the obtained phase margin of the loop is about 83. The operational amplifier has designed with 55 db of dc gain and 2 MHz of bandwidth. Its performance are resumed in Tab. 2. Very low unity gain bandwidth is here required, for stability reasons, and avoiding also additional power budget request. Nevertheless there isn t any effect of this almost limited bandwidth on the settling time for the inner node of the current mirror during the ramp phase switch-on. Fig. 3 - Improved Low Voltage Current Mirror. The current mirror in Fig. 3 has been completely validated by MonteCarlo simulations, including also process and temperature spread. This design guarantees an error less than 5% on the ramp slope. This is shown in Fig. 4. If the process effects on the capacitor are also taken into account, this deviation falls in the tunable range that the external biasing current can compensate. Fig. 4 - Process and Mismatch effects on Current Mirror C. Clocked Comparator One of the most common comparators architecture is based on latch-type sense amplifier. The main characteristics of this structure are a rail-to-rail output swing and a negligible static power consumption. On the other hand, this type of comparator may suffer more from kickback noise. In order to reduce this effect, the input stage has been drawn in a continuous time version. In this way the input signals are shielded from the comparator output (clocked) stage [9]. Fig. 5 shows the schematic of the comparator. The sizing of the input stage transistors plays a key role in terms of the comparator offset, parasitic capacitance and gate leakage current (see RAMP GENERATOR section). Large offset values reduce the input range in which (1) provides right conversion results. Fig. 2 - G Loop and Loop Phase. Gain DC 55 db UGBW 2 MHz Power Consumption 30 µw Tab. 2 - Operational Amplifier Performance Fig. 5 - Clocked Comparator Schematic. 141

87 Paper H2 ICICDT 2013, Pavia, Italy To mitigate this problem, the comparator offset has to be minimized increasing the input stage transistor area. On the other hand this approach increases the parasitic capacitance. Notice that in spice simulations the comparator parasitic capacitance of the input differential pair does not appear critical, due to the large 100pF connected at the current source drain. V. SIMULATION RESULTS The A-to-D power consumption is 350µW, six times lower than the maximum allowable power (Tab. 1). To perform a complete conversion (two consecutive conversion steps) about clock periods are needed, so that the simulation duration is quite long. In order to test the A-to-D converter, two simulation sets have been performed: nominal and Transient Noise simulations, choosing three input signals: 3.785mV (corresponding to 15.5LSB), 500.1mV ( LSB) and 996.2mV ( LSB). As illustrated in Fig. 6, the A-to-D output digital data coincides with the required ideal result, so that the accuracy of the A-to-D converter is equivalent to a 12bits conversion. A slight degradation of the A-to-D performance is observed in Fig. 7, where the converter has been simulated using Transient Noise tool. Ten different simulations have been run for each analog input signal (3.785mV, 500.1mV and 996.2mV), demonstrating that the worst case accuracy is 11bits, but statistically less frequently observed (about the 70% of the simulation results coincides with nominal case). Fig. 7 - Conversion results in Transient Noise simulations. VI. CONCLUSIONS In this paper a 32 Channel 12 bits single-slope A-to-D converter has been presented. It has been designed in 0.13 µm CMOS technology. The ramp has been obtained charging, with a very accurate current mirror, a grounded capacitor. The overall deviation of the ramp slope, due to the process and mismatch effects on the capacitor and the current mirror, falls into the range that the external current can tune. Performing two conversion of the same input signal ( 430µs), the comparator input offset has been cancelled in an automatic way. The conversion maximum error, in transient noise simulation, is 1 LSB. These performance are summarized in Tab. 3. # of channel 32 Resolution 12 bits Input Range 0V 1V Quantization Error (max) 1 LSB Power Dissipation 350µW Convertion Time 430µs Tab. 3 - A-to-D converter overall performance. REFERENCES Fig. 6 A-to-D conversion results in nominal conditions. [1] Baschirotto, A.; Cocciolo, G.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G. A fast and low noise charge sensitive preamplifier in 90 nm CMOS technology. Journal of Instrumentation. Volume 7, January pp.1-8. [2] D'Amico, S.; et al. A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers. Circuits and Systems I: Regular Papers, IEEE Transactions on Vol.59 n. 2. pp [3] Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G. CLARO-CMOS, a very low power ASIC for fast Photon counting with pixellated photodetectors. Volume 7. November pp: [4] Wang, X. et al. A high-band IR-UWB chipset for real-time duty-cycled communication and localization systems. Solid State Circuits Conference (A- SSCC), 2011 IEEE Asian pp [5] M. De Matteis, et al. A 550mV 8dBm IIP3 4th order analog base band filter For WLAN receivers. Solid State Circuits Conference, ESSCIRC rd European. Page(s): [6] Musa, L.;, "Highly integrated system-on-chip circuits for the readout of highenergy physics detectors," Advances in Sensors and Interface, IWASI nd International Workshop on, vol., no., pp.1, June 2007 [7] G. Magazzù, A. Marchioro, P. Moreira, A rad-hard 8-channel 12-bit resolution ADC for slow control applications in the LHC environment, 7th Workshop on Electronics for LHC Experiments, Stockholm, Sweden, Sep 2001, pp [8] J. Ramirez-Angulo, et al. Low supply voltage high performance CMOS current mirror with low input and output voltage requirements IEEE Transactions on Circuits and Systems-II Express Briefs, Vol. 51, No. 3, March 2004 [9] S. D Amico, G. Cocciolo, M. De Matteis, A. Baschirotto, A 7.65mW 5bits 90nm 1Gs/s ADC folded-interpolated without calibration, Solid State Circuits Conference, ESSCIRC th European. Page(s): pp [10] D'Amico S., M. De Matteis, A. Baschirotto, "A 6.4 mw, 4.9 nv/ Hz, 24 dbm IIP3 VGA for a multi-standard (WLAN, UMTS, and Bluetooth) receiver". Analog Integrated Circuits and Signal Processing Volume 61, Issue 1, October 2009, Pages

88 PRIME 2013, Villach, Austria Session M2A Oversampled ADCs An Automatic Calibration Circuit for 12-bits Single-Ramp A-to-D Converter in LHC Environments T. Vergine (1) (2), M. De Matteis (1), L. Rota (1), A. Marchioro (3), A. Baschirotto (1) (1) University of Milano Bicocca Italy. Department of Physics G. Occhialini. (2) University of Pavia Italy. Department of Electrical Computer and Biomedical Engineering. (3) CERN, 1211 Geneve 23, Switzerland. tommaso.vergine, marcello.dematteis, Abstract A calibration circuit for single-ramp A-to-D converters is presented here. The calibration circuit allows to automatically compensate the process/mismatch and radiation effects on the A-to-D converter, improving performance and Equivalent Number of Bits. In particular, the calibration circuit is able to automatically align the ramp signal reference used for the conversion in single slope architectures A-to-D architectures, compensating slope deviations due to technological/electrical reasons. Moreover, the calibration circuit shares the same analog circuits of the A-to-D converter, requiring only a small additional power budget and logic for the implementation. The calibration circuit has been validated, testing the overall A-to-D converter after the calibration. A 12 steps binary search is required to calibrate the A-to-D converter (about 2.5ms). This calibration circuit is able to guarantee an 11bits accuracy, in the worst case simulation corner. The technology used is a 65 nm CMOS. The clock frequency has been set to 20 MHz and the power consumption is about 400 µw. Keywords A-to-D, Low-Power, Radiation Hardness, High-Energy- Physics instrumentation, Automatic Calibration, Successive Approximations Register. I. INTRODUCTION Nowadays CMOS integrated microelectronic circuits are widely used in instrumentation for High-Energy Physic experiments [1][2][3][4]. In particular, in the LHC (Large Hadron Collider) environment, the detectors read-out channels and the additional circuits for environmental sensing/monitoring are mostly implemented in CMOS technology [5]. The LHC environment is very harsh for microelectronic circuits since the high intensity radiation present around such accelerator can damage integrated devices. Device electrical/physical parameters (like MOS threshold voltage, mobility and resistances) can significantly change due to irradiation and can lead to system-level performance degradation or even failure. In order to optimize performance and increase life-time a practical approach in high-energy physics experiment is to externally periodically calibrate the integrated devices. In this way the electrical variation of the integrated circuits can be adequately compensated. Similar approach appears robust and reliable, but becomes critical and impracticable in presence of several integrated circuits in a limited specific area, like in LHC environment. The 12 bit A-to-D converter object of this paper will be art of a bigger system responsible for the temperature/leakage sensing and monitoring of the detectors in the LHC CMS (Compact Muon Solenoid) central tracker. This A-to-D converter is based on single-ramp architecture. Notice that any deviation of ramp slope, due to process, temperature, radiation, can be detrimental for overall A-to-D converter performances. For these reasons an automatic calibration circuit has been implemented, with the aim to occasionally align, in an automatic way, the ramp slope to the nominal one, compensating any ramp signal deviation due to electrical/physical parameters variations. The calibration circuit improves significantly the overall performance of the A-to-D converter, and in addition no external calibration is then needed for A-to-D performance optimization. An important aspect of this approach is that it does not affect the A-to-D converter overall power consumption because several A-to-D blocks are shared with the calibration circuit. It exploits the A-to-D conversion result in the array capacitor control word research. This makes the calibration circuit simpler and composed only by a few additional digital logic gates. The ramp voltage signal has been obtained charging a 12 bit grounded array capacitor with a very precise current mirror. This approach allows to control the ramp slope changing the array control word. This paper is organized as follows. In Section II the structure and sizing of the Calibration Circuit are shown. In Section III the design of the A-to-D converter two most important blocks is reported whereas Section IV shows the A- to-d converter performance, as validation tool. At the end of the paper the conclusions are drawn. II. CALIBRATION CIRCUIT The calibration circuit proposed here is foreseen to work in a single-ramp A-to-D Converter [5]. The conversion method is a voltage to time conversion, comparing the analog input signal with a continuous-time ramp voltage signal. It is clear that any deviation in the ramp voltage signal slope affects the overall A-to-D converter performance. For this reason the main aim of the calibration circuit is to automatically align the ramp signal to the nominal (ideal) ramp, compensating any electrical/physical deviation, and improving the overall A-to- D conversion performance. The ramp voltage signal is obtained by charging a capacitor with a very precise reference current (I REF ) - see Fig. 1. A. Calibration Algorithm The idea of this calibration circuit is to align the ramp slope with the ideal one by adjusting the size of the integrating capacitor through a digital control word (Calibration Word). Notice that, there are two main reasons for the ramp slope deviation (and as a consequence A-to-D converter performance degradation): variation of I REF (reference current), and spread of the capacitor due to process, temperature and aging /13/$ IEEE 45

89 Paper M2A3 PRIME 2013, Villach, Austria Fig. 2 - Comparator Output Duty-Cycle vs. Ramp Voltage Signal. The main effect of both non-idealities is a deviation of the ramp slope with respect to the ideal one. The basic idea of the calibration circuits presented here is to compare the ramp signal (affected by some deviation due to I REF and C ARRAY ) with a fixed reference voltage signal. As a consequence of a non-ideal ramp signal, the duty-cycle of the comparator output voltage will be different from the expected duty-cycle (in case of ideal ramp), as shown in Fig. 2. Comparing the two signals duty-cycles, it is possible to evaluate how much is important the slope deviation with respect to the ideal one. The calibration word search could be performed in several ways: starting from all zeros word, adding one bit at a time, could be the simplest way, but such an approach requires too long time. Remember that 2 Nb -1 clock periods (where Nb is the number of bits in the A-to-D) are needed to perform a single conversion. For this reason the research of the right calibration word is based on a binary search. The calibration word is set, bit by bit, making a comparison between the real and ideal conversion results. Fig. 1 Single Slope A-to-D converter with automatic calibration circuit The binary search, being based on the result of A-to-D conversion, allows to share several blocks between the A-to-D converter and the binary search-based calibration circuit, saving power consumption and circuital complexity. Indeed only few additional logic gates are required to perform the calibration. B. Calibration Circuit Implementation. Fig. 1 shows the block diagram of the Single Slope A-to- D converter with the automatic calibration circuit. The calibration circuit is essentially composed by three 12 bit registers, a digital comparator block and some logic. The first 12 bit register (A) stores the actual conversion result, provided by the A-to-D converter. This result is compared with the ideal one, stored in the second 12 bit register (B). After the comparison, the logic sets the array capacitor control word in the third 12 bit register (C). An example of the calibration sequence is shown in Fig. 3. The algorithm starts assuming that the MSB of the (C) register is 1 and the other bits are 0. At the end of the first conversion the actual converted data is compared with the ideal one. If it is higher the MSB are set to 0, if it is lower the MSB is asserted to 1. The algorithm proceeds recursively until the last bit, the LSB, is asserted. The circuit topology of the array capacitor is shown in Fig. 4. Its resolution has given by the equation (1) [7]: Cmax Cmin δc = (1) N 2 1 where Cmax = Cnom /( 1 ξ ) and C = Cnom /( 1+ξ ) min are the maximum and minimum array capacitance and ξ is the technological spread. This parameter (ξ) has been imposed to 46

90 PRIME 2013, Villach, Austria Session M2A Oversampled ADCs 35%, considering the process/mismatch effects both on the array capacitor elements and on the current mirror. In order to make negligible the minimum difference between ideal ramp and real ramp (±0.5 LSB) that the A-to-D converter can sense, the calibration procedure has been performed using a voltage signal (V calibration ) very close to the full scale ( mv = 4000 LSB). Eq. (2) shows the voltage error between the ideal and real ramp as a function of time, knowing its value in a given point. If this point is chosen very close to the full scale the voltage deviation between the ideal and the real ramp is almost equal to 0.5 LSB up to the full scale. t calibration is the time that the ramp needs to reach the V calibration voltage. As previously said, the algorithm changes the calibration word in order to match the real conversion result with the ideal result. See lower part of Fig. 3. t ΔV () t = ΔV ( tcalibration ) (2) t III. calibration Fig. 3 Example of Calibration. Fig. 4 Array Capacitor Sizing. A-TO-D CONVERTER ARCHITECTURE The A-to-D converter, as shown in Fig. 1, is composed by two sections. The analog section includes mainly the RAMP GENERATOR and the COMPARATOR blocks while the digital section includes the A-to-D CONTROL LOGIC and the calibration circuit blocks. Since the analog input signal ranges from 0 V to 1 V the output of the RAMP GENERATOR has to start from 0 V and reach 1 V too. For this reason a grounded array capacitor is charged, with an accurate current mirror, to generate the ramp voltage signal. This implies a careful design of the RAMP GENERATOR block. The COMPARATOR is a Verilog-A block. The A-to-D CONTROL LOGIC is responsible of the A-to-D converter overall control and timing. Every SOC (start-ofconversion) rise-edge enables an A-to-D conversion. The flag EOC points out the end of every conversion cycle. The calibration circuit controls the array capacitor value in order to match real conversion result with the ideal one. At the SOT rising edge the automatic calibration procedure starts with 12 consecutive conversions. Each conversion is activated by its SOC signal. At the end of the 12 th conversion the calibration word is set. A. Ramp Generator The ramp voltage signal is obtained charging a grounded array capacitor with a very accurate current mirror. Since the voltage swing at the output node of the current mirror is 1 V, its output resistance has to be carefully evaluated. A simple Matlab script of the current mirror has demonstrated that the minimum output resistance value has to be about 5 GΩ, in order to avoid performance degradations. A low voltage current mirror has been implemented [6]. A regulated coscode structure has been introduced, as reported in Fig. 5. The negative feedback tends to keep constant, when the drain voltage of transistor M4 changes from 0 V to 1 V, the drain node of transistor M3. An output resistance of 6.5 GΩ has been obtained. As it can be seen in Fig. 1, the current mirror output node voltage is periodically reset to ground. For this reason the loop stability of the low voltage current mirror has to be carefully evaluated. In addition the power consumption of the loop operational amplifier has to be minimized, to accomplish the low-power target. An operational amplifier has been designed with 55 db of dc-gain, 2 MHz of bandwidth and a phase-margin of about 83. Despite the very low unity gain bandwidth there aren t any negative effects on internal nodes settling time, during all the conversion phases. The low voltage current mirror performance has been also evaluated in MonteCarlo Simulations, introducing the process/mismatch effects. The maximum current deviation obtained for each corner is less than 3.5%, see Fig. 6. The ramp slope variation due to this current deviation could degrade the performance of a 12 bit A-to-D converter but the calibration circuit, acting directly on the ramp slope, is able to compensate these variations. IV. SIMULATION RESULTS To validate the Successive-Approximations Calibration Circuit performance a rough A-to-D converter quantization error (QE) has been evaluated. Four corners have been set (see Tab. 1). Parameter Values Process slow-slow, fast-fast Temperature -40 C, 120 C Tab. 1 - Simulation Corners This QE has been evaluated for 391 points of the input range, chosen as multiples of ¼ LSB and ¾ LSB and spaced by 10 LSB. The ideal QE, considering these input values, should be a saw-tooth waveform between ±0.25 LSB, being the distance between the input values and the corresponding 47

91 Paper M2A3 PRIME 2013, Villach, Austria ideal quantized voltage of ¼ LSB. As shown in Fig. 7 and Fig. 8 this calibration circuit has allowed to obtain a quantization error very close to the ideal one. The maximum quantization error, in the worst case, is 1 LSB as shown in Fig. 9 and Fig. 10. Some input values, multiples of ¾ LSB, have been converted with the next quantized interval. This implies a QE equal to LSB. Fig. 9 Quantization Error in ss corner, 120 C. Fig. 5 - Improved Low Voltage Current Mirror. Fig Quantization Error in ff corner, 120 C. Fig. 6 - Current Mirror Process/Mismatch Deviation. V. CONCLUSIONS In this paper a Successive-Approximations Calibration Circuit for the integration capacitor on a single slope A-to-D converter has been presented. This circuit compensates the process/mismatch effects on the ramp signal slope through a 12 bit calibration procedure. An on-chip calibration circuit changes the capacitor value used to generate the ramp signal. Radiation effects that change the circuit operating point are also mitigated. The design has been realized in a 65 nm CMOS Technology. The proposed solution shares several blocks with the A-to-D converter and results in a consumption of only about 400 µw for the overall system. This solution results in an A-to-D converter maximum quantization error of 1 LSB in the worst case. REFERENCES Fig. 7 Quantization Error in ss corner, -40 C. Fig. 8 Quantization Error in ff corner, -40 C. [1] M. De Matteis, et al. A 550mV 8dBm IIP3 4th order analog base band filter For WLAN receivers. Solid State Circuits Conference, ESSCIRC rd European. Page(s): [2] D'Amico et al. "A 6.4 mw, 4.9 nv/ Hz, 24 dbm IIP3 VGA for a multi-standard (WLAN, UMTS, and Bluetooth) receiver" Analog Integrated Circuits and Signal Processing October 2009, Volume 61, Issue 1, pp 1-7 [3] Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G. CLARO- CMOS, a very low power ASIC for fast Photon counting with pixellated photodetectors. Volume 7. November pp: [4] D'Amico, S.; et al. A 255 MHz Programmable Gain Amplifier and Low-Pass Filter for Ultra Low Power Impulse-Radio UWB Receivers. Circuits and Systems I: Regular Papers, IEEE Transactions on Vol.59 n. 2. pp [5] G. Magazzù, A. Marchioro, P. Moreira, A rad-hard 8-channel 12-bit resolution ADC for slow control applications in the LHC environment, 7th Workshop on Electronics for LHC Experiments, Stockholm, Sweden, Sep 2001, pp [6] J. Ramirez-Angulo, et al. Low supply voltage high performance CMOS current mirror with low input and output voltage requirements IEEE Transactions on Circuits and Systems-II Express Briefs, Vol. 51, No. 3, March [7] D Amico, S. ; Delizia, P.; Baschirotto, A.; Azeredo-Leme, C.; Tavares, A. A 90nm- CMOS 1.8mW 87dB-SNR 3 rd order analog filter for GSM receivers. Research in Microelectronics and Electronics, PRIME Ph.D., pp:

92 A 32-Channel 12-bits 65nm Wilkinson ADC for CMS Central Tracker Tommaso Vergine, Marcello De Matteis, Andrea Baschirotto, A. Marchioro University of Pavia Italy. Department of Electrical Computer and Biomedical Engineering. Dept. of Physics, University of Milano-Bicocca, Milano, Italy University of Salento, Lecce Italy. Department of Innovation Engineering. CERN, 1211 Geneve 23, Switzerland. tommaso.vergine, marcello.dematteis, Abstract The ADC proposed in this paper is part of a larger VLSI (Very Large Scale Integration) circuit, called Detector Control Unit (DCU), whose aim is to monitor some critical quantities in the High-Energy Physical experiments inside the Large Hadron Collider (LHC). In particular it has been developed for the CMS (Compact Muon Solenoid) central tracker. The damage caused by radiation in such an environment requires that some key-parameters like leakage currents, local temperatures and supply voltages are carefully monitored in order to reduce failure events and improve overall performance. Indeed, CMOS integrated circuits, if exposed to very high radiation levels can experience large leakage currents and significant voltage/temperature variations. For this reason this monitoring system has been realized to provide real time information about the electrical/physical scenario of detectors. The ADC here shown, based on a Wilkinson single-slope architecture, has a resolution of 12 bits and is able to manage 32 input analog channels. Simulation results have shown a definitive 11 bit accuracy and a power consumption of about 500µW. The ADC has been designed in CMOS 65nm technology. It operates with a 40 MHz clock frequency. The final signal sample rate is about 5.5kHz. Keywords: A-to-D Converter, ADC, Low-Power, Radiation Hardness, High-Energy Experiments. I. INTRODUCTION CMOS integrated microelectronic circuits are more and more used in High-Energy Physic experiments. Even thought this approach is characterized by lacking reconfigurability and portability, it brings several advantages. First of all costs reduction and performance improvement. When CMOS read-out circuits are exposed to very high radiation levels performance degradation and breakdown events appear. Thus, in the CMS central tracker a monitoring system (named DCU[1]), has been implemented in order to provide real-time information about the status of detectors. An electrical/physical quantities monitoring (i.e. temperature, voltages and leakage currents) can increase by far the life-time and the performance of integrated circuits. Notice that, as it happens for detectors, also the monitoring system can be also exposed to radiation. Hence it has to be radiation-hard. Typically using devices wider than µm can increase the radiation tolerance (the shift of the threshold voltage is drastically reduced) but, when narrow channels are needed, proper layout techniques,for better immunity, can be considered. In this design both approaches have been used: transistors greater than a certain (minimum) area and with an annular gate layout[4]. The ADC is based on a /14/$31.00 c 2014 IEEE single-ramp (Wilkinson) architecture[2][3], although the large conversion time typically required by these converters is not an issue because the voltage supply, leakage and temperature time variations are more slower than the ADC conversion rate. The ramp generator circuit, one of the most important blocks in a Wilkinson ADC, has been carefully designed in order to provide an accurate and linear ramp signal over all the input full-scale. Also the comparator design has been challenging. It has to manage an input full-scale of 1 V with a voltage supply of 1.2 V. This paper is organized as follow. In Section II the DCU system is described, while in Section III the most important ADC specifications are addressed. Section IV presents all analog blocks that constitute the ADC. Finally, Section V reports the simulations results, and at the end of the paper Conclusions are drawn. II. SYSTEM OVERVIEW The DCU is a VLSI circuit designed for the CMS central tracker. Its aim is to monitor some key-parameters (both electrical and physical quantities) for the life-time of detectors. The silicon micro-strip detectors in the CMS tracker, when exposed to high level of radiation undergo several damaging phenomena. The two most important effects are an increase of the detector leakage current and a change in the depletion voltage. Thus, in order to extend life-time and to maintain integrity of detectors, a careful monitoring of environmental conditions is needed. This is done by the DCU. III. ADC SPECIFICATIONS The most important ADC converter specifications are obtained by system-level considerations and are presented in Tab. I. The ADC has to manage 32 analog inputs. The quantization error has to be lower than 1.5 LSB. The analog input fullscale is from 0 V up to 1 V. The maximum allowed power consumption, including power of digital circuits, has to be lower than 2 mw (from a single 1.2 V supply voltage) and the maximum conversion time has to be lower than 1 ms. IV. ADC ARCHITECTURE In a Wilkinson ADC the conversion is performed comparing the input signal with a linearly increasing voltage, generated on a capacitor by a fixed current. If the charging current is accurate and the capacitor is stable the voltage measured is simply proportional to the time needed to charge

93 Parameter Value # of channels 32 Resolution 12 bit Input Range 0V 1V Quantization Error (max) 1.5 LSB Power Consumption < 2mW Conversion Time < 1ms Voltage Supply 1.2V Table I: ADC Specifications the capacitor. In other words a voltage vs time conversion is carried out. The block scheme of the proposed ADC is shown in Fig. 1. As said previously, being the conversion algorithm based on a comparison with a ramp signal, every slope variation can critically affect the overall ADC performance. For this reason a careful design of the Ramp Generator circuit is here developed. In order to allow the digital conversion of several input signals, an analog multiplexer has been placed as first block of the ADC. Considering the input full-scale a design effort is required for Ramp Generator and the following blocks design because they have to manage signals very close to the voltage supply. An important design specification, to be taken into account, is that the external biasing current, essentially used to bias the ramp generator and the comparator, can be periodically tuned. This allows to compensate variations due to the technological spread and mismatch. On the other hand, it is very important to design the internal current mirrors able to manage the exact reference current without significant degradation due to the MOS transistor process/mismatch variations. The third component in the ADC is the Offset Cancellation block. If properly controlled during a conversion it allows to evaluate the comparator offset voltage and to obtain its conversion value. This is done because a digital offset compensation technique has been implemented. Regarding the comparator, it has been implemented with two complementary input stages (in order to manage the input full-scale without any biasing problems) and a latched output (in order to improve the compatibility between analog and digital blocks and to reduce static power). The last block is the Control Logic that is in charge of the ADC overall timing and control. The CLK signal is the external clock while SOC is the asynchronous start of conversion signal. To control the Offset Cancellation block, provide a controlled (stopped) clock (to reduce power consumption) to the comparator and give the 12 bits output converted value (DATA) are the main functions of the Control Logic block. The BUSY signal is an ADC activity flag. It indicates when the digital conversion result can be read and when the ADC is ready for another conversion. B. Clocked Comparator Figure 1: ADC Block Scheme The comparator plays a key role in the ADC performance. First of all, it has to be able to sense a difference at least of 1 LSB ( 244µV) between its input signals to guarantee a resolution of 12 bit for the ADC. In addition the parasitic (nonlinear) capacitance, seen from its inputs, has to be negligible if compared with the ramp generator capacitance. To guarantee low parasitic input capacitances it is enough to reduce the area of the input pair transistors but this typically leads to an increase of the comparator offset. However, this does not represent a issue because a proper conversion algorithm allows to cancel-out the offset contribution. For this reason the fixing of the parasitic capacitance issue has been preferred. The schematic of the comparator is shown in Fig. 2[6]. It has a rail-to-rail structure with two complementary input stages that share the same output circuit. In this way it is possible to manage the input signals, close to ground and voltage supply, also in the worst case scenario. On the other hand, without any equalization circuit, this comparator can easily exhibit a variable offset, as function of the input signal. Another consequence of the complementary input stages could be the cross-over distortion but it can be neglected, because this circuit is used as comparator. The output stage is latched instead and reset to ground with the positive edge of the clock. To reduce the kickback noise each input stage has been drawn in a continuous-time version (no-latched). A. Analog Multiplexer High-Energy Physics experiments are often characterized by a large number of signals to be processed. For this reason a multi-channels multiplexer, shown in Fig. 1, has been introduced. A decoder structure (controlled by 5 bits) has been used in order to minimize the unwanted effects of the unselected channels (e.g. leakage current and noise). Each switch has been designed as complementary switch. This approach allows to minimize the on-resistance, and consequently the input settling time, keeping a low circuital complexity. Figure 2: Rail to Rail Comparator C. Offset Cancellation Block The basic idea for the offset cancellation technique is to remove the contribution of the comparator offset directly into the digital domain (all other contributions to the offset voltage, like residual error in the ramp reset/sample phases or the

94 charge injection of switches are negligible). To do this the offset voltage is initially treated as an input signal and it is converted in a digital word using a suitable ramp signal (see Ramp Generator section). Thus, the Offset Cancellation Block essentially swaps the polarity of the comparator input signals to allow, jointly with the ramp generator, the offset evaluation (absolute value and sign) from the ADC Control Logic. For example a positive offset, modelled as a DC voltage source in series with the positive input of the comparator, has been assumed. As shown in Fig. 3, placing the input voltage on the comparator positive input and using a ramp signal, starting from V IN on the comparator negative input, it is possible to evaluate the digital conversion result of the offset voltage, V OFFSET [LSB]. On the other hand, using the same polarity of the comparator inputs but with a ramp signal starting from 0 V the conversion result will be V IN [LSB] + V OFFSET [LSB]. Thus, obtaining these two information, it is possible to cancel out the offset contribution, subtracting its value from the digital conversion of the input signal. If a negative offset is assumed the algorithm continues to work properly just swapping the polarity of the comparator inputs. Since the offset is not constant each input signal conversion is preceded by an offset calibration procedure. This implies a longer conversion time but it does not represent an issue because the maximum time required for a complete conversion (offset and analog input) is about 200µs 1ms (specification). Finally, considering that the ADC has to be able to digitalize V IN + V OFFSET also with V IN = 1V, the internal counting registers have been made using 13 bit to avoid overflows and the charging period has been extended. D. Ramp Generator Any deviation in the ramp signal, like wrong slope or poor linearity, can easily degrade the ADC overall performance. For this reason the ramp generator block has to be carefully designed. To realize a ramp signal from 0 V to 1 V (the input full scale) a grounded capacitor has been charged with a constant accurate current. This current source has to exhibit an output resistance in the GΩ order to minimize the charging current lost in the output resistance of the generator and to obtain a linear ramp signal. A Matlab model has provided 5GΩ as minimum needed output resistance. To obtain such a value a regulated low-voltage cascode current mirror has been designed, as shown in Fig. 4a [5]. The introduced negative loop increases the output resistance and keeps stable the operating point of the transistor M3, when M4 drain changes between 0V and 1V. This guarantees an output resistance of about 6GΩ. In order to reduce power consumption the operational amplifier has been designed with the minimum needed performance (i.e. 55 db of dc gain and 1.3 MHz of bandwidth). The achieved phase margin is about 80 o. The ramp generator has been completely validated with Monte Carlo tool, including also process and temperature variations. This design guarantees an error less than 5% on the ramp slope. Nevertheless, this deviation falls in the tunable range that the external biasing current can compensate. As said in the previous section, it is possible to use the same conversion algorithm for the input signal and the comparator offset. To convert the offset and store its value in the control logic a suitable ramp signal has to be used. As shown in Fig. 3, the offset contribution can be evaluated changing the starting point of the ramp signal (sampling V IN voltage on the ramp capacitor) and performing an analog to digital conversion. This allows a correct offset evaluation, as function of V IN. To obtain a ramp with a variable starting point a set of switches have been introduced. These deviate the charging current during the sampling and reset phases (controlling the φ signal) and pre-charge with V in or reset to ground the ramp signal. Note that the ramp charging period of the offset conversion can be made shorter than that of the input signal conversion, with the benefit of a faster conversion. Only few hundreds clock cycles (enough to convert the offset in the worst case) have been reserved for this phase. The ramp generator circuit is shown in Fig. 4b. Figure 3: Offset Conversion vs Input Conversion V. SIMULATION RESULTS Being the simulation time quite long to characterize the ADC for all input values, two simulation sets have been performed. In particular, nominal and transient noise simulations, with three input signals: 1.3 mv (5.5 LSB), 490 mv ( LSB) and 976 mv ( LSB). As illustrated in Fig. 5, 6, 7, the first set of simulations has provided results within ±0.5 LSB from the ideal results. In Fig. 5 and 7 the offset sign is positive. Since the Control Logic starts assuming a positive offset, only one conversion is needed to correctly digitalize its information. In addition, the Control Logic automatically connects the input and the ramp signal directly to the comparator with the proper polarity. On the other hand, in Fig. 6, the comparator offset has a negative sign. In this condition two conversion steps are needed for the offset conversion and the polarity of the comparator inputs is inverted. A slight degradation of the ADC performance is (a) Regulated Cascode (b) Ramp Generator Circuit Figure 4: Ramp Generator and Low Voltage Current Mirror

95 observed in Fig. 8, where the converter has been simulated using Transient Noise tool. Using the same input levels ten different simulations have been run demonstrating that the worst case accuracy is 11bits. The ADC power consumption is around 600 µw, including dynamic power due to the digital circuits. Figure 8: Conversion results in Transient Noise simulations Figure 5: V in = 5.5 LSB and V offset = 10 LSB Figure 6: V in = LSB and V offset = -50 LSB Figure 7: V in = LSB and V offset = 30 LSB VI. CONCLUSION In this paper a 32 Channel 12 bits Wilkinson ADC has been presented. It has been designed in 65 nm CMOS technology. Particular attention has been focused on the ramp generator and the comparator design. The ramp voltage has been obtained charging a grounded capacitor with a very accurate current mirror. The overall deviation of on the ramp slope, due to the process and mismatch, falls into the range that the external current can tune. The comparator has a rail-to-rail design with two complementary input stages that share the same output (latched) stage. The maximum quantization error, in transient noise simulation, is 1 LSB. The ADC performance are summarized in Tab. II. Parameter Value # of channels 32 Resolution 12 bit Input Range 0V 1V Quantization Error (max) 1 LSB Power Consumption 600 µw Conversion Time 200 µs Table II: ADC Performance REFERENCES [1] G. Magazzú et al., The detector control unit: an ASIC for the monitoring of the CMS silicon tracker, Nuclear Science, IEEE Transactions on, vol.51, no.4, pp.1333,1336, Aug [2] T. Vergine et al., A 32-channel 12-bits single slope A-to-D converter for LHC environment, IC Design Technology (ICICDT), 2013 International Conference on, vol., no., pp.139,142, May 2013 [3] T. Vergine et al., An automatic calibration circuit for 12-bits single-ramp A-to-D converter in LHC environments, Ph.D. Research in Microelectronics and Electronics (PRIME), th Conference on, vol., no., pp.45,48, June 2013 [4] Fan Xue et al., Gate-enclosed NMOS transistors, 2011 J. Semicond [5] J. Ramirez-Angulo et al., Low supply voltage high performance CMOS current mirror with low input and output voltage requirements IEEE Transactions on Circuits and Systems-II Express Briefs, Vol. 51, No. 3, March 2004 [6] Sung-Min Chin et al., A new rail-to-rail comparator with adaptive power control for low power SAR ADCs in biomedical application, Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol., no., pp.1575,1578, May June

96 A 65nm CMOS Technology Radiation-Hard Bandgap Reference Circuit Tommaso Vergine, Stefano Michelis, Marcello De Matteis, Andrea Baschirotto University of Pavia Italy. Department of Electrical Computer and Biomedical Engineering. Dept. of Physics, University of Milano-Bicocca, Milano, Italy University of Salento, Lecce Italy. Department of Innovation Engineering. CERN, 1211 Geneve 23, Switzerland. tommaso.vergine, marcello.dematteis, Abstract This paper presents a BandGap reference circuit with low sensitivity to temperature and to the voltage supply variations. It has been designed to be Radiation-Hard up to 1 GRad. This voltage reference has been developed in a commercial 65nm CMOS technology with 1.2 V of nominal voltage supply. A current-mode architecture has been chosen to allow the lowvoltage operation. Particular attention has been dedicated to circuit radiation hardness, in order to provide a stable voltage signal also with high radiation levels, like that of high-energy physics experiments. One of the advantages of CMOS scalingdown process is that the effects, due to radiation exposure, steadily decrease making circuits more and more robust. It follows that, in a conventional BandGap circuit, the most critical aspect could regard the diodes, or in general, the sensing elements. This design has been preceded by a series of measurements of two different sensing device in order to use that with the better radiation hardness.the BandGap reference circuit has been simulated with temperature range from -10 o C to 50 o C. The output value is around 330 mv with a curvature error of 0.05% in nominal conditions. The maximum output deviation in the absolute value is about ±1.1% and ±1.6% under process and mismatch respectively. The integrated noise from 0.01 Hz to 100 MHz is about 180 µv and the power consumption is 240µW. The radiation effects have been simulated modifying the models of devices according to measurements. In this case, thanks to a proper sizing, the output voltage shift is of a few millivolts. Keywords: BandGap voltage reference, Low-voltage, CMOS, Radiation Hardness, Enclosed Layout, High-Energy Experiments. I. INTRODUCTION Reference voltage generating circuits are widely used in analog and mixed-signal systems. Their aim is to provide an accurate voltage, independent on temperature and supply variations. Traditionally, the BandGap reference circuits generated the output voltage from the sum of the built-in voltage of a diode and the thermal voltage of kt/q, multiplied by a constant term but this precluded the low-voltage operation since the supply voltage would have to be larger than the 1.25 output voltage. The technological scaling-down process has forced designers to find alternative solutions to overcome the low-voltage supply issue. One of the most common approach, in sub-micron technologies, is the so-called current-mode [1]. The output voltage is obtained from the sum of two currents: the first is proportional to the built-in voltage of a diode and the second is proportional to the thermal voltage. This BandGap /14/$31.00 c 2014 IEEE design has been developed starting from the latter architecture. A particular attention has been also focused on the BandGap radiation-hardness. This is the additional specification required to work in high-energy physics experiments [2][3] or in the aerospace activities. Deep sub-micron technology are inherently highly tolerant to radiation, mainly due to the reduced oxide thickness[4]. Recombination of the radiation-induced charges is favoured by quantum tunnelling [5]. In a BandGap reference circuit it is possible to neglect the contribution of the radiation effects of transistors on the output voltage by a proper sizing. Nevertheless, just the effects of radiation on diodes can shift the output voltage of a BandGap of few hundreds millivolts. This can easily compromise, for example, the correct behaviour of all other analog blocks. To reduce the radiation damage effects on diodes a proper layout technique can be adopted. Indeed, surrounding the diode s p + diffusion with thin oxide (instead of shallow trench isolation field oxide - STI), it is possible to avoid the TID (Total Ionization Dose) radiation effects. This technique is called enclosed layout [5][7][8]. A resistive voltage divider has been inserted in the main circuit of the BandGap to allows the use of an operational amplifier (opamp) with the input stage of type PMOS. The voltage across diodes is typically about mv and, if directly applied to the opamp input, could generate biasing problems (especially in the worst case scenario - VDD 10% lower than nominal value and higher threshold voltage). A PMOS type opamp provides better performance especially in terms of unity gain bandwidth and flicker noise. This paper is organized as follow. In Section II the enclosed layout diode and its TID robustness are shown while in Section III the BandGap architecture is presented. Section IV shows the simulation results and at the end of this paper the Conclusions are drawn. II. ENCLOSED LAYOUT VS CONVENTIONAL DIODE A flux of high energetic charged particles and gammas leads to total ionization dose (TID) effects in MOS transistors [5]. Radiation creates, inside the oxide, free electron-hole pairs and the holes can be trapped at the interface between SiO 2 and Si. The electric field in the channel is changed by these holes presence with the consequence of a threshold voltage shift and leakage current. When the oxide thickness is lower than 12nm [6] the tunnelling of free electrons from channel into the gate oxide reduces drastically the number of holes, before they can convert to interface trapped states. This is why, in sub-micron technology, the main source of TID effects is the thick isolation oxide all around MOS devices. An enclosed

97 (a) EL Diode 3-D view. (a) Conventional Diode Current. (b) EL Diode vertical section. Figure 1: Enclosed Layout (EL) Diode layout can drastically reduce this problem because, as shown in Fig. 1a, the gate thin oxide of a transistor with an annular layout completely surrounds the source diffusion, distancing the STI oxide [7][8]. Fig. 1b shows how it is possible to obtain a diode from a PMOS with a enclosed layout. The gate contact, biased to VDD, avoids to the PMOS to turn on. The source diffusion becomes the anode and the n-well contact the cathode. In Fig. 2 a comparison between the I D vs V D of a conventional diode and an enclosed layout diode is shown at different TID values. The diffusion area is the same for both devices and is 0.5µm 2. The test of sensing devices has been done at the SEIFERT RP149 Xray machine installed at CERN. As shown in 2a, the characteristic of the conventional diode is strongly changed by radiation. The damage is larger for smaller values of bias current. In the past the BandGap circuits were designed using high biasing current to reduce the effects of radiation (introduction of leakage current), but this approach led to higher power consumption. In Fig. 2b the current of an enclosed layout diode is reported, for different TID values. The radiation degradation effects are much lower than the conventional diode, especially considering that it has been exposed up to 50 MRad (i.e. 20 MRad more than the conventional diode). This diode has been therefore used in the BandGap circuit design. III. BANDGAP VOLTAGE REFERENCE CIRCUIT The basic idea in a current-mode BandGap reference circuit is to combine two currents, with different temperature dependences, in order to obtain a stable output current/voltage. The area of the diodes plays a key role in the temperature dependence. In general, the temperature dependence of a semiconductor diode can be approximated as reported in Eq. 1. In other words, the voltage across a diode is IPTAT (Inversely Proportional To the Absolute Temperature with a proportional factor α) and its maximum value, occurring at 0 o K, is the BandGap voltage of silicon. (b) EL Diode Current. Figure 2: Current vs TID V D = V BG α T (1) where α is given by α = k ln (const/j). Thus, assuming the same current level through the two diodes and being designed with different areas, they work with different current densities. As consequence, they exhibit a different temperature trend. In addition, the temperature sensitivity can be increased using different biasing currents per each diode. The BandGap circuit is shown in Fig. 3. Eight replicas of D 1 have been used to realize D 2 and the transistor M 1 has been sized eight time larger than the transistor M 2 (better temperature sensitivity). Being the voltage across D 1 (for the chosen biasing current level) around 800 mv, two resistive voltage dividers have been necessary in order to use, without biasing problems, a PMOS type operational amplifier. The opamp keeps the two nodes V a, V b at equal voltages and consequently V a and V b (all voltage divider resistors have the same value). The current in the transistor M 2 can be expressed as reported in Eq. 2. I M2 = I Rs + I R2 + I D2 = 2 R s + R 2 2 R s R 2 V D1 + V R 3 (2) with V = V D1 V D2 and where the first term is IPTAT while the second is Proportional To the Absolute Temperature (PTAT). Changing the value of resistances it is possible to obtain an output current independent from the temperature variations. To work properly it is necessary that the ratio of the current densities of the two diodes (J D2 /J D1 ) is independent from temperature. Assuming the current in M 1

98 Figure 4: Operational Amplifier. Figure 3: BandGap Voltage Reference Circuit. and M 2 independent from temperature. As said before, the current that flows through D 2 (I D2 ) is PTAT. The current of R 2 is thus IPTAT. The resistor R 1, placed in parallel with D 1, deviates the current that passes through R 2 from D 1 making the current of D 1 PTAT too, as that of D 2. Being M 1 eight times greater than M 2, R 1 will be eight times lower than R 2. Assuming a 1:1 mirroring factor between M 2 and M 3 the output voltage is given by Eq. 3. A regulated cascode current mirror has been used in order to increase the accuracy of the output current [9]. Contrarily to the opamp in the main BandGap sub-circuit, this has to have an NMOS type input differential pair because the input voltage is next to 800 mv. The opamp in the output stage has been designed with the minimum DC gain and bandwidth, in order to reduce power consumption. In particular, it exhibits about 60 db of DC gain and 150 khz of unity gain bandwidth. The output capacitance C OUT allows to filter-out some noise and increase power supply rejection. V OUT = [ 2 Rs + R 2 V D1 + V ] R OUT (3) 2 R s R 2 R 3 A. Operational Amplifier and Offset Contribution Particular attention has to be focused on the operational amplifier and its offset voltage contribution on the output of the BandGap circuit. A symmetrical operational amplifier, compensated by Miller technique, has been chosen. Its schematic is shown in Fig. 4. This architecture allows to improve the BandGap overall power supply rejection since the opamp output node follows the voltage supply variation. In this way the V GS of transistors M 1, M 2 and M 3 of Fig. 3 remains constant. Also in this case it has been sized in order to provide the minimum required DC gain and bandwidth ( 65 db and 1.5 MHz). Considering the BandGap circuit without resistive divider networks, as shown in 5b. The nodes V a and V b represent the effective operational amplifier input. Considering also the opamp offset as a DC voltage in series with the negative input. The output current becomes as reported by Eq. 4. To make negligible the offset contribution the first two terms have to be greater than the last one. To do this the ratio A 2 /A 1 (areas of diodes) or the mirroring factor between M 1 and M 2 can be increased. Typically the latter is preferred, especially in radiation environments, because increasing the area of devices increases also the susceptibility to radiation effects. (a) Voltage Dividers. (b) No Voltage Divider. Figure 5: Opamp Offset Contribution. I OUT = V D1 R 2 + V R 3 V o ( 1 R R 2 Considering now the circuit of Fig. 5a. The output current is given by Eq. 5. This means that the opamp offset is more important in the output current value. Thus, it has to be carefully evaluated and sized, if a certain precision in the output current is needed. The input pair has been sized taking into account the Eq. 6 to minimize the offset voltage due to the MOS threshold mismatch [10]. In addition, the current mirrors of Fig. 4 have been sized in order to work in strong inversion, minimizing in this way the offset quantity linked to current mismatch. All transistors inside the BandGap circuit have been sized in order to minimize the effects due to the threshold voltage shift up to 1 GRad. PMOS transistors (with W or L > 5µm) exhibit a threshold shift of 60 mv while NMOS transistors (with W or L > 3µm) exhibit a shift of 20 mv. I OUT = 2 R s + R 2 2 R s R 2 V D1 + V R 3 IV. σ V th V o ) (4) ( ) R S R 3 R 2 (5) 1 W L (6) SIMULATION RESULTS Fig. 6 shows the nominal simulation of the BandGap output voltage, for a temperature swept from -10 o C to 50 o C. The mean value is about mv and the curvature error is only

99 Figure 6: BandGap Output Voltage in Nominal Conditions. Figure 8: BandGap Output Voltage under Mismatch Simulations. about 0.06%. The BandGap has been simulated also under Process-Voltage variations, according to the Tab. I. The output voltage is shown in Fig. 7. Also in this case the maximum curvature error is less than 0.1% and the maximum spread among all output values is about ± 1.1%. Fig. 8 shows the BandGap output voltage under Mismatch simulations. The maximum deviation is about ± 1.6%, mainly due to the offset voltage of the operational amplifier. It has been possible to simulate the radiation effects modifying the MOS threshold voltage in the model files of technology increasing the absolute value variation of the ouptu of about 2%. Parameter Value Process ss, ff, fs, sf, tt Voltage Supply 1.2, 1.08, 1.32 Table I: PV Simulation Corners Figure 7: BandGap Output Voltage under P-V Variations. V. CONCLUSIONS A Low-Voltage Rad-Hard BandGap voltage reference circuit has been proposed in this paper. The current-mode architecture has been chosen to allow low-voltage operation. Particular attention has been focused on the design of the sensing elements, i.e. the diodes to reduce drastically the TID effects (mainly leakage current and threshold shift). A proper layout technique has been adopted in order to replace the STI oxide all around diodes with thin oxide (Gate Oxide), much more efficient under radiation. The BandGap design has been made in a commercial 65nm CMOS Technology and the main performance is resumed in Tab. II. Parameter Nominal Process-Voltage Mismatch <V> mv mv mv σ mv 1.64 mv Curvature Error 0.06 % 0.15 % 0.4 % Power Consumption 200µW 240µW 230µW Noise(0.01Hz 100MHz) 170 µv 188 µv 190 µv Table II: Summarized Performance REFERENCES [1] Banba, H., et al. A CMOS bandgap reference circuit with sub-1- V operation, Solid-State Circuits, IEEE Journal of, vol.34, no.5, pp.670,674, May 1999 doi: / [2] Magazzú, G., et al. The detector control unit: an ASIC for the monitoring of the CMS silicon tracker, Nuclear Science, IEEE Transactions on, vol.51, no.4, pp.1333,1336, Aug [3] Vergine, T., et al. A 32-channel 12-bits single slope A-to-D converter for LHC environment, IC Design Technology (ICICDT), 2013 International Conference on, vol., no., pp.139,142, May 2013 [4] C. Claeys and E. Simoen, Radiation Effects in Advanced Semiconductor Materials and Devices, New York: Springer-Verlag, 2002, pp [5] Gromov, V., et al. A Radiation Hard Bandgap Reference Circuit in a Standard 0.13 m CMOS Technology, Nuclear Science, IEEE Transactions on, vol.54, no.6, pp.2727,2733, Dec doi: /TNS [6] Saks, N.S., et al. Radiation Effects in MOS Capacitors with Very Thin Oxides at 80K, Nuclear Science, IEEE Transactions on, vol.31, no.6, pp.1249,1255, Dec doi: /TNS [7] D. R. Alexander et al., Design issues for radiation tolerant microcircuits in space in Proc IEEE NSERC Short Course, 1996, pp. V-1 - V-54 [8] Lacoe, R.C., Improving Integrated Circuit Performance Through the Application of Hardness-by-Design Methodology, Nuclear Science, IEEE Transactions on, vol.55, no.4, pp.1903,1925, Aug doi: /TNS [9] J. Ramirez-Angulo, et al. Low supply voltage high performance CMOS current mirror with low input and output voltage requirements IEEE Transactions on Circuits and Systems-II Express Briefs, Vol. 51, No. 3, March 2004 [10] W. Sansen, Analog Design Essentials, 2006.