Design of solar insolation power logging system with ADC error testing and correction

Transcription

1 300 Journl of Scentfc & Industrl Reserch J SCI IND RES VOL 70 APRIL 011 Vol. 70, Aprl 011, pp Desgn of solr nsolton power loggng system wth ADC error testng nd correcton K Hrhrn*, T J Rmbbu, R K M Rjkumr nd V Abhkumr Deprtment of Electroncs nd Communcton Engneerng, Thgrjr College of Engneerng (TCE), Mdur , Ind Receved 9 November 010; revsed 08 Mrch 011; ccepted 10 Mrch 011 Ths study presents low cost solr nsolton meter wth ccurte mesurement of nherent non-lner trnsfer chrcterstcs of ADC. Mesured vlues were found close to ccurcy of hghly sophstcted nstruments (pyrnometer nd pyrhelometer), whch re costler for lrge-scle use, low commercl vlblty nd need for speclzed knowledge for hndlng. Test results over long durton under vryng sesonl condtons were lmost dentcl to those of clbrted stndrd pyrnometer. Keywords: ADC error correcton, Renewble energy, Solr energy, Solr rdton Introducton After nstllton of solr power system 1, perodcl loggng of solr rdton dt s mndtory to ensure sustned operton of solr system under vrous postons, nclnton of erth nd unpredctble wether condtons. Success of ny solr system depends hghly on ccurcy of ste specfc solr rdton dt vlble to the system,3. Mnul method for ADC error mesurement s very tedous nd tme consumng process 4. Ths study proposes novel desgn for smple, low cost solr nsolton meter nd logger, where Tme Tck 5 bsed pproch s used to mesure errors n the dt converter effcently. Epermentl Secton Solr Rdton Mesurement Solr nsolton s mesured s GSI = DSI + DSI...(1) where, globl solr rrdnce (GSI) s totl solr energy obtned, drect solr rrdnce (DSI) s mesure of solr energy drectly from the sun nd dffused solr rrdnce (DSI) mesures energy from sources other thn sun. Eq. (1) cn be epressed s 6 *Author for correspondence E-ml: khh@tce.edu GSI = DSI Cos() I + DSI...() where, I = Incdent ngle of bem. Solr rrdnce s mesured by trnsducer (PV cell or solr cell), whch converts short crcut current to n equvlent voltge, whch hs lner reltonshp wth ncdent solr energy. Whle mesurng ths vlue sometmes nstrumentl (ADC) error mght be dded to mesured vlue, ledng to ncorrect mesurement. For n 8-bt ADC, one hs totl of 8-1=55 levels. It s ssumed tht 00 th level hs n rrdnce of 1000 W/ m, wheres 55 th level represents full scle voltge (5V). Mmum mesured solr rrdnce (MMSR) s mesured s N ( 1) G MMSR =...(3) L G where, N, number of bts n ADC; G, ssumed mmum solr rrdnce; L G, level t whch G vlue s ssumed. Ths clculton s for del mesurement when there s no error n ADC. If there s ny error, Eq. (3) becomes s N ( 1) G MMSR= + error...(4) L G

2 HARIHARAN et l : DESIGN OF SOLAR INSOLATION POWER LOGGING SYSTEM WITH ADC ERROR 301 Solr Module R1 R Condtoned Rmp Source To An S/~R Swtch Rmp output Fg. Sgnl source module Fg. 1 Solr nsolton power loggng Irrdnce vlue for 55 levels s gven s MMSR = = 150W / m 00 Epermentl Setup Instrument Components SIPS (Solr Insolton Power Loggng System) conssts of power supply crcut, nput crcut, PIC, output crcut, crystl osclltor nd rel tme clock unts (Fg. 1). Power Supply Crcut Components present n power supply unt re: ) Rechrgeble bttery (00 mah current nd 11.1 V); ) B. IC7805, voltge regultor IC to gve constnt 5V DC to SIPS; nd ) Nose flterng cpctors (1 µf & 10 µf) used prllel to supply to rrest nose n power supply. Input Crcut Input crcut conssts of followng components: ) Solr pnel (SP), whch receve voltge nd gves to voltge dvder to forwrd to ADC, present n PIC mcrocontroller; ) Condtoned rmp source (CRS), nother nput to ADC, cn be selected by usng S/~R swtch. It s used to swtch nput between ether solr pnel or CRS. These two nput sources together (Fg. ) re known s sgnl source module (SSM); nd ) C.3*5 mtr keybord, n whch 15 swtches re plced s 3 rows nd 5 columns, nd used to brng SIPS to dfferent modes. Dfferent modes present n SIPS re: 1) Tme confgurton mode (TCM), used to set RTC tme, dte nd yer opton; ) Dt loggng mode (DLM), to log dt n two types of loggng (contnuous DLM, n ths mode solr dt s logged contnuously; nd sngle tme DLM, n ths mode dt s logged only once); nd 3) Idel tme tcks clculton mode (ITTCM), whch by usng sgnl source module for rmp sgnl clcultes del tme tcks, nd used for ADC error correcton. PIC PIC 16F877A (progrmmble nterfce controller) s 40 pn RISC CPU, whch s used to record nlog dt, gve control nformton & dt to LCD dsply, nd montor RTC (rel tme clock). It hs nbult ADC wth 5 ports to get nput nd send output. These ports connecton wth other eternl components re gven s follows: Port A - It hs fve pns (RA0-1st pn s used to get nput from ether SP or CRS; RA4-5 th pn used to get counter nput); Port B - It s connected to 3*5 mtr keybord, where 3 pns re used s nput nd 5 pns s output; Port C - In ths port, frst three pns (RC0, RC1, RC) re used s LCD RS (Regster Select) pn, LCD R/W (Red/Wrte) pn nd LCD En (Enble) pn, respectvely, RC3 pn s used s clock genertor for both RTC nd EEPROM SCL (Serl Clock), nd RC4 pn s used s serl dt for both RTC nd EEPROM SDA (Serl Dt for); Port D - All pns present n ths port re drectly connected to dt bus of LCD dsply unt; nd Port E - Ths port hs 3 pns (RE0, RE1 pns re connected to two swtches S1 nd S, nd RE s connected to S/~R swtch). Output Crcuts Output crcuts hve LCD dsply nd 4C51 eternl nterfced memory. In ths, SIPS system 16* LCD dsplys smpled nlog dt, dfferent modes n

3 30 J SCI IND RES VOL 70 APRIL 011 Anlog n A V ut_o Cn V ut A V lt V lt_o Fg. 3 Dgtlly swtchble rmp source Fg. 4 Slope detector crcut SIPS, RTC tme nd number of smpled nd stored dt n EEPROM.4C51. By usng I C concept, dt s stored. Mn dvntge of usng ths concept s usge of lesser number of pns to trnsfer dt. Crystl Osclltor nd Rel Tme Clock Unts RTC DS1307 IC s used to show rel tme n seconds, mnutes, hours, dte of month, month, dy of week, nd yer wth lep-yer compenston nd vld up to 100. Crystl osclltor (0 MHz) s hert of PIC controller. Serl port s used to progrm mcrocontroller from PC t the frst tme. M3 IC s used s n nterfce between PC nd mcrocontroller. ADC Error Correcton To reduce error ntroduced by ADC, system s clbrted by pplyng ether sne wve source or lner rmp source to ADC. In present SIPS system, dgtlly swtchble rmp source (DSRS) s used s nput (Fg. 3). DSRS genertes n dptve slope of rmp sgnls. To generte lner rmp, there re dfferent methods (Med-Sgnl 7, SSLAR Rmp sgnl 8, Low cost dptve rmp genertor 9 nd hgh precson rmp genertor 10 ), whose slope depend upon ther pssve devces. But present system requres rmp sgnl wth dynmclly vrble slope to fnd error of ADC. Intlly, swtch S1 s n off stte. Slope detector output s connected to mcrocontroller pn. Mcrocontroller polls the vlue of V lt_o. Cntr vrble begns countng f nd only f V lt_o = 0 nd Cntr =0. Cntr vrble counts del tme tcks for totl rmp sgnl. Ths dt s stored n memory nd del tme tck vlues re computed nd stored. Slope detector crcut (Fg. 4) s used to detect rmp sgnl level by usng two comprtors. Anlog rmp sgnl s fed s nput to non nvertng termnl of both comprtors, wheres correspondng threshold vlues re pssed to nvertng termnls. Voltges re determned by requred voltge level of rmp source. Ths crcut gves output s hgh only when lower comprtor output s hgh nd upper comprtor output s low. Ths output s gven to counter present n controller for fndng del tme tcks, fter whch cpctor s dschrged to 0V by usng nother swtch S tht s connected cross cpctor (Fg. 3). After settng requred slope rmp sgnl s nput, S/~R swtch s brought down to low stte (S/~R=0). Now, SIPS system wll operte n Prctcl Tme Tcks (tt) Clculton mode. Desred slope rmp nput s ppled to ADC. SIPS wll clculte Prctcl Tme Tcks (Fg. 5) of ech code occurrence (1Code =1LSB Sze) nd store t n memory. Frst rmp wll strt from V mn (0V) nd lnerly ncresng up to V m (5V). Intlly, counter s loded wth zero. Ths counter vlue wll ncrese f one gets sme smple output. Else ths vlue s stored n memory locton correspondng to nput code. Counter s gn ntlzed to zero nd bove process s contnued untl occurrence of mmum code or V m (For n 8bt ADC, mmum code = 8-1 = 55). Smples tken from redngs my be smplfed s second order equton s 11 n = y y y (5) where, n s number of collected smples, y s correlton fctor. s mesured nput V IN.

4 HARIHARAN et l : DESIGN OF SOLAR INSOLATION POWER LOGGING SYSTEM WITH ADC ERROR 303 f S/~R = = 1 Cntr = = 0, = 0; p [] = 0; p []! = 55 No Actul power, W/m Smple the /p f V lt_o = = 1 Come out from ths del tt mode. No Tme, h ) Cntr = Cntr + 1; p [] = Cntr; Cntr = 0; = + 1; Fg. 5 Prctcl tme tck clculton From Eq. (5), error of n ADC s modeled. From ths observton, vlues re found of coeffcents ( 0, 1, ) requred to model error. After error model s computed, ny nput s correspondngly corrected usng Eq. (5).The dt to be corrected s nput n Eq. (5). Results nd Dscusson SIPS system output wth nd wthout correcton (Fg. 6) compres well wth del pyrhelometer output usng present ADC error corrected output (Fg. 6b). Thus from obtned output, s tme ncreses, receved solr rdton ncreses, t noon obtned solr rdton s mmum, nd mnmum s obtned t 6.00 pm. Further from output, nonlner behvor of ADC ffects obtned solr rdton dt. In error plot (Fg. 7), SIPS system mesurements compred wth pyrhelometer for every 10 mn ntervl nd t s plotted. From error correcton lgorthm, corrected output s lmost equl to output obtned by pyrhelometer. SIPS system cn be used for long term dt loggng nd correltng the results for future pplcton usng fuzzy logc 1. Further, these nsolton mesurements re hghly helpful n systems where solr dt needs to be constntly montored nd verfed 13. For desgned system Actul power, W/m Fg. 6 ) Prctcl vlues vs error corrected vlues; b) Error corrected vlues vs pyrhelometer vlues Actul power, W/m Tme, h b) Tme, h Fg. 7 Error plot uses n ADC for dt converson, mcrocontroller for dt cqurng, nlyzng nd correcton, n EEPROM

5 304 J SCI IND RES VOL 70 APRIL 011 for dt loggng nd dsply/keypd for dsplyng mesured dt nd for fng settngs. SIPS system lso concentrtes on ADC error testng nd ts correcton to brng mesured redng closer to clbrted stndrd nstruments lke pyrhelometer. Conclusons A low cost solr nsolton system wth ADC error correcton s presented. Error corrected output of ADC s found lmost equl to prctcl hgh cost pyrhelometer output. Proposed SIPS system s low cost system, where cost of entre system sns solr sensor module s rnge of few thousnd rupees, whle cost of estng systems rnges from few ten thousnds to lkhs rupees. Automtc dt loggng s nother benefcl feture of ths system. Further, SIPS system s esly portble. It cn be nterfced to PC v serl port, to get dt logged n memory. SIPS system lso gves strtng tme nd ntervl between two dt loggng. Ths feture s hghly useful for scentfc reserch nd clmtc chnge montorng system. Lfe tme epectncy of SIPS system s bsed on EEPROM red/wrte cycles nd dt retenton perod. References 1 Al-Slymeh A, A generl model for the predcton of globl dly solr rdton on horzontl surfces for Ammn cty, Emrtes J Eng Res (EJER), 11 (009) L D H W, Lm J C & Lu C C S, A new pproch for predctng vertcl globl solr rdnce, Renew Energy, 5 (00) L D H W & Lm J C, Predctng solr rrdnce on nclned surfces usng sky rdnce dt, Energy Convers Mgmt, 45 (004) Bdrn O, Al-Slymeh A, El-Tous Y & Abdl W, Desgn nd testng of n nnovtve solr rdton mesurement devce, Energy Convers Mgmt, 51 (010) Hrhrn K, Gouthmrj S, Subrmnm B, Venktesh Bbu S R & Abhkumr V, A novel method for testng dgtl to nlog converter n sttc rnge, Amer J Appl Sc, 7 (010) Sukhtme S P, Solr energy: Prncple of Therml Collecton nd Storge (Tt McGrw-Hll, New York) 003, Zhng N, Yo S & Zhng Y, Rmp genertors for med-sgnl BIST nd ADC self-test, J Trns Tnjn Unv Sold-Stte- Crcuts, 38 (003) Blgopl S & Ay S U, An on-chp rmp genertor for sngleslope look hed rmp (SSLAR) ADC, n 5nd IEEE Int Mdwest Symp on Crcuts nd Systems (Unversty of Idho, Moscow) 009, Azs F, Bernrd S, Bertrnd Y, Mchel X & Renovell M, A low-cost dptve rmp genertor for nlog BIST pplctons, n 19th IEEE Proc VLSI Test Symp (Unversty des Scence et Technology du Lnguedoc, Montpeller), 001, Lee W-T, Lo Y-Z, Hsu J-C, Hwng Y-S & Chen J-J, A hgh precson rmp genertor for Low cost ADC test, n 9th IEEE Int Conf on Sold Stte nd Integrted Crcut Technology (ICSICT) (Unversty of Technology, Tpe, Twn) 008, Hrhrn K, Vsnthkumr P, Vrun G & Abhkumr V, A method for ADC error testng nd ts Compenston n Rtometrc Mesurements, Mesurement Sc Rev, 10 (009) Shhmlek P, Mhzoon M & Shhmlek P, Desgnng controller system for ntegrted solr power plnt usng fuzzy method, n ASME 008 Int Mech Engg Congr nd Epo (IMECE008) (Amercn Socety of Mechncl Engneers, Boston, Msschusetts, USA) vol 11, 008, Ho C K, Khls S S & Segel N P, Modelng on-sun tests of prototype sold prtcle recever for concentrtng solr power processes nd storge, n ASME 009 3rd Int Conf on Energy Sustnblty (Amercn Socety of Mechncl Engneers, Sn Frncsco, Clforn, USA) vol, 009,