Mismatch-tolerant Capacitor Array Structure for Junction-splitting SAR Analog-to-digital Conversion

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 ISSN(Prnt) ISSN(Onlne) - Msmatch-tolerant Capactor Array Structure for Juncton-splttng SAR Analog-to-dgtal Converson Youngjoo Lee,*, Taehyoun Oh, and In-Cheol Park Abstract A new juncton-splttng based SAR ADC wth a redundant searchng capactor array structure n. μm CMOS process to allevate capactor msmatch effects, s presented. The normalzed average power has a factor of.5 to the conventonal SAR ADC at -bt converson accuracy. Statstcal experments show the number of mssng codes resultng from the msmatch reduces by 95% for % unt-capactor msmatch rato, whle keepng the converson energy to that of the conventonal JS capactor array. Index Terms Capactor msmatch, low-power ADC, redundant ADC, SAR analog-to-dgtal convertor I. INTRODUCTION Along wth the flash analog-to-dgtal converter (ADC) [, ] and the ppelned ADC [, ], the successve approxmaton regster (SAR) ADC s wdely used for Nyqust-rate analog-to-dgtal converson. The charge-redstrbuton SAR ADC [5] has been conventonally used n many applcatons due to ts smple control scheme. However, the conventonal method s not effcent n the vewpont of energy consumpton, snce all the capactors are nvolved n the chargng and dschargng process. To reduce the energy Manuscrpt receved Aug. 5, ; accepted Mar. 7, 7 Department of Electrcal Engneerng, Pohang Unversty of Scence and Technology (POSTECH), Pohang 77, Korea Department of Electronc Engneerng, Kwangwoon Unversty, Seoul 97, Korea Department of Electrcal Engneerng, Korea Advanced Insttute of Scence and Technology, Daejeon, Korea E-mal : youngjoo.lee@postech.ac.kr consumed n the capactor array and control crcut, many papers have suggested energy-effcent capactor array archtectures and swtchng methods such as charge sharng [], capactor splttng [7, ] and comparator splttng [9]. More advanced works takng advantage of dfferental nputs have been reported n [, ]. Among the varous solutons, the juncton-splttng (JS) capactor array n [] conssts of multple capactor sectons, elmnatng power-hungry dschargng operatons. Based on the JS archtecture, a two-step charge-sharng method [] has been proposed to reduce the energy consumed n the capactve DAC. The lnearty of SAR ADC s constraned by the msmatches among capactor array durng mplementaton. To mprove the lnearty of ADC, several error-correcton algorthms have been reported. The hard-decson output was dgtally corrected n [], and a background dgtal calbraton method was presented n [5]. To reduce the dfferental nonlnearty (DNL) error, a nose-shapng method based on fngered regsters was proposed n [], and a flexble comparator n [7]. However, the above methods necesstate addtonal correcton blocks and complex control crcuts. Recent analyss reveals that provdng multple redundant paths s effectve n correctng such errors, and can be realzed at the cost of a lttle addtonal complexty [- ]. However, all the prevous redundant search algorthms assume relatvely small capactor msmatches, whch are vald for the conventonal capactor array. As the capactor sze of JS SAR ADC s ncrementally ncreased to generate the next voltage to be compared, the most sgnfcant bt (MSB) s determned wth the smallest capactors and can be sgnfcantly affected by a small capactor msmatch rato. In addton,

2 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR straghtforwardly applyng the conventonal redundant search to the JS capactor array would ncrease the total capactance remarkably, consumng much more energy than the orgnal JS capactor array does. Compared to complcated capactor sets n [], ths paper presents a smpler array structure and ts control scheme to allevate the capactor msmatch effects. To recover errors made n earler steps, we provde redundant search steps by modfyng the capactor array slghtly. In addton to the capactor msmatch effects, the redundant array s effectve n mprovng the lnearty nfluenced by several factors such as the parastc nput capactance of the comparator and the nonlnear characterstcs of swtches. A statstcal analyss s presented to mnmze the overheads by dervng the number of redundant steps approprate for a gven untcapactor msmatch. The rest of ths paper s organzed as follows: Secton II brefly descrbes prevous capactor array archtectures, and Secton III presents the proposed redundant capactor array and ts control scheme. The statstcal analyss on the number of redundant steps s presented n Secton IV, and smulaton results are summarzed n Secton V. Fnally, concludng remarks are made n Secton VI. II. PREVIOUS CAPACITOR ARRAYS Fg. shows the block dagram of an n-bt SAR ADC, usng a bnary-weghted capactor array for the dgtal-toanalog converter (DAC). Intally, all the capactors n the array sample the nput voltage, V n at a specfc tmng by closng S sample. In the conventonal SAR algorthm, the dgtal code correspondng to the nput voltage s found by conductng bnary search. Gven a prevously determned DAC code, the capactor array generates a voltage V out to be fed to the comparator by subtractng V n from the voltage correspondng to the code. As the SAR algorthm determnes one bt at a tme, n cycles are taken to generate the fnal n-bt dgtal code. The comparson result d determned at the -th step s fed back to the SAR control logc to produce the next dgtal code. In the frst step, all the bts of the dgtal code except the most sgnfcant bt (MSB) are set to zero to ndcate the half reference voltage. In the second step, the next dgtal code s generated by changng the MSB accordng to the comparson result and settng the second MSB to one. Ths process contnues untl we reach the last bt of the dgtal code.. Conventonal Capactor Array Archtecture Fg. shows a conventonal DAC capactor array [], whch conssts of n capactors and one dummy capactor of capactance C u. At the -th step, the output voltage s C V = - V + V H out n ref CH + CL where C H s the capactance connected to the reference voltage ( ) and C L s that connected to ground (GND) dependng on the decson pror to -th step. Note that C C H L S sample Capactor Array V out V n for DAC = å C for k such that S k k k k k u u SAR Control Logc Fg.. Block dagram of SAR ADC. S n- n- C u S n- S C u S S n-bt control sgnals C u S sample S S Fg.. Conventonal DAC capactor array. S sample, C u S S d V n () s closed, and = å C for k such that S k s closed. As S d s always closed durng the redstrbuton mode, the dummy capactor s always ncluded n C L. In summary, V out s dependent on the capactance rato of C H to the total capactance C tot of C H + C L. Durng the converson, the bottom plate of a certan capactor n the DAC capactor array s connected to GND at frst and then swtched to forcefully n the S ref d V out C u S d

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 9 S p rd Secton S p C u nd Secton S p C u st Secton C u S p S - S sample V out C u C u S - Step Step d = d = + + d = + d = d = + d = Step d = d = d = d = d = d = d = d = + Step next step. Dependng on the prevous decson, t can move back to GND n the followng step as well. Whle ths node s swtchng back and forth, t wastes energy. In the prevous capactor arrays ncludng the conventonal capactor array [5] and the splttng capactor array [7, ], all the capactors are nvolved n dervng V out so that C tot be always constant. Therefore, t s nevtable to swtch some of the capactors to make a new capactance rato needed for the next V out.. Juncton-splttng Capactor Array S sample Fg.. Overall structure of the JS capactor array. S - C u S - C u C u - C u d - d - d - d d V n - C u Fg.. Detaled structure of the -th JS capactor secton. A low-power juncton-splttng (JS) capactor array has been presented n []. Fg. shows the basc structure of the JS capactor array. Each box represents a capactor secton of whch structure s denoted n Fg., and the number n a box of Fg. s the total capactance of the capactor secton. Ths capactor array has addtonal seral swtches, S p to decde whether or not connect the top plates of the capactor sectons. In contrast to the conventonal capactor array that uses all the capactors and rearranges the swtches connected to the bottom plates to make a desred V out, the JS capactor array makes a new V out by appendng a capactor secton S ref - Fg. 5. Bnary search tree for the JS capactor array. to the prevous capactor array. How the JS capactor array works s llustrated n Fg. 5, where the denomnator and numerator represent C tot and C H, respectvely. Frst, the MSB, d, s determned by comparng the nput voltage wth.5, whch s acheved wth the two smallest capactors. Then, the next voltage to be compared s made by connectng the adjacent capactor secton, one at a tme. As shown n Fg. 5, the capactance of the next secton to be added to the denomnator, C Δtot, s the same as that of the current total capactance. In addton, the capactance to be added to the numerator, C ΔH, s determned by the sequence of the prevous comparator results. In partcular, C ΔH to generate C H at the -th step s ( - - ) C = d + d + L + d + d C, () DH - - u where C u represents the unt capactance. Therefore, the -th capactor secton conssts of capactors as shown n Fg., where d k s the k-th bt of the dgtal code. The total capactance of the -th secton s C u, whch s equal to the total capactance aggregated over all the prevous sectons. Each capactor s assocated wth two swtches controlled by one of the prevously determned bts. A capactor s connected to GND through swtch S j f the correspondng bt d j s, otherwse t s connected to through S j. Snce all the capactors controlled by the same bt can be connected together, a secton has a par of swtches for the left-most capactor and has connectons to the prevous sectons for the other capactors. Once the poston of a swtch n the JS capactor array s determned, the swtch never changes ts poston durng the redstrbuton mode. Therefore, the JS capactor array can acheve remarkable energy savng compared to the splttng capactor structure [7, ] and

4 9 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR the conventonal structure. III. PROPOSED CAPACITOR ARRAY. Proposed Redundant Search Although the JS capactor array s effectve n reducng energy consumpton, t s more susceptble to msmatch than the conventonal array s. Especally n the earler steps, the total capactance of the JS capactor array s much smaller than that of the conventonal array, whch means that the comparson s easly affected by a small capactor msmatch. The msmatch among unt capactors makes V out dfferent from the desred voltage, and thus the comparson may result n ncorrect decsons especally n the frst few steps of the redstrbuton mode. As the bnary search algorthm never overcomes such erroneous decsons, t s possble to have many mssng codes. The proposed redundant search allows multple paths to overcome ncorrect decsons n the earler steps. Fg. shows an example of the proposed search tree generated for 5-bt converson. The bnary steps and the redundant steps are denoted as Step Bx and Step Rx, respectvely. Lke the JS capactor array, the total capactance of the proposed array s ncreased by appendng a secton at a tme. To ntroduce multple recovery paths, each capactor secton s utlzed two tmes: one for a redundant step and the other for a bnary step. The redundant search starts from Step R as the earler steps cannot provde multple paths. If redundant steps occur all the tme between bnary steps except the frst one, the proposed search tree can employ n redundant steps for n-bt converson. Suppose that the rght chld s selected at Step B. In ths case, the sub-tree startng from the node of / contans leaf nodes rangng from / to /. If the left node of / s selected at Step B, the sub-tree covers leaf nodes rangng from / to 9/. As the two subtrees are overlapped a lot, the ncorrect decson made at step B can be corrected at the later steps, f step B does not decde that / s greater than / or / s less than /. The man pont of the proposed redundant array s that the earler ncorrect decsons can be corrected at the later steps. Ths means that the redundant capactor array allows a relatvely large capactor msmatch and thus can be bult wth small-szed unt-capactors. Another meanng s that rough comparson s allowed n the earler steps. Therefore, we can reduce the power consumed n the comparson by utlzng a low-precson comparator n the earler steps, whch s an addtonal advantage of the proposed redundant array []. As ths s not the focus of ths paper, however, we wll not go further. The comparator decson n Step B(x ) determnes the next comparson node of redundant Step Rx. Every node n Step B(x ) has a value of (k+)/ x, where k s a non-negatve nteger less than x. Based on the decson n Step B(x ), the next comparson value of voltage Rx s V Rx Fg.. Proposed redundant search tree for a 5-bt converson. The rregular redundant nodes are colored gray. db( x- ) + (k + ) + (- ) = - V n, () x+ where d B(x ) s the comparator decson n Step B(x ). Note that the denomnator n () s twce larger than that of Step B(x ) as the JS capactor array appends the same capactance as that of the prevous array. For example, a node of 5/ n Step B nduces a comparson node of / f the decson s. Otherwse, t leads to a comparson node of /. Two nodes located at the leftmost and the rght-most postons n a redundant step are rregular, but they are consdered to provde more multple paths. The rregular nodes, whch are shaded n Fg., are nvoked when the prevous decsons are all

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 9 zeros or all ones. After completng Step Rx, the current secton s reorganzed to derve the next comparson for Step Bx. As shown n Fg., the denomnator of Step Bx s equal to that of Step Rx, and the numerator s dfferent only by one, whch means that the numerator of Step Bx can be derved by changng the numerator of Step Rx slghtly nstead of appendng a capactor secton. The decson made n Step Rx s used to derve the comparson value of Step Bx as follows; V H d ( ) R x Rx Bx = - V n, () x+ where H Rx and d Rx are the numerator and the comparator decson of step Rx, respectvely. As the proposed search can provde n redundant steps for n-bt converson, the dgtal code s obtaned n n cycles. For the example of 5-bt converson, three redundant steps occur between bnary searches and the converson takes cycles. In the conventonal or the JS capactor array, the dgtal code for n-bt converson s derved by concatenatng the decson values. In other words, the dgtal code s n- n-- å d (5) = However, as the proposed redundant search can correct ncorrect decsons, the dgtal code should be decded consderng some correcton terms as follows; n- n- n-- n-- å db å = = n- n-- dr + + R, = ( ) db ( ) ( - ) + - å L where L (R ) s when we have to vst the left (rght) rregular node n Step R. Unlke the JS structure that monotoncally ncreases the numerator n each step, the proposed redundant search tree sometmes decreases the numerator n order to recover ncorrect decsons. As some capactors should be dscharged, the proposed search consumes more energy than the JS capactor does. However, the energy ncrease s not severe because the proposed redundant search does not ncrease the entre capactance. An () S p rd Secton S p C u nd Secton S p C u st Secton effcent control scheme s also proposed n the next subsecton to reduce the ncrement of energy consumpton.. Proposed Capactor Control S -L S sample S sample S -L S -R The capactor array for the proposed redundant search s depcted n Fg. 7. Compared to the JS archtecture, two swtches, S R and S R, are addtonally ncluded n the capactor array. Except these swtches, each capactor secton s exactly dentcal to that of the JS capactor array. After the sample mode, all the swtches on the top plate are open. In Step B, we close S R and S L and open S R and S L to compare.5 wth the nput voltage. After the comparson, the frst secton contanng C u capactance s connected by closng S p. At the same tme, two swtches n the frst secton are controlled by the prevous comparson result. After that, the adjacent capactor secton s serally appended n every two cycles to provde a redundant step and a bnary step alternatvely. Fg. llustrates how to generate the next comparson node after Step B. Fg. (a) depcts the method to generate the next comparson node of Step Rx from Step B(x ), where shaded are two rregular nodes n Step Rx. In Step Rx, the next secton s appended to ncrease the total capactance. In Step B(x ), we close two swtches, S R and S L, and open the counterparts, S R and S L. The numerator n Step B(x ) becomes a postve odd nteger, as only one of the frst two capactors n Fg. 7 s connected to. The odd numerator can be represented as k+, where k s an nteger n the range of [, x ). When the comparator decson n Step B(x ) s,.e., d B(x ) =, the next capactor secton to be appended s controlled to ncrease the numerator by k. More specfcally, the next capactor secton s controlled such C u S p C u S ref V n V out C u S -R Fg. 7. Proposed capactor array structure for redundant search.

6 9 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR Step B(x ) k + x d B(x ) = d B(x ) = -V n +.5 C u C u C u C u C u C u C u C Step B u d B = Step Rx (k+) + (k) x+ x+ (a) (k+) + (k+) + x+ x+ x+ -V n +.75 C u C u C u C u C u C u C u C u Step B d B = -V n +.75 Step Rx k x+ C u C u C u C u C u C u C u C u Step R d R = Step Bx d Rx = d Rx = (k ) + k + x+ x+ (b) Fg.. Constructon method for the proposed redundant tree. (a) Generaton of Step Rx from Step B(x ), (b) generaton of Step Bx from Step Rx. that k unt-capactors are connected to. To produce a proper numerator value, we close S R and open S R to connect the frst capactor to GND. As we dscharge one unt-capactor when d B(x ) =, the numerator of Step Rx n Fg. (a) has a mnus-one term. If all the prevous decsons ncludng d B(x ) are zeros, an rregular node of whch numerator s s consdered to provde more redundant paths. The rregular node s the left shaded chld n Fg. (a). In ths case, all the capactors n the capactor sectons ncludng the newly appended secton are connected to GND because all the prevous decsons are zeros. To make a numerator of requred n the rregular node, both the frst two capactors are connected to. In case of d B(x ) =, the control scheme s smlar to the above case. The newly appended secton s controlled to have k+ unt-capactors connected to by usng the prevous decsons. However, the frst capactor remans to be connected to by controllng S R and S R. Instead of changng the connecton of the frst capactor, we change the bottom plate of the second capactor from GND to by closng S L and openng S L. As one unt-capactor s newly connected to, the numerator n Fg. (a) has a plus-one term. If the prevous decsons are all ones, we consder an rregular node that s the rght shaded one n Fg. (a). In ths case, both the frst two capactors are connected to GND. Fg. (b) shows how to generate the comparson node -V n +.75 C u C u C u C u C u C u C u C u Step B d B = -V n +.75 C u C u C u C u C u C u C u C u Step R d R = -V n +.75 C u C u C u C u C u C u C u C u Step B d B = Fg. 9. Swtchng example of a -bt ADC. The correct dgtal code s, but a sngle error occurs n Step B. of a bnary Step Bx from the prevous Step Rx. For the sake of smplcty, the prevous comparson node n Step Rx s represented as k/ x+. As the numerator s odd n Step Bx, only one of the frst two capactors n Fg. 7 should be connected to. To make the numerator odd, we close S R and S L and open S R and S L. The rest capactors are controlled based on d Rx. If d Rx s, k untcapactors are connected to. Otherwse, k untcapactors are connected to. Note that the capactor sectons retan ther prevous values, f the prevous decsons have no errors. Only the error correcton paths may change the control sgnals of the capactor sectons and result n the energy-wastng dscharge process. As the error-correcton step changes the capactance connected to by at most one unt-capactance, the energy waste caused by the recovery step s not sgnfcant. Durng the converson based on the proposed redundant tree, the frst two capactors may charge or dscharge to produce the proper numerator. As the frst two capactors are the smallest ones, the energy consumpton of the capactors s relatvely smaller than those of the other capactors. The proposed control scheme s llustrated n Fg. 9 by

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 9 takng an example of -bt converson. Suppose that the nput voltage corresponds to a dgtal code of, and assume that an error occurs n Step B. Fg. depcts how the error can be recovered by usng redundant paths. Note that both the error-free path and the error recovery path reach the same destnaton correspondng to the dgtal code of. The error resultng from Step B, whch s shaded n Fg., s recovered through the followng steps, as the redundant search provdes multple error-correcton paths. As the frst two decsons are both ones, Step R consders the rregular node shown at the rght-hand sde of Fg.. In ths case, the frst two capactors are connected to GND. Hence, the error of Step B s recovered n Step R. In the second secton, the capactors connected to S and S are dscharged to provde a recovered comparson node and the path s recovered from the error. The comparson voltage of a redundant node s equal to the voltage compared n the prevous step. Due to the capactance ncreased by a factor of two, the comparson voltage of the redundant node s always more relable than the prevous comparson voltage whch s determned based on the smaller capactance. As the capactance rato resultng from small capactors s more subject to capactor msmatch, n addton, the proposed redundant search can be appled only to a few earler steps, f the capactor msmatch s small enough to guarantee a relable rato at the remanng steps. For Fg.. Error correctng sequence for the -bt ADC example. example, a -bt ADC can be mplemented by applyng the redundant search to the frst 5-bt converson and the tradtonal bnary search to the rest 5-bt converson. As the entre capactance s equal to that of the JS capactor array, the proposed redundant search s expected to consume almost the same energy whle enhancng the lnearty dramatcally.. Dscusson on Overheads The proposed algorthm can nsert n redundant steps maxmally, and thus the overall converson steps ncludng the samplng step can be ncreased to n when the full maxmum redundant steps are employed. Hence, the overall converson tme ncreases compared to the prevous bnary search. In addton, the redundant array ncrease the number of comparsons nvoked for a sample, ncreasng the energy consumed n the comparator for a sample, ncreasng the energy consumed n the comparator. However, the number of redundant steps s dependent on the capactor msmatch. If the capactor msmatch s small, t s suffcent to nsert a few redundant steps nto earler steps. In achevng - bt accuracy wth % capactor msmatch, for example, t s enough to nsert redundant steps. Wthout employng the redundant steps, we can ncrease the unt-capactor sze as an alternatve way to meet the specfed accuracy, whch ncreases the overall area and energy consumpton of the SAR ADC. As the proposed redundant array overcomes the capactor msmatch wthout enlargng the unt-capactor sze, t s an effectve method to acheve a low-area SAR ADC. In ths paper, we choose 5. ff as unt capactance, the smallest metal-nsulator-metal (MIM) capactor provded n a. μm CMOS process. Note that the number of redundant steps should be optmzed to mnmze energy and speed overheads. For ths, a statstcal approach s dscussed n Secton IV. In addton, smulaton results n [] show that the addtonal converson tme caused by the redundant search algorthm can be reduced by allowng the ncomplete settlng n the DAC. The control crcut of the proposed archtecture s more complex than that of the conventonal structure requrng only shfted regsters and smple control crcutry. The proposed redundant algorthm requres more complcated crcuts ncludng a recalculaton block

8 9 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR and a dedcated FSM for rregular steps. In a. μm process, the control crcut of the proposed archtecture requres % more equvalent gates compared to the conventonal method, f desgned for the full redundant case. The ncrement s also dependent on the number of redundant steps employed. If redundant steps are used to acheve -bt accuracy wth % capactor msmatch, for example, the ncrement s about 5%, whch s acceptable f we consder the lnearty mproved by the redundant steps. To mprove lnearty, prevous works have consdered calbraton technques [5, ] that are n general assocated wth much more complex algorthms and large hardware complexty. The adaptve background dgtal calbraton crcut presented n [5] requres a down converter, an average-calculaton unt and a truncaton unt. In [], the complcated analog nput stage havng multple-fngered regsters s used to compensate the peak DNL. Moreover, some calbraton technques necesstate an addtonal reference ADC. Note that the proposed work mproves the lnearty wthout usng such calbraton crcuts. As the proposed capactor array s connected through the top-plate swtches as shown n Fg. 7, the nonlnear characterstcs of swtches may degrade the lnearty. However, the prevous ncorrect decsons caused by the nonlnear characterstcs of the top-plate swtches can be corrected by multple paths enabled n the proposed redundant steps. Varous smulatons wll be dscussed n Secton V, ncludng the effects of nonlnear swtches. IV. STATISTICAL ANALYSIS More recovery paths can be enabled by provdng more steps, but the swtchng energy ncreases accordng to the ncreased number of redundant steps. Therefore, the number of redundant steps should be optmzed to acheve a low-energy, msmatch-tolerant SAR ADC. Gven a capactor msmatch rato, the requred number of redundant steps can be calculated statstcally. A practcal method to make a large capactor s to connect multple unt-capactors as shown n Fg.. Note that dummy capactors are placed around the connected untcapactors to remove n effect the msmatches between the unt-capactors at the boundary and those on the nsde []. For the statstcal analyss of msmatch effects, suppose that the capactance of the unt-capactor has a Gaussan dstrbuton wth mean C u and varance σ. A sngle unt-capactor C can be modeled as C = C + e C e N s (7) u u, ~ (, ), where e s the msmatch rato of a sngle unt-capactor. If we set the maxmum msmatch rato of the untcapactor, e max, to σ, 99.7% of unt-capactors are assocated wth capactor msmatch ratos less than e max. For the large capactor C N generated by connectng N unt-capactors, we have a statstcal model as follows; N N = = u + N u, N ~ (, ). = C å C NC e C e N Ns () Wth a confdence of 99.7%, therefore, the maxmum msmatch rato of C N s NC e = e = e. (9) u Nmax max max NCu N Note that the maxmum msmatch rato of C N s decreased by a factor of N compared to that of one unt-capactor, whch means that the smaller capactor s more subject to capactor msmatch than the larger capactor does. In the bnary search, the comparson voltage at the -th step s CH H Cu + eh Cu = C C + e C + e C Dummy unt capactors C u C u C u C u C u C u Fg.. Layout technque for drawng a large capactor. u H u L u, () where H and L stand for the numbers of unt-capactors

9 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 95 Table. Maxmum tolerance of capactor msmatch for varous redundant ADC confguratons Redundant level connected to and GND, respectvely. For n-bt converson, the error from the msmatch should be less than / n. Usng (9) and (), we can derve constrants to be satsfed for the 99.7% confdence level. At Step (- ) n whch the total capactance s C u, the constrants are Therefore, e max H + H emax H < + n + H e - - H e max max max H - H emax H > - n - H e + - H e < max n n- H - ( H - - H )( H + ) () () The nequaltes n () are consderng two extreme cases of (). The upper nequalty consders one case that all the unt-capactors related to H have postve msmatches and the other unt-capactors have negatve msmatches, and the lower consders the opposte. From (), we can calculate the msmatch rato allowed for every node n the bnary search. The maxmum rato at Step ( ) assocated wth unt-capactors, e max, can be calculated by explorng all the possble values of H as follows; e - max 5-bt ADC = MIN -bt ADC 7-bt ADC -bt ADC 9-bt ADC -bt ADC step steps steps steps steps steps steps steps n H - ( H - n- - H )( H + ) () Gven a desred precson and a unt-capactor msmatch rato, we can dentfy a relable step by Table. Swtches and converson steps requred n n-bt ADCs ADC type evaluatng (). For varous confguratons, Table shows the maxmum msmatch rato that can be tolerated n each redundant step. If the msmatch rato s %, for example, Table says that 7 redundant steps should be used for a -bt ADC. V. SIMULATION RESULTS. Swtchng Energy Consumpton To compare the swtchng energy n the capactor arrays, the C-level smulator s newly developed to model several -bt SAR ADCs ncludng the conventonal capactor array, the splttng capactor array [], the JS capactor array [] and the proposed redundant array. Table compares four methods n terms of the number of converson steps, the number of swtches and the normalzed energy consumpton. In countng the number of swtches, we nclude the swtches requred n the sample and hold modes. The total capactance requred n each structure s not presented n Table, because all the structures have the same amount of capactance. Compared to the JS capactor array, Fg. (a) shows the energy consumed n the proposed capactor array havng x redundant steps. All the values are normalzed by the average energy of the conventonal structure. Note that the maxmum number of redundant steps n the proposed archtecture s for -bt converson. Fg. (b) reveals that the average energy dsspated n the proposed archtecture ncreases as the number of redundant steps ncreases. However, the ncrement s not severe even compared to the average energy consumpton of the JS capactor array. The proposed redundant array saves about 5% of energy compared to the conventonal array.. Accuracy of Converson Converson steps Requred Swtches Normalzed Average Power Conventonal [] n+ n+5. Splttng Cap [7] n+ n+.5 Orgnal JS [] n+ n+.5 Redundant (n steps) n- n+.5 For the sake of precse comparsons, the converson

10 9 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR Nomalzed energy..5 Conventonal Juncton-Splttng redundant steps 7 redundant steps redundant steps Accuracy (bts) Juncton-Splttng redundant steps redundant steps redundant steps 5 redundant steps 7 redundant steps redundant steps.. 5 Dgtal code (a) Normalzed nput capactance of the comparator Nomalzed energy... (a) Juncton-Splttng redundant steps redundant steps redundant steps 5 redundant steps 7 redundant steps redundant steps.. Conv JS RS RS RS 5 RS RS 7 RS RS DAC type (b) Fg.. Swtchng energy dsspated n the redundant DAC and comparsons wth prevous works (a) Comparson for each nput code, (b) Average energy comparson for the conventonal (Conv), the juncton-splttng (JS) and the proposed redundant capactor arrays, where RS stands for redundant steps. accuracy s expressed n unts of bt as follows; ( ) Accuracy = log Error () MAX where Error MAX represents the maxmum error between the deal voltage, that changes output dgtal code, and the actual one resultng from the capactor array. If there are mssng codes, the accuracy becomes lower than the desred resoluton. To optmze the number of redundant steps, the accuracy of -bt converson resultng from varous confguratons s plotted shown n Fg.. Accordng to Table obtaned by (), we need to nsert 7 redundant steps f the capactor msmatch rato s %. In Fg., the accuracy of bts s acheved by usng 7 or redundant steps for % capactor msmatch. Note Accuracy (bts) Normalzed parastc capactance of a swtch (b) Fg.. Accuracy mprovement (a) for the nput capactance of the comparator, (b) for the parastc capactance of top-plate swtches. The capactance s normalzed by C u. that the statstcal analyss s consstent wth the smulaton result. In the SAR ADC, some analog components such as comparators and swtches have to be carefully desgned, because ther characterstcs affect the lnearty drectly. The parastc capactors connected to the top plate of the DAC capactor array shown n Fg. may nvolve n the charge redstrbuton process and degrade the lnearty severely. Especally, the orgnal JS capactor array s easly affected by the parastc capactors n the earler redstrbuton steps assocated wth small capactance. As

11 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 97 the comparator has a relatvely large nput capactance sometmes, the nput capactance can affect the frst few steps serously, leadng to lots of errors. Fg. (a) shows how the nput capactance of the comparator degrades the accuracy of converson, where the nput capactance s normalzed by the unt-capactance. To take nto account only the effect of the nput capactance, the smulaton assumes that there s no msmatch n the capactor array. When the nput capactance s only 5% of C u, the accuracy s severely degraded f redundant steps are not used at all. However, errors from the nput capactance can be almost recovered by usng redundant steps. As shown n Fg. (a), the full redundant case mantans -bt accuracy untl the nput capactance ncreases up to 5% of C u. In the JS array that generates the next comparson voltage by appendng a capactor secton, a swtch s used to connect the top plates of adjacent two sectons. There are two parastc factors to be consdered n the desgn of the swtches: resstance and capactance. The parastc resstance affects the redstrbuton tme a lttle, but the nfluence can be gnored n our SPICE smulatons. The parastc capactance can reduce the accuracy. Fg. (b) shows how the accuracy s affected by the parastc capactance, where the parastc capactance s normalzed by C u. Though the JS capactor array loses ts accuracy even f the parastc capactance s as small as.5%, the full redundant capactor array can tolerate up to 5%.. Lnearty The redundant search s also effectve n enhancng the lnearty of the ADC, especally the ntegral nonlnearty (INL) and dfferental nonlnearty (DNL), as t can drastcally reduce the number of mssng codes. For - bt converson, Fg. depcts how the INL and DNL change accordng to the ncrease of capactor msmatch. The INL and DNL of the JS array are severely deterorated by capactor msmatch, but the lnearty s recovered by adoptng the full redundant search. Fg. 5 shows the peak INL and DNL caused by capactor msmatch, where we can see that nsertng redundant steps s an effcent way of reducng them. The peak INL and DNL caused by the nput capactance of the comparator and the parastc capactance of the top-plate INL INL Dgtal code Capactor msmatch.5.5 Dgtal code DNL Capactor msmatch.5.5 (a) DNL (b) Dgtal code swtches are shown n Fg. and 7, respectvely. In addton, charge njecton may reduce the lnearty and ncrease the number of redundant steps requred. As the charges stored n the capactor array can be charged or dscharged by the top-plate swtches, the charge njecton may reduce the lnearty of ADC severely. The amount of njectng charges s modeled as an addtonal capactor connected to or GND. The addtonal capactors correspondng to charge njecton are connected to or GND n a random manner, and assumed to have the same capactance to smulate the worst case. Fg. depcts the peak INL and DNL caused by the charge njecton, where the capactance value correspondng to charge Dgtal code Capactor msmatch.5.5 Capactor msmatch.5.5 Fg.. INL and DNL of a -bt ADC for (a) the JS capactor array, (b) the redundant array wth redundant steps. Peak INL Juncton-Splttng redundant steps redundant steps Capactor msmatch rato Peak DNL Juncton-Splttng redundant steps redundant steps Fg. 5. Peak INL and DNL for a -bt ADC Capactor msmatch rato

12 9 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR Peak INL 5 Juncton-splttng redundant steps redundant steps Normalzed nput capactance Peak DNL njecton s normalzed to the unt capactance. The proposed redundant array s effectve n mprovng the lnearty that can be degraded by charge njecton. VI. CONCLUSIONS Normalzed nput capactance In ths paper, we have presented an effcent redundant search algorthm sutable for the JS capactor array and ts swtchng algorthm that allevates the effects of capactor msmatch and parastc capactors. To recover ncorrect decsons, redundant steps are adopted by modfyng the structure of the JS capactor array slghtly. The proposed redundant search, whch s enabled by nsertng two addtonal swtches nto the orgnal JS array, enhances the lnearty resultng from capactor msmatch and parastc capactors wthout much 5 Juncton-splttng redundant steps redundant steps Fg.. Peak INL and DNL caused by the nput capactance of the comparator. Peak INL Juncton-splttng redundant steps redundant steps Normalzed parastc Capactance of a swtch Peak DNL Juncton-splttng redundant steps redundant steps Normalzed parastc capactance of a swtch Fg. 7. Peak INL and DNL caused by the parastc capactance of top-plate swtches. Peak INL 5 Juncton-splttng redundant steps redundant steps Normalzed capactance for charge njecton Peak DNL 5 Juncton-splttng redundant steps redundant steps Normalzed capactance for charge njecton Fg.. Peak INL and DNL caused by the charge njecton. ncreasng swtchng energy. In addton, the number of redundant steps approprate for a gven msmatch rato has been analyzed statstcally to mnmze the overheads of the proposed redundant array. Smulaton results show that the proposed redundant search recovers most of the lnearty degradaton caused by msmatch, parastc capactors and nonlneartes of swtches, whle keepng the energy consumpton smlar to that of the JS capactor array. ACKNOWLEDGMENTS Ths work was supported by the Natonal Research Foundaton (NRF) grant funded by the Korea government (MSIP) (RCB759) and the IC Desgn Educaton Center (IDEC). REFERENCES [] J.-I. Km, D.-R. Oh, D.-S. Jo. B.-R.-S. Sung, and S.-T. Ryu, A 5nm CMOS 7b GS/s.7 mw flash ADC wth cascaded latch nterpolaton, IEEE J. Sold-State Crcuts, Vol. 5, No., pp. 9-, Oct. 5. [] H.-Y. Lee, D.-G. Jeong, Y.-J. Hwang, H.-B. Lee, and Y.-C. Jang, A -V.-GS/s 5.5-ENOB CMOS flash ADC usng tme-doman comparator, J. Semcond. Technol. Sc., Vol. 5, No., pp. 95-7, Dec. 5. [] J. Yuan, S. W. Fung, K. Y. Chan, and R. Xu, A -bt MS/s 5. mw ppelned ADC wth nterpolaton-based nonlnear calbraton, IEEE Trans. Crcuts Syst. I, Reg. Papers, Vol. 59, No., pp , Mar.. [] J.-S. Park, et al., A b MS/s three-step hybrd ppelned ADC based on tme-nterleaved SAR ADCs, J. Semcond. Technol. Sc., Vol., No., pp. 9-97, Apr.. [5] J. L. McCreary and P. R. Gray, "All-MOS charge redstrbuton analog-to-dgtal converson technques," IEEE J. Sold-State Crcuts, vol. SC-, no., pp. 7-79, Dec [] J. Crannckx and G. V. D. Plas, "A 5fJ/converson-step -to-5ms/s -to-.7mw 9b charge-sharng SAR ADC n 9nm dgtal CMOS," n IEEE Int. Sold-State Crcuts Conf. Dg. Tech.

13 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.7, NO., JUNE, 7 99 Papers, 7, pp. -7. [7] B. P. Gnsburg and A. P. Chandrakasan, "5-MS/s 5-bt ADC n 5-nm CMOS Wth Splt Capactor Array DAC," IEEE J. Sold-State Crcuts, vol., no., pp , Apr. 7. [] B. P. Gnsburg and A. P. Chandrakasan, "An Energy-Effcent Charge Recyclng Approach for a SAR converter Wth Capactve DAC," n Proc. IEEE Int. Symp. Crcuts Syst., 5, pp. -7. [9] W. Y. Pang et al., "A -b 5-KS/s Low Power SAR ADC wth Splttng Comparator for Bo- Medcal Applcaton," n IEEE Asan Sold-State Crcuts Conf. Dg. Tech. Papers, 9, pp [] C. C. Lu et al., A.9mW -bt 5-MS/s SAR ADC n.um CMOS Process, n Proc. IEEE Symp. VLSI Crcuts, 9, pp. -7. [] C. C. Lu et al., A -bt 5-MS/s SAR ADC Wth a Monotonc Capactor Swtchng Procedure, IEEE J. Sold-State Crcuts, vol. 5, no., pp. 7-7, Apr.. [] J. S. Lee and I. C. Park, "Capactor Array Structure and Swtch Control for Energy-Effcent SAR Analog-to-Dgtal Converters," n Proc. IEEE Int. Symp. Crcuts Syst.,, pp. -9. [] W. Yu et al., Two-step splt-juncton SAR ADC, Electron. Lett., vol., no., pp. -, Feb.. [] K. Bacrana, "A -bt Successve-Approxmaton- Type ADC wth Dgtal Error Correcton," IEEE J. Sold-State Crcuts, vol. SC-, no., pp. - 5, Dec. 9. [5] W. Lu and Y. Chu, "Background dgtal calbraton of successve approxmaton ADC wth adaptve equalsaton," Electron. Lett., vol. 5, pp. 5-5, Apr. 9. [] F. Ohnhaeuser and M. Huemer, "Methods to elmnate dynamc errors n hgh-performance SAR A/D converter," n Proc. IEEE Int. Symp. Crcuts Syst.,, pp. 9-. [7] V. Gannn et al., "An uw 9b MS/s Nose- Tolerant Dynamc-SAR ADC n 9nm Dgtal CMOS," n IEEE Int. Sold-State Crcuts Conf. Dg. Tech. Papers,, pp. -9. [] M. Hesener et al., "A b MS/s Redundant SAR ADC wth MHz Clock n. CMOS," n IEEE Int. Sold-State Crcuts Conf. Dg. Tech. Papers, 7, pp. -9. [9] F. Kuttner, "A.V b MSample/s Non-Bnary Successve Approxmaton ADC n.um CMOS," n IEEE Int. Sold-State Crcuts Conf. Dg. Tech. Papers,, pp [] T. Ogawa et al., "SAR ADC algorthm wth redundancy," n Proc. IEEE Asa Pacfc Conf. Crcuts Syst.,, pp. -7. [] Y. Lee and I.-C. Park, Capactor array structure and swtchng control scheme to reduce capactor msmatch effects for SAR analog-to-dgtal converters," n Proc. IEEE Int. Symp. Crcuts Syst.,, pp. -7. [] A. Johns and Ken Martn, Analog Integrated Crcut Desgn. New York: John Wley & Sons, Inc., 997. [] Y. Lee, J. Song, and I.-C. Park, Statstcal modelng of capactor msmatch effects for successve approxmaton regster ADCs," n Proc. IEEE Int. SoC Desgn Conf.,, pp. -5. Youngjoo Lee receved the B.S., M.S. and Ph.D. degrees n electrcal engneerng from Korea Advanced Insttute of Scence and Technology (KAIST), Daejeon, Korea, n, and, respectvely. Snce February 7, he has been an Assstant Professor n the department of Electrcal Engneerng, POSTECH, Pohang, Korea. Pror to jonng POSTECH, he was wth Interunversty Mcroelectroncs Center (IMEC), Leuven, Belgum, from May to February 5, where he researched reconfgurable SoC platforms for software-defned rado systems. From March 5 to February 7, he was wth the Faculty of the Department of Electronc Engneerng, Kwangwoon Unversty, Seoul, Korea. Hs current research nterests nclude the algorthms and archtectures for embedded processors, ntellgent transportaton systems, advanced error-correcton codes, and mxed-sgnal crcut desgns.

14 YOUNGJOO LEE et al : MISMATCH-TOLERANT CAPACITOR ARRAY STRUCTURE FOR JUNCTION-SPLITTING SAR Taehyoun Oh receved the B.S. and M.S. degrees from Seoul Natonal Unversty, Seoul, Korea, n 5 and 7, respectvely, and the Ph. D. degree from the Unversty of Mnnesota, Mnneapols, MN, USA, under the supervson of Dr. R. Harjan, all n electrcal engneerng. Hs doctoral research focused on hgh-speed I/O crcuts and archtectures. Durng the summer of, he worked on I/O channel modelng at AMD Boston Desgn Center, MA. In the fall semester of, he researched I/O archtecture and jtter budgetng of the lnk wth Intel Corporaton. In the fall of, he joned the IBM System Technology Group, where he worked on performance verfcaton of hgh-speed decson feedback equalzer for server processors. In the sprng of, he joned the Department of Electronc Engneerng, Kwangwoon Unversty, Seoul, Korea, as an Assstant Professor. In-Cheol Park receved the B.S. degree n electrcal engneerng from Seoul Natonal Unversty, Seoul, Korea, n 9, and the M.S. and Ph.D. degrees n electrcal engneerng from the Korea Advanced Insttute of Scence and Technology (KAIST), Daejeon, n 9 and 99, respectvely. Snce June 99, he has been an Assstant Professor and s currently a Professor wth the Department of Electrcal Engneerng, KAIST. Pror to jonng KAIST, he was wth the IBM T. J. Watson Research Center, Yorktown, NY, USA, from May 5 to May 99, where he researched hgh-speed crcut desgn. Hs current research nterests nclude computer-aded desgn algorthms for hgh-level synthess and very large scale ntegraton archtectures for general-purpose mcroprocessors.