California, 4 University of California, Berkeley

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1 Dversty Processng WCDMA Cell earcher Implementaton Ahmed M. Eltawl, Eugene Grayver 2, Alreza Targhat, Jean Francos Frgon, Kambz hoarnejad, Hanl Zou 3 and Danjela Cabrc 4 Unversty of Calforna, Los Angeles, 2 Aerospace Corporaton, Elsegundo, Calforna, 3 Broadcomm Corporaton, Irvne, Calforna, 4 Unversty of Calforna, Berkeley ahmed@ee.ucla.edu Abstract- In ths paper algorthmc and mplementaton nnovatons for a novel dversty processng based WCDMA synchronzaton system are presented. The system employs a dual antenna front end system and a three stage ppelned synchronzaton technque to acheve slot, frame and code synchronzaton. The slot boundary secton employs a hybrd matched flter/correlator approach for maxmum flexblty and to mnmze power consumpton. The secondary stage secton employs a novel maxmum lkelhood algorthm to perform frame boundary dentfcaton, whle the thrd and fnal stage shares the RAKE engne correlators to perform code dentfcaton. The system was mplemented n a 0.8 µm CMO process wth poly and 6 metal layers. The total standard cell count s 28k mplemented n mm 2. The average power consumed over a full frame s 2 mw from a.8 V supply. I. INTRODUCTION Wth the advent of thrd generaton (3G) cellular systems, data rates that users expect and the assocated Qualty of ervce (Qo) requrements demanded by network provders have soared n comparson to second generaton (2G) systems. Furthermore, the fact that these systems have to meet a tght power budget, ft wthn the sze constrants of the next generaton handsets as well as meet the cost constrants of a termnal devce, have provded addtonal challenges. One technque that has shown tremendous potental n solvng the dlemma of provdng hgh data rates whle causng a mnmal overhead n complexty s spatal dversty. The feasblty of such an approach has been made possble due to advances n RF crcut technques and ntegraton []. Dversty processng drectly translates to ncreased capacty and better coverage as well as less watng tme durng the ntal synchronzaton phase. Ths paper presents the synchronzaton secton of a dual antenna recever desgned for 3G WCDMA. Fgure llustrates the mprovement n the average watng tme usng a dual antenna structure versus a sngle antenna soluton. The average watng tme s defned as the tme elapsed startng at the orgnaton of a cell search for the transmttng base staton untl a successful lock s declared. The paper s organzed as follows; secton II descrbes dversty processng and ts mpact on synchronzaton access tme. ectons III, IV, V dscuss the prmary, secondary, and fnal synchronzaton stages, respectvely. ecton VI presents the AIC mplementaton of the system. The paper s concluded n ecton VII. II. DIVERITY PROCEING Usng dual antennas at the moble staton presents the demodulaton core wth extra copes of the sgnal that have statstcally sem-ndependent nose. By combnng these sgnals n a maxmal rato combnng scheme the sgnal to nose rato (NR) can be sgnfcantly mproved. Ths mprovement can be demonstrated at all stages of the demodulaton algorthm startng wth the synchronzaton stages and endng at the fnal demodulaton stage. Cell search n W-CDMA s performed usng three channels, namely the Prmary ynchronzaton Channel (P-CH), the econdary ynchronzaton Channel (-CH), and the Common Plot Channel (CPICH) [2]. Fgure 2 depcts the slot and frame formats of these channels. Each frame of chps (0 ms) s dvded nto 5 slots, of 2560 chps (0.67 ms). The CPICH s scrambled by the prmary downlnk scramblng code of the cell. There are 0 plot symbols wthn each tme slot, each spread by 256 chps. Unlke CPICH, the P-CH and -CH are not scrambled by the prmary downlnk scramblng code [3]. As shown n Fgure 2, the P-CH sequence s transmtted once n every slot, and thus can be used for detectng the slot boundary. All cells use the same P-CH sequence, and only one P-CH matched flter s needed to detect the slot boundares. Ths code structure leads to a three stage ppelned approach where the prmary synchronzaton stage performs a correlaton off the P-CH and results n the dentfcaton of the correct slot boundary. Followng the prmary stage, the second stage obtans the frame boundary along wth the code group number. Each code group specfes a set of 8 possble prmary scramblng codes. Fnally the thrd and fnal stage of synchronzaton s performed usng the RAKE correlator banks and s used to decde on the exact code beng used wthn the code group chosen by the second stage sync. Ths procedure s depcted n Fgure 3. Fgure. Average watng tme for sngle and dual antenna /04/$ IEEE 3900

2 one slot 256 chps (one plot symbol) P-CH -CH CPICH one frame (0ms) Fgure 2 WCDMA synchronzaton channel structure tart Frame tage tage tage 2 tage tage 2 tage 3 Rejects tage tage 2 tage 3 Rejects Fgure 3 Ppelned operaton tage tage 2 tage 3 Accepts III. PRIMARY YNCHRONIZATION A. ystem Requrements The goal of the prmary synchronzaton stage s to detect the slot boundares. Ths s acheved by detectng the 256 chps P-CH sequence transmtted at the begnnng of every downlnk slot. Ths sequence s common to all basestatons. Due to the low operatng NR, the matched flter outputs have to be averaged over several slots to generate a relable result. Furthermore, durng the ntal cell search, the frequency offset at the recever can be as large as 20 KHz, whch results n a sgnfcant loss f the correlaton s performed coherently. To compensate for the frequency offset and acheve robustness, non-coherent combnng of shorter correlaton length s typcally performed. For example, a 256 chp correlaton s dvded nto shorter correlatons (e.g. four 64 chp correlatons) and the results are combned. B. P-CH Code tructure An nterestng characterstc of the 256 chps that form the P-CH channel s that they are the Kronecker product of the followng two codes: = [ ] 2 = [ ] Ths observaton leads to the proposed hardware archtecture shown n Fgure 4 where a 6-tap matched flter s matched to whle a memory block of sze 256 s used to perform () the flterng aganst the 2 sequence. In ths approach, only a 6-tap shft regster s used, therefore reducng the power consumed for clockng the flp flop regsters and the area used for mplementng t. Furthermore, for every output of the frst stage matched flter, only 6 memory locatons (partal correlaton results) have to be updated, makng t feasble to use a sngle memory block (to save area) and a clockng rate of 6 tmes the chp rate (~64MHz) to update the memory locatons properly. Ths structure leads to a 60 % reducton n power consumpton compared to a drect 256 tap matched flter where each flp-flop s clocked. Ths s an mportant consderaton snce the unt s runnng at the samplng frequency of the analog to dgtal converter whch typcally runs at 4 tmes the chp rate (chp rate s 3.84 Mcps). 6-tap matched to word Memory Block Fgure 4 tage one cell searcher Matched Flterng: To further reduce the power consumed n the matched flter, we used a dfferental archtecture that reduces the number of multplcatons and addtons. Ths s acheved by mplementng the sequence as hardwred. The dfferental mplementaton comes from the followng smplfcaton. Assume that x(n) s the nput sgnal to the matched flter and y(n) s the output of the matched flter. The flter s output at tmes n and n+ can be wrtten as: y ( n) = 5 x( n ) ( ) = 0 (2) 5 y ( n + ) = x( n + ) ( ) = 0 Now a recursve equaton for the flter s output can be derved as follows: /04/$ IEEE 390

3 y( n+ ) = y( n) n+ )[ (0) 0] n)[ () (0)] + (3) n 4)[ (5) (4)] n 5)[0 (5)] The matched flter output can be derved recursvely from the prevous computed output by performng the correlaton aganst a new sequence defned as: dff = [ 0] [0 ] (4) Ths new sequence bascally contans the dfference between all consecutve elements of the orgnal sequence. About half of the elements n the new sequence are zero, therefore reducng the number of multplcatonsaddtons n mplementng the orgnal matched flter. Correlaton Bank: The man motvaton to have a correlaton bank usng a memory block nstead of regular matched flter s ts area effcent archtecture, and the fact that the memory block can be used to temporarly store the partal results of the correlaton results. The RAM or Regster Fle (RF) mplementaton of memory locatons s much more area effcent than regular flp-flop based storage. Ths s the case snce the number of memory locatons for prmary and secondary synchronzaton s relatvely large ( words of 2 to 24 bts). The other advantage of the two-stage matched flter/correlaton bank s ts lower clockng rate (by a factor of 6) compared to other alternatves. Only 6 memory locatons n the two-stage archtecture are updated (clocked) for every receved chp sample. Dversty Combnng To beneft from dversty a non-coherent sum of contrbutons from both antennas s performed and the results are transferred to a supervsng mcro-controller that decdes on vald peaks. Fgure 5 llustrates the probablty of error n detecton (Pe) of a dual antenna system versus a sngle antenna system for dfferent Doppler frequences n a flat fadng envronment. Fgure 5 Performance n a flat fadng channel IV. ECOND TAGE YNCHRONIZATION Followng the prmary synchronzaton, the slot boundary s dentfed, the second stage utlzes ths nformaton to lock onto the frame boundary as well as dentfy the code group used. Ths s acheved by usng two synchronzaton channels, namely the P-CH and the -CH. As shown n Fgure the -CH conssts of a symbol that s transmtted n the frst 256 chps of the slot. There are 5 dfferent slots n a frame. The structure of the econdary ynchronzaton Channel (-CH) s as follows: -CH 256 chps lot #0 lot # c,0 c, 2560 chps 0 ms CH rado frame The above sequence gets repeated n every frame There are a total of 64 possble sequences C, k c,4 lot #4 Each s a 256 chps sequence, taken from a 6-ary codebook. The specfc structure of the codewords s gven n [2]. C, k The codewords are assgned for dfferent slots (slot #0 to slot #4) for dfferent code groups (group #0 to group #63) based on a Reed-olomon (R) code. The structure of the codebook s such that a non-zero cyclc shft less than 5 of any of the 64 code sequences s never equvalent to some cyclc shft of any other of the 64 sequences, or the cyclc shft of the codeword tself. In the second stage synchronzaton, one should recover from the receved samples on -CH, whch code sequence has been sent and what the correspondng offset s,.e., the frame start. Ths nformaton wll be passed onto the thrd stage synchronzaton to obtan the exact scramblng code from the common plot channel (CPICH). The mplementaton of the second stage synchronzaton can be consdered n two steps: - Computaton of the requred correlaton values 2- R Decodng,.e. fndng the code sequence (group number) and the correspondng offset (frame boundary). There are multple mplementatons that could be consdered for the second stage. - A straght forward approach would be to perform decodng on a symbol by symbol bass followed by a hard decson on that symbol. At the end of the frame 5 decsons are avalable and a code group selecton could be performed. Ths approach s very smple to mplement but results n extremely poor performance due to the hard decson. 2- A second approach s to perform maxmum lkelhood decson. In ths case a correlaton s performed on a symbol by symbol bass however for each slot. Usng 6 correlaton values per slot a table s constructed consstng of a (64 code_sequence x 5 offset) matrx by nsertng the value of the correlaton wth the codeword /04/$ IEEE 3902

4 number K n every (,j) locaton of the matrx f nd( C, j ) = K. (=0,,63 and j=0,,4). At the end of the frame the row and column that have the maxmum value s the requred. The total number of computatons s: (6 correlatons + 64 x 5 addtons)/slot x 5 slots. Whle there are a total number of 960 x 5 addtons, the advantage of ths scheme s that these addtons are dstrbuted n the whole frame. The major dsadvantage, however, s the memory requrement, snce a 64 x 5 matrx should be saved and therefore 960 memory words are requred. 3- The fnal and novel approach to ths problem results n a compact hghly effcent archtecture by rearrangng the maxmum lkelhood calculaton. A correlaton s performed on a symbol by symbol bass aganst all possble 6 values. Thus on a slot by slot bass 6 correlatons values are computed. Ths s repeated for each slot to generate a 5x6 matrx as follows,0 2,0 6,0, 2, 6,,4 2,4 6,4 j where, s the value of the correlaton between the receved samples on the j-th slot (j=0,,4) and the codeword wth ndex (=,,6). The dea s to obtan the correlatons wth all possble sequences over a frame wth all possble offsets and pck the maxmum correlaton. Usng the codebook table, the correlaton correspondng to group number (=0,,63) and offset j (j=0,,4) s obtaned as: Corr (, j ) = 4 nd m = 0, ( j+ m) mod5, ( j + m ) mod 5 ( C Recall that nd( C ) s taken from the codebook table and s a number from to 6. Ths scheme obtans the same metrcs as scheme II, and therefore fnds the ML soluton and performs better than a hard-decson scheme. The number of computatons: 6 correlatons/slot x 5 slots x 5 addtons The major advantage of ths scheme over cheme II s that only 6 x 5 = 240 memory words are requred. Note that there s no need to keep all Corr (, j) s anymore, as we are only nterested n the maxmum value. In other words, every calculated Corr (, j) s compared aganst the prevous one and the bgger one s pcked. Moreover, the same number of addtons (960 x 5) s requred n cheme III as n cheme II. Correlator Crcut Desgn When desgnng the -CH correlaton block three man ponts were consdered. ), m (5) (6) A relatvely hgh frequency offset of +/- 20 KHz mght stll affect the data snce fne frequency acquston has not yet been ntated. The dual antenna structure must be utlzed to mprove performance. An nverse Hadamard transformaton should be used to mplement the fnal R decodng due to ts hardware effcent fast mplementaton smlar to the FFT. To address these ponts, the correlator was splt nto two parallel channels, one correlatng off the P-CH channel whle the second correlates of the -CH. nce the P-CH s always transmtted smultaneously to the -CH, the P-CH can be used as a phase reference for the -CH. A non-coherent processng s used where the nputs to the nverse Hadamard transform are corrected by a channel estmate computed usng 64 chps from the P-CH. The nputs from both antennas are then combned together usng the channel estmate n a manner smlar to maxmal rato combnng. That s, for slot the 6 nputs to the nverse Hadamard transform are gven by: * s p s = Real y, n y k, n = 0,,5, j = 0,,4 (7) n= k = 4 4 Where s the symbol ndex, n s the antenna ndex, y p s the correlaton result from the P-CH channel and y s s the correlaton result for the -CH channel. Fgure 7 llustrates the fnal block desgn. Fgure 6 llustrates the mpact of MRC on the probablty of error n detecton (Pe). One sample per chp was used to calculate correlaton values. Three cases are consdered. Offset corresponds to the optmum samplng pont. Offset 2 s the sample next to the optmum samplng pont wth 4 tmes oversamplng rato, whle offset 3 s the sample on the boundary between two consecutve chps. We can observe that n all cases MRC show an mprovement n performance. V. THIRD TAGE YNCHRONIZATION The second synchronzaton stage dentfed the frame tmng and narrows down the set of possble codes to 8. The purpose of the thrd stage s to determne whch of the 8 possble codes s beng used. The output of ths stage also provdes a fnal confdence check of the overall synchronzaton. Eght correlators are used to check the 8 possble codes n parallel. Each correlator has an assocated generator, programmed to generate one of the codes beng tested. The correlators process the common plot channel (CPICH) and accumulate the magntudes of N-chp correlatons over the duraton of a frame. Just lke the prevous two stages, the thrd stage must operate wth a frequency offset of up to 20kHz. Fortunately, the correlators are hghly programmable and N can be set to any value. The outputs for each correlator are then accumulated non-coherently L tmes. A majorty votng scheme s mplemented after every L*N chps. The /04/$ IEEE 3903

5 counter correspondng to the correlator wth the largest accumulated value s ncremented. Ths procedure s repeated for the duraton of a frame and results n P=38400/(L*N) votes. After a frame s complete, the resultant 8-element vector s passed to the up. The ndex of the largest value n the vector dentfes the most lkely code, whle the relatve magntudes of the values ndcate the confdence n the result. Ths confguraton s shown n Fgure 8. Fgure 8. Block dagram for the 3 rd stage (tmes n chps) earcher Fgure 6 MRC mpact on probablty of error RAM RAM2 AB RAM Prmary ynch Memores 8x 8x x Adjusted amplng Offset from tage x r k, r k,2 lot Offset from tage Dual Antenna PC Correlator Dual Antenna C Correlator -PC -C y s, y s,2 y p,2 y p, Intal Cell earch Inverse Hadamard Transform h h 6 Accumulate over 5 slots and select maxmum lkelhood Canddate Code Group and Frame Boundary Fgure 7 Dual Antenna econdary ynchronzaton tucture VI. AIC Implementaton To verfy the functonalty of the desgn an AIC ncorporatng the cell searcher descrbed n ths paper as well as a RAKE recever core and front end dgtal sgnal processng (flterng, tmng and frequency synchronzaton) was mplemented n a 0.8 µm CMO technology. The total area of the chp s 4 mm 2 wth a total of 90 Kgates. The synchronzaton block takes up mm 2 area and uses under 28k standard cells. The total power consumpton of the chp wth all resources runnng s 8 mw. The de photo of the fabrcated AIC showng the locaton of the cell searcher s shown n Fgure 9. Fgure 9 RAKE recever AIC VII. CONCLUION A novel and robust dversty processng synchronzaton engne for 3G WCDMA has been presented. The archtecture utlzes statstcally ndependent multpath receved from two antennas to accelerate the average cell search tme and ncrease the probablty of a successful search. ystem and crcut technques were employed to mnmze the complexty of the fnal system. The archtecture has been successfully tested and proven on slcon n a 0.8 µm CMO technology. The entre synchronzaton block takes up about mm 2 area and uses under 28k standard cells. The peak power consumpton wth all three stages runnng was measured to be 20mW whle the average over a full frame s 2mW. REFERENCE [] B. Razav, RF CMO transcevers for cellular telephony, IEEE Communcatons Magazne, vol.4, no.8, pp.44-9, Aug [2] 3 rd Generaton Partnershp Project, Physcal channels and mappng of transport channels onto physcal channels (FDD), 3GPP Tech. pec., T 25.2, V3.0.0, Oct [3] emens and Texas Instruments, Generalzed herarchcal Golay sequence for PC wth low complexty correlaton usng pruned effcent Golay correlators, 3GPP Tech. Doc., Tech. Doc. R-99554, Cheju, Korea, June 999. [4] Y. E. Wang and T. Ottosson, Cell search n W-CDMA, IEEE Journal on elected Areas n Communcatons, vol. 8. No. 8, pp , August /04/$ IEEE 3904