Crossover Distortion FETS Spec sheets Configurations Applications

Transcription

1 Crossoer Distortion FETS Spec sheets Configurations Applications Acknowledgements: Neamen, Donald: Microelectronics Circuit Analysis and Design, 3 rd Edition Spring 2017 Lecture 6 1

2 Three Stage Amplifer Crossoer Distortion Hole Feedback Spring 2017 Lecture 5 2

3 Crossoer Distortion Analysis Spring 2017 Lecture 5 3

4 Crossoer Distortion Analysis e g in 570 e 1 10 out The distortion 0.6 in each direction or 1.2 total resulting in a hole that is: out out in in 1 10 out n n in n *1.2 ~ 0.02 Increasing open loop gain will reduce the crossoer distortion Spring 2017 Lecture 5 4

5 BJT FET Bipolar Junction Transistor Three terminal deice Collector current controlled by base current ib= f(vbe) Think as current amplifier NPN and PNP Field Effect Transistor Three terminal deice Channel conduction controlled by electric field No forward biased junction i.e. no current JFETs, MOSFETs Depletion mode, enhancement mode Spring 2017 Lecture 6 5

6 BJT JFETS MOSFETS BJT JFET MOSFET Circa Gm/I (signal gain) Best Better Good Isolation PN Junction Metal Oxide ESD Low Moderate Very sensitie Control Current Voltage Voltage Power YES No Yes Spring 2017 Lecture 6 6

7 Voltage Noise * * Horowitz & Hill, Art of Electronics 3 rd Edition p Spring 2017 Lecture 6 7

8 FET Family Tree FET JFET depletion MOSFET n-channel p-channel depletion enhancement Vgs(off) gate source cutoff or n-channel n-channel p-channel Vp pinch-off oltage Vgs(th) gate source threshold oltage Spring 2017 Lecture 6 8

9 Transistor Polarity Mapping* + n-channel depletion n-channel JFET n-channel enhancment npn bjt - + p-channel enhancment pnp bjt p-channel JFT - * Horwitz & Hill, the Art of Electronics, 3 rd Edition Spring 2017 Lecture 6 9

10 MOSFETS MOSFET &JFETS Much more finicky difficult process (to make) than JFET s. Good news: Extremely high input impedance. Zero input current. Bad news: Easily blown up by ESD on the gate. Add protection circuit and input bias current becomes at best comparable to JFET s. Good news: Essentially infinitely fast. If you change the gate oltage, the deice will respond instantaneously! Essentially always in static equilibrium. Bad news: It can be really hard to change the gate oltage quickly! (especially power deices BIG BIG capacitor) Much better power deices than JFET s. (There were briefly power JFET s as output deices in audio amps. Too many blew up.) And you can t make digital VLSI out of JFET s Spring 2017 Lecture 6 10

11 MOSFET s JFETS JFET s Very simple manufacturing process like BJT s. Much cheaper than (discrete) MOSFET s. Quieter than MOSFET s. Low input bias current like back biased diode. As low as 10pA. But note this doubles eery 6 deg C! At high temps a JFET op amp can hae more input current than some bipolar op amps! Used in microphones, hearing aids and other high impedance sources (electret microphones hae ery high output impedance) because of low noise and ruggedness compared to MOSFET s. Fast. Used on many high speed scope probes. Was major adance in bias current and speed oer bipolar input op amps. See data sheets of (JFET input) LF356 series and compare to then bipolars. Downside is input capacitance can t be as low as some BJT s. Wide spread in threshold oltage and zero Vgs current. Sometimes requires sorting and selecting for a gien circuit Spring 2017 Lecture 6 11

12 MOSFET Symbols S S Bulk body terminal IRFD9110 2N7000 N-Channel MOSFET N-channel P-channel Spring 2017 Lecture 6 12

13 JFET: Junction FET Symbol G D S G S D G D S G S D N channel JFET P channel JFET Spring

14 Simple Model of MOSFET D G + V gs - S MOSFET made VSLI (microprocessors and memories) possible. ~0 gate current G D S G D S 2N7000 R on 7.5 IRFD9110 Ron 1.2 Very high input resistance Voltage controlled deice ~25 V max operating off state V gs < V t on state V gs V t Spring

15 MOSFETS: Gain & non linearity source gate Polysilicon wire Heaily doped (n-type or p-type) diffusions W Inter-layer SiO 2 insulation Very thin (<20Å) high-quality SiO 2 insulating layer isolates gate from channel region. L drain I DS W/L Channel region: electric field from charges on gate locally inerts type of substrate to create a conducting channel between source and drain. bulk Doped (p-type or n-type) silicon substrate MOSFETs (metal-oxide-semiconductor field-effect transistors) are four-terminal oltage-controlled switches. Current flows between the diffusion terminals if the oltage on the gate terminal is large enough to create a conducting channel, otherwise the mosfet is off and the diffusion terminals are not connected Chris Terman

16 FETs as switches The four terminals of a Field Effect Transistor (gate, source, drain and bulk) connect to conductors that generate a complicated set of electric fields in the channel region which depend on the relatie oltages of each terminal. gate source drain E h N+ N+ INVERSION: A sufficiently strong ertical field will attract enough electrons to the surface to create a conducting n-type channel between the source and drain. The gate oltage when the channel first forms is called the threshold oltage -- the mosfet switch goes from off to on. p bulk E inersion happens here CONDUCTION: If a channel exists, a horizontal field will cause a drift current from the drain to the source Chris Terman

17 Excellent graphic showing four states of MOSFET for different Vgs and Vds Spring 2017 Lecture 6 17

18 What s the difference between the drain and the source? MOSFET s can be symmetrical and drain and source interchangeable. Especially inside IC s. But discrete deices (with few exceptions) hae input protection networks on the gate to protect against ESD. Also, the substrate must connect somewhere. Once the input protection clamping and the substrate are connected to a terminal, that must be the source. N-Channel MPSFET Spring 2017 Lecture 6 18

19 Classic ideal MOSFET characteristics Flat cures in saturation region assume long channel MOSFET BJT Spring 2017 Lecture 6 19

20 ideal MOSFET cures continued Triode mode, or linear mode, or ohmic region. Saturation or actie mode. K n = transconductance parameter As the channel length becomes short, these equations become inaccurate. At the channel ends, source and drain regions causing fringing effects and Distort the electric fields from the ideal case used to derie aboe eq s. For analog design, long-channel MOSFET s can offer extremely high output Impedance, making excellent stiff current sources. Minimum geometry transistors used in digital VLSI do not hae such flat cures Spring 2017 Lecture 6 20

21 Channel Length Modulation: Early Voltage Spring 2017 Lecture 6 21

22 JFET p-channel Spring 2017 Lecture 6 22

23 6.101 Spring 2017 Lecture 6 23

24 2N7000 n channel Spring 2017 Lecture 6 24

25 2N7000 Wide process spread Vgs(th) : Spring 2017 Lecture 6 25

26 2N7000 C iss C GS C oss C DS C irs C GD Estimating MOSFET Parameters from the Data Sheet Spring 2017 Lecture 6 26

27 MOSFET Configurations Common drain Common source Common gate Spring 2017 Lecture 6 27

28 Basic FET Circuits Analog switch oltage controlled Digital logic microprocessor, VLSI, ASIC Power switching preferred oer BJT Variable resistors use linear region of drain cure Current sources General replacement for bjt (in some cases) Spring 2017 Lecture 6 28

29 Simple NMOS Small Signal Equialent Circuit Spring 2017 Lecture ] [ ] ) ( [ ) ( 2 ) ( 2 DQ TN GSQ n o i o DQ n TN GSQ n m gs d i m I V V K r r I K V V K g i g DS D GS D

30 Common Source Configuration DC analysis: Coupling capacitor is assumed to be open. AC analysis: Coupling capacitor is assumed to be a short. DC oltage supply is set to zero olts.

31 Small Signal Equialent Circuit A V o V i g m ( r o R D )( R i Ri R Si )

32 Common Source Neamen Ch 4.3 More generalized common source with source degeneration and equations: Usage: oltage amplifier, transconductance amplifier Spring 2017 Lecture 6 32

33 Common Drain Source Follower Neamen Ch 4.4 Usage: oltage buffer Spring 2017 Lecture 6 33

34 NMOS Source Follower or Common Drain Amplifier

35 Small Signal Equialent Circuit for Source Follower A ( R R S o i 1 RS ro i RSi m g R r )

36 Common Gate Neamen Ch 4.5 Usage: High frequency amplifier Spring 2017 Lecture 6 36

37 Comparison of 3 Basic Amplifiers Configuration Voltage Gain Common Source A > 1 Source Follower A 1 Current Gain Input Resistance Output Resistance Moderate to *R TH high *R TH Low Common Gate A > 1 A i 1 Low Moderate to high * Determined by biasing resistors Spring 2017 Lecture 6 37

38 Cascode Configurations All hae the same purpose to decouple the input terminal (of the bottom deice) from capacitie feedback from the output by taking the output from a second deice. Bottom deice: Current gain (no appreciable oltage gain) Top deice: Voltage gain (no current gain) Combines common-emitter/source/cathode with common-base/gate/grid. Result is like a single common-emitter/source/cathode deice with drastically reduced Miller capacitance from the output to the input BJT JFET MOSFET Vacuum tube triode Spring 2017 Lecture 6 38

39 Single deices with cascode like construction Tetrode (tet for 4 terminal) acuum tube adds a fourth grid called a screen to shield the grid and cathode from the anode Similar MOSFET deice incorporates a second gate. Useful for RF circuits Spring 2017 Lecture 6 39

40 JFET Amplifier Configurations Common Source Amplifier Common Drain Amplifier [Source Follower] Common Gate Amplifier * For polarized [electrolytic] input coupling capacitor, the "+" should be oriented towards the most positie DC oltage. For example, if there is -2V on the gate, and -8V associated with Vin, then the capacitor orientation should be reersed as shown. The input coupling cap for the common gate configuration will most often be a polarized electrolytic, since the impedance at the Source of the JFET is only 1/g m in parallel with R S Spring 2017 Lecture 6 40

41 Common Source JFET (bypassed source resistor) Spring 2017 Lecture 6 41 L m S m L m S m gs L gs m S gs m gs L gs m in out R g A or R g R g A R g R g R g R g A 1 1

42 Common Drain Amplifier (Source Follower) Spring 2017 Lecture 6 42 S m S m S m gs S gs m S gs m gs S gs m in out R g R g A R g R g R g R g A 1 ; 1

43 Common Gate Amplifier Spring 2017 Lecture 6 43 L m i S i i m L m S i i m gs L gs m in out R g A R R R R g R g R R R g R g then if A, ; 1 1 0

44 Output Resistance Source Follower R i g + V gs _ I test s + V test d g m V gs Remoe R S and replace it with a test AC oltage generator Short the input signal V i and replace it with its source resistance R i. Sole for I test, which is a consequence of applying the test generator V test, and for V test in terms of the hybrid-π parameters. _ To correctly calculate the alue of a bypass capacitor for R s, use the parallel combination of r o and R S. r o V I test test V g m gs V gs 1 g m Spring 2017 Lecture 6 44

45 Low Frequency Hybrid π Model Spring 2017 Lecture 3 45

46 OK, now what can we do with these things? signal in: -10 to +10 MOSFET analog switch Spring 2017 Lecture 6 46

47 OK, now what can we do with these things? This schematic from the now obsolete Intersil 7662 datasheet shows how a flying capacitor generates a negatie oltage from a positie oltage. Slightly different connections can double a oltage instead of inerting it Spring 2017 Lecture 6 47

48 JFET follower A JFET follower using matched (dual) JFET s. The bottom JFET automatically generates just the right amount of current to bias the top one so Vin is approximately equal to Vout. Horowitz Hill, 3 rd Edition p Spring 2017 Lecture 6 48

49 JFET ariable attenuator r The Dolby B noise reduction circuit used this circuit as a Variable attenuator. By adding ½ the drain oltage back to the gate oltage linearizes the JFET resistance. V ) ( V DS GS V th DS 6k Control oltage (negatie) P4392 From An introduction to electronics, Cambridge Uni Press Spring 2017 Lecture 6 49

50 n Channel JFET Current Source 2N Spring 2017 Lecture 6 50

51 P Channel JFET Current Source Spring 2017 Lecture 6 51

52 Neat Circuit Ideas From Make a classic phase shift oscillator (3 stages of 60 deg phase shift each any three digital logic inerters will usually do) so you can WATCH the oscillation run around the loop! Works with any odd number of stages. Question : Is this guaranteed to start up? Why? And what if you had a large (odd) number of stages can you start a skinny pulse going around the loop? Will it stay skinny or widen and turn into 50-50% duty cycle? 2N Spring 2017 Lecture 6 52

53 More from same web site note single ended drie implies this motor has commutator brushes. I had wrongly assumed these drills used brushless motors Spring 2017 Lecture 6 53

54 Important basic power configuration The H bridge Note how the high side MOSFET s are drien by leel shift. Four drie signals required. Note the trade off in switching speed ersus static power dissipation in leel shifter. The 10k resistor will not turn off the IRF9Z30 ery fast. But motor dries don t operate at ery high frequencies Spring 2017 Lecture 6 54

55 Continuing from this web site This is a great summary of MOSFET failure modes AKA (Also Known As) What NOT to do with a MOSFET. WHY MOSFETs FAIL There are quite a few possible causes for deice failures, here are a few of the most important reasons: Oer-oltage: MOSFETs hae ery little tolerance to oer-oltage. Damage to deices may result een if the oltage rating is exceeded for as little as a few nanoseconds. MOSFET deices should be rated conseratiely for the anticipated oltage leels and careful attention should be paid to suppressing any oltage spikes or ringing. Prolonged current oerload: High aerage current causes considerable thermal dissipation in MOSFET deices een though the on-resistance is relatiely low. If the current is ery high and heatsinking is poor, the deice can be destroyed by excessie temperature rise. MOSFET deices can be paralleled directly to share high load currents. Transient current oerload:massie current oerload, een for short duration, can cause progressie damage to the deice with little noticeable temperature rise prior to failure Spring 2017 Lecture 6 55

56 MOSFET failure modes continued Shoot-through - cross conduction: If the control signals to two opposing MOSFETs oerlap, a situation can occur where both MOSFETs are switched on together. This effectiely short-circuits the supply and is known as a shootthrough condition. If this occurs, the supply decoupling capacitor is discharged rapidly through both deices eery time a switching transition occurs. This results in ery short but incredibly intense current pulses through both switching deices. Allow a dead time between switching transitions, during which neither MOSFET is turned on. This allows time for one deice to turn off before the opposite deice is turned on. No free-wheel current path: When switching current through any inductie load (such as a Tesla Coil) a back EMF is produced when the current is turned off. It is essential to proide a path for this current to free-wheel in the time when the switching deice is not conducting the load current. This current is usually directed through a free-wheel diode connected antiparallel with the switching deice. When a MOSFET is employed as the switching deice, the designer gets the free-wheel diode "for free" in the form of the MOSFETs intrinsic body diode. This soles one problem, but creates a whole new one Spring 2017 Lecture 6 56

57 MOSFET failure modes continued Excessie gate drie: If the MOSFET gate is drien with too high a oltage, then the gate oxide insulation can be punctured rendering the deice useless. Gate-source oltages in excess of +/- 15 olts are likely to cause damage to the gate insulation and lead to failure. Care should be taken to ensure that the gate drie signal is free from any narrow oltage spikes that could exceed the maximum allowable gate oltage. *** WAIT A MINUTE! This author fails to point out that practically all discrete MOSFET s hae a oltage clamp on the input. The actual failure mechanism is usually you melt the clamping zener, and the puddle of molten silicon forms a short. The MOSFET may be fine, but the gate is now shorted to the source, which makes it kind of hard to use Spring 2017 Lecture 6 57

58 MOSFET failure modes continued Insufficient gate drie - incomplete turn on: MOSFET deices are only capable of switching large amounts of power because they are designed to dissipate minimal power when they are turned on. It is the responsibility of the designer to ensure that the MOSFET deice is turned hard on to minimise dissipation during conduction. If the deice is not fully turned on then the deice will hae a high resistance during conduction and will dissipate considerable power as heat. A gate oltage of between 10 and 15 olts ensures full turn-on with most MOSFET deices. ***NOTE: The reference to gate oltages of between 10 and 15 olts applies to older or higher oltage power deices (like 20 to 200V). The newer power parts hae long been based on the latest digital process: i.e., they re designed for 5V. Newer power MOSFET s hae guaranteed on resistance at lower Vgs oltages consistent with use in 3.3V logic inputs, and hae Vds absolute maximum ratings of 6V or 7V, and similar abs max Vgs ratings. Modern logic requires lots of power conersion deices operating at these low oltages Spring 2017 Lecture 6 58

59 For further reading and possible inspiration for your projects, read Jim Williams app notes! You gotta loe a guy who titles an app note (#25) : The aboe title is not happenstance and was arried at after considerable deliberation Mysterious modes, sudden, seemingly inexplicable failures, peculiar regulation characteristics and just plain explosions are common occurrences. Diodes conduct the wrong way. Things get hot that shouldn t. Capacitors act like resistors, fuses don t blow and transistors do. The output is at ground, and the ground terminal shows olts of noise. Added to this poisonous brew is the regulator s feedback loop, sampled in nature and replete with uncertain phase shifts. Eerything, of course, aries with line and load conditions and the time of day, or so it seems. In the face of such menace, what are Eeryman and the poets to do? Spring 2017 Lecture 6 59

60 6.101 Spring 2017 Lecture 6 60