Complementary Pair Enhancement Mode Field Effect Transistor
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1 Features: Low OnResistance Low Gate Threshold oltage Low Input Capacitance Fast Switching Speed Low Input / Output Leakage Complementary Pair SOT363 Maximum Ratings: Total Device Ratings at 25 C unless otherwise specified. Parameter Symbol alue Units Power Dissipation PD 200 mw Thermal resistance, junctiontoambient RθJA 625 C/W Junction and storage temperature TJ, Tstg 55 to +150 C NChannel Q1, 2N7002 Section Drainsource voltage DSS 60 Draingate voltage( RGS 1MΩ) DGR 60 Gate source voltage continuous Pulsed GSS ±20 ±40 Drain current continuous Continuous at 100 C Pulsed ID ma NChannel Q2, BSS84 Section Drainsource voltage DSS 50 Draingate voltage (RGS 1MΩ) DGR 50 Gate Source voltage continuous GSS ±20 Drain current continuous ID 130 ma Page <1> 28/02/13 1.0
2 Electrical Characteristics: Ratings at 25 C unless otherwise specified Q1, 2N7002 Section Parameter Symbol Test conditions Min. Typ. Max. Unit Drainsource breakdown voltage (BR)DSS GS=0, ID=10μA Gate threshold voltage GS(th) DS=GS, ID=250μA Gatebody leakage Forward Reverse IGSS DS=0, GS=20 DS=0, GS= na Zero gate voltage drain current IDSS DS=60, GS=0 1 DS=60, GS=0, Tj=125 C 500 μa Onstate drain current ID(On) GS=10, DS= A Drainsource onvoltage DS(ON) GS=10, ID=500mA GS=5, ID=50mA Forward transconductance gfs DS=10, ID=200mA 80 ms Static drainsource onresistance RDS(ON) GS=5, ID=50mA GS=10, ID=500mA, Tj=125 C Ω Input capacitance CISS Output capacitance COSS DS=25, GS=0, f=1mhz pf Reverse transfer capacitance CRSS 2 5 Turnon delay time td(on) DD=30, ID= 0.2A, 7 RL = 150Ω, GS=10, TurnOff Delay Time td(off) RGEN= 25Ω ns Page <2> 28/02/13 1.0
3 Electrical Characteristics: Ratings at 25 C unless otherwise specified Q2, BSS84 Section Parameter Symbol Test Conditions Min. Typ. Max. Unit Drainsource breakdown voltage (BR)DSS GS=0, ID=250μA 50 Gate threshold voltage GS(th) DS=GS, ID=1mA Gatebody leakage Forward Reverse IGSS DS=0, GS=20 DS=0, GS= na DS=50, GS=0, Tj=25 C 15 Zero Gate oltage Drain Current IDSS DS=50, GS=0, Tj=125 C 60 na DS=25, GS=0, Tj=25 C 100 Forward transconductance gfs DS=25, ID=0.1A 0.05 S Static drainsource onresistance RDS(ON) GS=5, ID=0.1A 10 Ω Onstate drain current ID(ON) GS=10, DS= A Input capacitance CISS 45 Output capacitance COSS DS=25, GS=0, f=1mhz 25 pf Reverse transfer capacitance CRSS 12 Turnon delay time td(on) DD =30, ID=0.27A, 10 Turnoff delay time td(off) GS=10, RGEN= 50Ω 18 ns Page <3> 28/02/13 1.0
4 Typical Characteristics: Ta = 25 C unless otherwise specified Page <4> 28/02/13 1.0
5 Page <5> 28/02/13 1.0
6 Page <6> 28/02/13 1.0
7 Package Outline: Plastic surface mounted package SOT363 Dim. Min. Max. A B C D 0.95 Typ Typ. E G H J 0.1 Typ. K Soldering Footprint: Dimensions : Millimetres Package Information: Device Package Shipping BSS8402DW7F SOT363 3,000 / Tape & Reel Dimensions : Millimetres Part Number Table Description Complementary Pair Enhancement Part Number BSS8402DW7F Important Notice : This data sheet and its contents (the Information ) belong to the members of the Premier Farnell group of companies (the Group ) or are licensed to it. No licence is granted for the use of it other than for information purposes in connection with the products to which it relates. No licence of any intellectual property rights is granted. The Information is subject to change without notice and replaces all data sheets previously supplied. The Information supplied is believed to be accurate but the Group assumes no responsibility for its accuracy or completeness, any error in or omission from it or for any use made of it. Users of this data sheet should check for themselves the Information and the suitability of the products for their purpose and not make any assumptions based on information included or omitted. Liability for loss or damage resulting from any reliance on the Information or use of it (including liability resulting from negligence or where the Group was aware of the possibility of such loss or damage arising) is excluded. This will not operate to limit or restrict the Group s liability for death or personal injury resulting from its negligence. Multicomp is the registered trademark of the Group. Premier Farnell plc Page <7> 28/02/13 1.0
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DESCRIPTION The is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to
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DESCRIPTION The SPP3415 is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored
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Description The is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored to
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DESCRIPTION The SPP3401D is the P-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored
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DESCRIPTION The SPN9910 is the N-Channel logic enhancement mode power field effect transistors are produced using high cell density, DMOS trench technology. This high density process is especially tailored
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