Power optimal gate current profiles for the slew rate control of Smart Power ICs

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1 Preprints of the 19th Worl Congress The International Feeration of Automatic Control Cape Town, South Africa. August 24-29, 214 Power optimal gate current profiles for the slew rate control of Smart Power ICs M. Blank T. Glück A. Kugi H-P. Kreuter Automation an Control Insitute, Vienna University of Technology, Gusshausstrasse 27-29, 14 Vienna, Austria {blank, glueck, Infineon Technologies Austria AG, Siemensstrasse 2, 95 Villach, Austria Abstract: Smart Power ICs are Power Switches with integrate control an protection functions. In orer to meet the electromagnetic compatibility requirements, the output terminal slew rate has to be limite uring the switching operation. In this context, special feeforwar gate current profiles are wiely use to control the switching slew rate. These profiles are typically etermine on the basis of a linearize mathematical moel of the Smart Power IC. However, ue to the nonlinear characteristics of the IC, these profiles may lea to a reuce switching spee an thus to higher switching losses. In this work, an optimal control problem is consiere which systematically accounts for the nonlinearities of the Power Switch, the switching losses an the limitation of the slew rate. In particular, a tailore mathematical moel of the Smart Power IC is evelope an parametrize. Base on this, the optimal control problem is formulate, numerically solve an the results are presente. Keywors: Smart Power IC; gate current profile; gate river; optimal control; slew rate control; feeforwar esign. 1. INTRODUCTION In the last ecaes, Power Switches with integrate control an protection functions have become state of the art for the switching of mile an high current loas in automotive an inustrial applications. These so-calle Smart Power ICs Murari et al., 22 typically consist of a Power Switch, e.g., a Power MOSFET or an IGBT, a river circuit to control the switching operation, an protection functions such as over temperature shutown an loa etection, see, e.g., Pribyl In state-of-theart Smart Power ICs, the control an protection functions are typically implemente in the form of analog circuits. To increase the reusability of the circuit esign an thus to reuce the evelopment costs an time to market a igital realization seems to be promising an also allows to implement new features to meet future emans. In orer to meet the electromagnetic compatibility requirements an the customer emans, the current an voltage slew rate at the output terminal of the Power Switch has to be limite, see Oswal et al The slew rate limitation results in a reuce switching spee an, consequently, in higher switching losses. In Smart Power ICs with a low on-resistance, the switching losses outweigh the total power issipation an therefore have to be minimize. In orer to minimize the switching losses, the slew rates not only have to be limite but they have to be actively controlle. To cope with this task, several, mostly analog, control strategies have been evelope, see, e.g., Lefranc an Bergogne 27; Wittig an Fuchs 212 an Lobsiger an Kolar 212. Because of the rather high harware emans, igital close-loop control strategies are not applicable an thus rather simple igital feeforwar an aaptive feeforwar strategies are employe in practice. In this context, so-calle gate current profiles are use to control the switching operation. These profiles are applie to the Power Switch by a igital controllable gate current source. Gate current profiles are either use as a constant, Schmitt et al., 28, or iteratively aapte feeforwar control, Dang et al., 211; Rose et al., 21. Due to the highly nonlinear characteristics of the Smart Power IC, a gate current profile that controls the output terminal slew rates an simultaneously guarantees optimal switching spee cannot be obtaine by a moel inversion. Therefore, linearize moels are often use to calculate such profiles. This typically results in limite slew rates but leas to a reuce switching spee an consequently to higher switching losses. In this paper, gate current profiles which control the voltage or current slew rate at the output terminal of the Power Switch with respect to optimal switching spee an therefore power optimality are presente. The gate current profiles are obtaine by solving an optimal control problem subject to the nonlinear mathematical moel of the Smart Power IC an the maximum slew rate as path constraint. The presente metho can be integrate in the harware esign process of the Smart Power ICs. Especially esign questions regaring the necessary ynamics an current limits of the gate river can be answere in a systematic way. Furthermore, the results can be use as an optimal initial guess for aaptive feeforwar concepts. The work is structure as follows: a mathematical moel of the Power Switch is presente in Section 2 an parametrize Copyright 214 IFAC 719

2 19th IFAC Worl Congress Cape Town, South Africa. August 24-29, 214 in Section 3. The optimal control problem is formulate in Section 4 an numerical results are presente in Section MATHEMATICAL MODEL The mathematical moeling is base on the simulation an circuit esign of the Smart Power IC given in the Custom IC Design: Caence Virtuoso Schematic environment. Because of the high complexity of the e- i g,1 i g,1 charge current ischarge current source source charge pump R Vcp i g V cp L L R L V bat Fig. 1. Schematic of the Smart Power IC incluing the switching loa in high-sie configuration. sign an the partly unknown sub-circuit parameters an equivalent circuit is introuce, see Fig. 1. The equivalent circuit inclues the n-channel Power MOSFET T 1, the charge an ischarge current sources, the charge pump an the ohmic-inuctive loa R L an L L. The charge pump increases the gate against the rain potential of the Power MOSFET an is moele by the voltage source V cp an the internal impeance R Vcp. Furthermore, the current sources are each moele by a current mirror, where i g,1 an are the controllable reference currents an i g,1 an are the output currents, respectively. The gate current i g = i g,1 serves as the control input for the switching operation. By applying a positive gate current i g,1 > an =, the input capacitances of the Power MOSFET are charge, the Power MOSFET is activate an the loa is switche to the battery voltage V bat. Similarly, by applying a negative gate current, > an i g,1 =, the input capacitances are ischarge, the Power MOSFET is eactivate an the loa is switche off. 2.1 Power MOSFET The turn-on an off characteristics of the Power MOS- FET are etermine by its parasitic capacitances an resistances an by the rain current which epens on the terminal voltage. In the large signal equivalent circuit shown in Fig. 2, the parasitic lea an substrate resistances are consiere by means of the gate, rain an source resistors R g, R an R s which are assume to be constant. The parasitic capacitances are summarize in the gate-source C gs, rain-source C s an gate-rain C g capacity. Since the epletion layer contributes to the parasitic capacitances, they vary with the terminal voltage an are efine as C = Q/v with the charge Q an the terminal voltage v. More precisely, C gs is the combination of the oxie an the epletion layer capacitance of the T1 i L Gate Drain Source Gate R g v g v gs C g C gs Drain R C s i s R s Source v s Fig. 2. Schematic an large signal equivalent circuit of the n-channel Power MOSFET. SI-SO2 interface an is assume to be inepenent of the terminal voltage, i.e. C gs = const., see Mohan et al. 23. Moreover, C s results from the p + n n + -ioe between the rain an source terminal, see Schröer 26, an is approximate with the capacitance of a pn-junction in the form C s v s = C s, 1 v s φ c,s nc,s, 1 where C s, enotes the rain-source capacitance at zero rain-source voltage v s =, φ c,s is the barrier potential an n c,s is the graing coefficient, cf. Allen an Holberg 22. Finally, C g is etermine by the oxie capacitance an the rain epletion layer beneath the gate oxie, see, e.g., Baliga 28. The latter exists only if the rain potential is more positive than that of the gate. When the gate is more positive, C g is ominate by the gate oxie capacitance C g = C g, = const. for v g, see Grant an Gowar Otherwise the epletion layer enlarges with v g an C g is approximately given by C g v g = C g, 1 v g b c,g ac,g for v g <, 2 with the constant parameters b c,g an a c,g. In orer to achieve continuous ifferentiability, C g v g is approximate by a polynomial of thir orer in a δ vg - neighborhoo of v g = resulting in C g,, v g > δ vg 3 C g, a i v g i, δ vg v g δ vg C g v g = i= C g, 1 v g b c,g ac,g, v g < δ vg 3 where a i, i =, 1, 2, 3 constitute constant parameters. The voltage epenency of the rain current is consiere by the rain current source i s = i s v gs, v s which is moele using the core of the so-calle EKV Enz- Krummenacher-Vittoz moel, see, e.g., Enz an Vittoz 26; Chauhan et al. 26. It escribes the rain current in the form of a single, continuous an continuously ifferentiable function i s = I s i F i R, 4a with the specific current I s, the normalize forwar [ ] 2 vp i F = ln 1 + exp 1 + λv s 4b 2V t 7191

3 19th IFAC Worl Congress Cape Town, South Africa. August 24-29, 214 an reverse current [ ] 2 vp v s i R = ln 1 + exp, 4c 2V t where V t enotes the thermal voltage, λ the channel length moulation factor an v p = v gs V th 4 n the pinch-off voltage with the threshol voltage V th an the slope factor n. The slope factor is assume to be constant an the forwar current i F is phenomenologically extene with the approximation of the channel length moulation 1 + λv s. 2.2 Discharge Current Source The ischarge current source is moele by a current mirror consisting of the transistors T 21 an T 22 with the reference current, the output current an the output terminal voltage v s,22, cf., Fig. 3. The terminal of the current source are consierably faster compare to the Power MOSFET. In orer to obtain a compact mathematical moel an by consiering at the same time the current source ynamics, a first orer lag element v s,22f T f,2 + v s,22f = v s,22 7 t is use, where T f,2 enotes the time constant an v s,22f is the elaye terminal voltage. Replacing v s,22 by v s,22f in 5 yiels, together with 6, the input/output behavior of the ischarge current source =, v s,22f. The presente moeling approach is also irectly applicable to the charge current source but will be omitte here for the sake of brevity. 2.3 Large-Signal Moel Complementing the equivalent circuit of Fig. 1 with the large signal equivalent circuits from Fig. 2 an Fig. 3 yiels the large signal moel of the Smart Power IC epicte in Fig. 4. Aitionally, the offset currents i off,1 i off,1 R Vcp V cp v s,22 i g,1 R v r, T 21 T 22 v gs,2 v s,22 i g,1 v s,12 v g Fig. 3. Large signal equivalent circuit of the ischarge current source. voltage v s,22 strongly varies uring a switching operation ue to its epenency on v gs. Therefore, T 22 operates in all regions an thus the all-region approach 4 is use to moel the output current as [ ] 2 vp,22 =I s,22 ln 1 + exp 1 + λ 22v s,22 2V t,2 [ ] 2 vp,22 v s,22 ln 1 + exp. 5a 2V t,2 Here, I s,22 enotes the specific current, V t,2 the thermal voltage, λ 22 the channel length moulation factor an v p,22 = v gs,2 V th,22 5b the pinch-off voltage with the threshol voltage V th,22 an the common gate-source voltage v gs,2. Here, the slope factor was set to 1. Furthermore, v gs,2 is etermine by solving the rain current equation of T 21. Due to the common gate-rain potential of T 21 an v gs,2 > V th,21, T 21 operates only in the saturation moe. Using the first orer MOSFET moel, see Arora 27, the common gate-source voltage in saturation moe reas as 2ig,2 v gs,2 = + V th,21, 6 K 21 with the gain factor K 21 an the threshol voltage V th,21. To obtain an exact moel of the current source ynamics, the parasitic resistances as well as the capacitances of T 21 an T 22 have to be moele too. However, because of the relatively small terminal currents, the parasitic resistances are negligible. Furthermore, the parasitic capacitances are rather small compare to those of T 1, thus, the ynamics i g,1 i off,2 i g v s,22 R g i off,2 C g C gs v gs R s L L R L i s i L C s v r,s v L v s Fig. 4. Large signal moel of the Smart Power IC. V bat an i off,2 accounting for miscellaneous measurement an control circuits are ae an are assume to be constant. By applying Kirchhoff s circuit laws together with the constitutive equations an the approximations v r, i L R an v r,s i L R s an by neglecting the gate resistance R g =, the mathematical moel of the Smart Power IC takes the form t i L = 1 V bat + v g v gs i L R s + R L + R L L t v g = C s v s i g,1 i g,1, v s,12f Cv gs, v g, v s,22f + i L + i s v g, v gs i off,2 + i g,1 i g,1, v s,12f C gs Cv gs, v g 8a 8b 7192

4 19th IFAC Worl Congress Cape Town, South Africa. August 24-29, 214 t v gs = C s v s i g,1 i g,1, v s,12f Cv gs, v g, v s,22f + C g v g i L i s v g, v gs + i off,2 Cv gs, v g, v s,22f 8c t v s,12f = 1 v g V cp R i L v s,12f T f,1 + i off,1 + i g,1 i g,1, v s,12f + i g,1 RVcp t v s,22f = 1 v gs + R s i L v s,22f T f,2 with the equivalent capacitance Cv gs, v g = C g v g + C gs C s v s 8 8e + C g v g C gs. 8f Here, C s v s an C g v g are accoring to 1 an 3, an v s = v gs v g. The rain current i s v g, v gs follows from 4 an the output currents i g,1 i g,1, v s,12f an, v s,22f are ue to 5 an PARAMETER IDENTIFICATION The parameter ientification is base on the circuit elements an the simulation results of the full circuit esign given in the Caence Custom IC Design environment an the ata sheet of the Power MOSFET: BSC2N3LS. 1 The rain current source parameters V t, I s, V th, n an λ are ientifie by means of a nonlinear least squares fitting of the transfer an output characteristics of the Power MOSFET given in the full circuit esign. 2 The parameters of the charge K 11, V th,11, V th,12, V t,1, I s,12, λ 12 an the ischarge current source K 21, V th,21, V th,22, V t,2, I s,22 an λ 22 are ientifie by a nonlinear least squares fitting of the input/output characteristics of the full circuit current sources. The time constants of the first orer lag elements T f,1 an T f,2 are parametrize by means of simulation results. 3 The ientification of the capacitance parameters C g,, C gs,, C s,, φ c,s, n c,s, b c,g an a c,g is base on the characteristics of the input, output an reverse capacitance C rss, C iss an C oss from the ata sheet. 4 The parasitic resistances R an R s, the offset currents i off,1 an i off,2, the moel parameters of the charge pump V cp an R Vcp as well as the battery voltage V bat are extracte from the full circuit esign. The ientification results are summarize in Table OPTIMAL CONTROL PROBLEM The mathematical moel 8 can be written in the form t x = fx, u, x = x, 9 with the state vector x T = [i L v g v gs v s,12f v s,22f ], the initial conition x R 5 an the control input u T = [i g,1 ]. The control objective is to fin an optimal Table 1. Moel parameters. Symbol Value Unit Symbol Value Unit R s 5 µω K µa/v 2 R 336 µω V th, V n V th, V λ 1.88 V λ V V th 2.48 V T f,1 4 I s 3.34 A I s, µa V t 25 mv V t,1 25 mv C g, 1284 pf K µa/v 2 C gs, 5321 pf V th, V C s, 5148 pf V th, V φ c,s 7.25 V λ 22 3 V n c,s.9 1 T f,2 1.5 b c,g.38 V I s, µa a c,g.5 1 V t,2 25 mv δ vg.2 V V cp 6 V a.94 1 R Vcp 3 kω a /V i off, µa a /V 2 i off, µa a /V 3 V bat 13 V control input u U = [u, u + ] that minimizes the switching losses i L v s t = x 1 x 3 x 2 t an takes into account the current slew rate i L /t or the voltage slew rate v s /t at the output terminal of the Power Switch. For this, the optimal control problem min u U s.t. Jx = t j f t j x 1 x 3 x 2 t t x = fx, u, xtj = xj [ ] [ ig,1 i u = U = g,1 i + ] g,1 s u s x, u s l i g,2 i+ g,2 1 is formulate. By means of the Lagrange ensity x 1 x 3 x 2 of the cost function Jx the minimization of the occurring power losses uring the switching operation t [t j, tj f ], j {on, off} is assure. Furthermore, xj represents the initial state for the on an off switching operation, respectively. The input u is constraine with the upper an lower physical limits of the charge an ischarge reference current, i g,1, i+ g,1 an i g,2, i+ g,2, respectively. To guarantee the switching of the Power MOSFET, i g,1 an i g,2 are assume to be positive. The term s l sx, u s u refers to the path constraint in orer to limit the current or voltage slew rate s to its esire upper an lower limit s u an s l. Note that for the switch-on operation only the charge current source an for the switch-off operation only the ischarge current source is use, i.e. u T = [i g,1 ] an u T = [ ]. Summarizing, four ifferent cases of the optimal control problem have to be solve: 1 The current slew rate i L /t uring the switch-on operation j = on is controlle by u T = [i g,1 ]. The path constraint is set to s = i L /t an the esire upper an lower limits are s u = i L, an s l = i L,. 2 The current slew rate i L /t uring the switch-off operation j = off is controlle by u T = [ ]. The path constraint is set to s = i L /t an the esire 7193

5 19th IFAC Worl Congress Cape Town, South Africa. August 24-29, 214 upper an lower limits are s u = i L, an s l = i L,. 3 The voltage slew rate v s /t uring the switch-on operation j = on is controlle by u T = [i g,1 ]. The path constraint is set to s = v s /t an the esire upper an lower limits are s u = v s, an s l = v s,. 4 The voltage slew rate v s /t uring the switch-off operation j = off is controlle by u T = [ ]. The path constraint is set to s = v s /t an the esire upper an lower limits are s u = v s, an s l = v s,. 5. NUMERICAL RESULTS OF THE OPTIMAL CONTROL PROBLEM The optimal control problem 1 is formulate as a finiteimensional optimization problem by means of full iscretization using the trapezoial rule an assuming a constant control input in the respective time interval, see, e.g., Betts 21. The finite-imensional optimization problem is solve using Matlab in combination with the Sequential Quaratic Programming metho from the Large-Scale Nonlinear Programming package SNOPT, see Gill et al. 26. The optimization was carrie out for the time intervals t on [1, 46] an t off [3, 66] with 24 iscretization points for each interval. Afterwars, a simulation was performe in Matlab, where the maximum value of the optimal control input was assigne outsie the time intervals t on an t off. The numerical results for ifferent voltage an current slew rates are summarize in Fig. 5a an Fig. 5b. In etail, the first row presents the gate current profiles i g,1 an for the switch-on an switch-off operation. In the secon an thir row, the resulting output terminal voltage v s an the respective slew rate v s /t are epicte an in the fourth an fifth row, the loa current i L an the respective slew rate i L /t are shown. Finally, the sixth row presents the switching losses il v s t. The results show that by means of the calculate gate current profiles, v s /t an i L /t is not only limite, but controlle to their esire maximum slew rate. As long as no slew rate constraint is violate, the gate current profile is at its maximum value. Thus, maximal switching spee an therefore minimal switching losses are achieve. This arises irectly from the consieration of the switching losses in the cost function 1. A constant gate current profile with a lower maximum value woul only change the peak of the slew rate. Clearly, this woul result in higher switching losses. A closer look at the gate current profiles shows that the profiles for the switch-on an switch-off operation are not ientical. This is ue to the ifferent physical characteristics of the charge an ischarge current sources. Because of the inuctive switching, the current lags behin the voltage. Therefore, by controlling the current slew rate, the voltage slew rate exhibits small spikes shortly before the current slew rate is active. This must be consiere for voltage relate electromagnetic compatibility problems. 6. CONCLUSION AND FUTURE WORK In this work, optimal gate current profiles are erive which simultaneously control the current or voltage slew rate at the output terminal of a Smart Power IC an minimize the switching losses. For this, a tailore mathematical moel of the Smart Power IC was evelope an ientifie. Base on this moel, an optimal control problem that limits the current or voltage slew rate to a preefine value uring the switch-on an off operation was formulate an numerically solve. The presente metho can be irectly integrate in the harware esign process of the Smart Power ICs. In particular, esign questions regaring the necessary ynamics an current limits of the charge an ischarge current source can be answere in a systematic way. Due to moel uncertainties an temperature epenencies the irect application of the gate current profiles in pure feeforwar control strategies is of limite practical use. However, the profiles can be utilize as an optimal initial guess for aaptive feeforwar strategies. Such a strategy is presente in Blank et al. 214 using an iterative learning control strategy that aapts the gate current profile in real time. REFERENCES P.E. Allen an D.R. Holberg. CMOS analog circuit esign. Oxfor University Press, New York, Oxfor, 2n eition, 22. N. Arora. Mosfet moeling for VLSI simulation: theory an practice. Worl Scientific, Singapore, 27. B.J. Baliga. Funamentals of power semiconuctor evices. Springer Science + Business Meia, LCC, New York, 28. J. Betts. Practical methos for optimal control using nonlinear programming. Siam, Phiaelphia, 21. M. Blank, T. Glück, A. Kugi, an H-P. Kreuter. Slew rate control strategies for smart power ics base on iterative learning control. In Proceeings of the Applie Power Electronics Conference an Exposition APEC, Fort Worth, 16-2 March 214. Y.S. Chauhan, C. Anghel, F. Krummenacher, R. Gillon, A. Baguenier, B. Desoete, S. Frere, A.M. Ionescu, an M. Declercq. A compact c an ac moel for circuit simulation of high voltage vmos transistor. In Proceeings of the 7th International Symposium on Quality Electronic Design ISQED 6, pages 6 11, San Jose, California, March 26. L. Dang, H. Kuhn, an A. Mertens. Digital aaptive riving strategies for high-voltage igbts. In Proceeings of the IEEE Energy Conversion Congress an Exposition ECCE, pages , Phoenix, AZ, Sept C. Enz an E.A. Vittoz. Charge-base MOS transistor moeling: the EKV moel for low-power an RF IC esign. John Wiley & Sons, Hoboken, New York, 26. P.E. Gill, W. Murray, an M.A. Saues. User s Guie for SNOPT Version 7: Software for Large-Scale Nonlinear Programming, 26. URL sbsi-sol-optimize.com. access D.A. Grant an J. Gowar. Power MOSFETS: theory an applications. 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6 19th IFAC Worl Congress Cape Town, South Africa. August 24-29, 214 ig,1, ig,2 µa vs V t v s mv il A t i L ma switch-on switch-off switch-on switch-off i Lvs t W t t t t t v s : unlimite 6 mv 5 mv 4 mv t i L : unlimite 15 ma 125 ma 1 ma a Control results of the voltage slew rate. b Control results of the current slew rate. Fig. 5. Numerical results of the optimal control problem for the switch-on an switch-off operation. Y. Lobsiger an J.W. Kolar. Close-loop igbt gate rive featuring highly ynamic i/t an v/t control. In Proceeings of the IEEE Energy Conversion Congress an Exposition ECCE, pages , Raleigh, NC, 15-2 Sept N. Mohan, T.M. Unelan, an W.P. Robbins. Power electronics: converters, applications, an esign. John Wiley & Sons, Hoboken, New York, 3r eition, 23. B. Murari, F. Bertotti, an G.A. Vignola. Smart Power ICs: Technologies an Applications. Springer, Berlin Heielberg New York, 22. N. Oswal, B.H. Stark, D. Holliay, C. Hargis, an B. Drury. Analysis of shape pulse transitions in power electronic switching waveforms for reuce emi generation. IEEE Transactions on Inustry Applications, 47 5: , 211. W. Pribyl. Integrate smart power circuits technology, esign an application. In Proceeings of the 22n European Soli-State Circuits Conference, ESSCIRC 96, pages 19 26, Neuchâtel, Swiss, Sept M. Rose, J. Krupar, an H. Hauswal. Aaptive v/t an i/t control for isolate gate power evices. In Proceeings of the IEEE Energy Conversion Congress an Exposition ECCE, pages , Atlanta, GA, Sept. 21. G. Schmitt, R. Kennel, an J. Holtz. Voltage graient limitation of igbts by optimise gate-current profiles. In Proceeings of the IEEE Power Electronics Specialists Conference, PESC, pages , Rhoes, June 28. D. Schröer. Leistungselektronische Bauelemente. Springer, Berlin Heielberg, 3r eition, 26. B. Wittig an F.W. Fuchs. Analysis an comparison of turn-off active gate control methos for low-voltage power mosfets with high current ratings. IEEE Transactions on Power Electronics, 273: ,