A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide

Transcription

1 Circuit Level Fault Moel for esistive Shorts of MOS Gate Oxie Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker an Weiping Shi Dept. of Electrical Engineering Texas &M University College Station, TX , US STCT Previous researchers in logic testing focuse on s in MOS gate oxies that have zero-resistance. However, most s are resistive an may cause elay faults. In this paper, we propose a simple an realistic elay fault moel for gate oxie s. reasonaly accurate metho is propose to compute elay change ue to resistive s. We also enumerate all possile fault ehaviors an present the relationship etween input patterns an output ehaviors, which is useful in TPG.. INTODUCTION Delay test etects small manufacturing efects that o not cause functional failure ut affect the spee of the circuits. In this paper, we consier the fault moel of resistive gate oxie s, which can e use for elay test. anerjee an raham first consiere gate oxie s. They assume the s are zero-resistance an moele the s as stuck-at faults []. Hawkins an Soen [] presente ata to show the resistance is in the range of 00 s to 000 s of ohms. Syrzycki [3] consiere ifferent structures of gate oxie s an propose lumpe-element moels. Gaitone an Walker [4] stuie some prolems face in mapping spot efects incluing gate oxie s to changes in the nominal circuit. Hao an McCluskey [5] stuie the logic an elay ehavior of resistive s. Their circuit level fault moel is shown in Figure, which covers the external ehaviors of gateto-source s, gate-to-rains an gate-to-channel s. Note that ecause the polysilicon gate is generally ope with n type opant, there is a ioe in series with the resistor for PMOS transistors. Hao an McCluskey also showe that faults cause y gate oxie s can e epenent on input signals of oth the gate containing the fault an other gates [6]. n they foun that ery Low oltage testing woul etect such pattern epenent faults cause y resistive s [7]. In [8], we propose a circuit level fault moel for resistive s in the interconnect. However, resistive s in MOS gates are more complex in certain cases. Moeling gate oxie s as elay faults helps elay test to etect more s. Previous moels lack in explicit Dept. of Computer Science Texas &M University College Station, TX , US walker@cs.tamu.eu relationship etween elay changes an resistive s. In this paper we propose a physically realistic an economical fault moel for elay test. esistive gate oxie s are moele as elay faults as well as logic faults accoring to the resistance. We also enumerate all possile fault ehaviors an present the relationship etween input patterns an output ehaviors. The fault moel is reasonaly accurate an easy to implement for elay fault simulation in large inustrial circuits. gate-torain gate-tosource gate-tosource gate-torain transistor PMOS transistor Figure. Gate-to-source an gate-to-rain s for an PMOS transistors.. FULT MODEL The ojective of the gate oxie moel is to transform the effect of the resistive into a elay fault or a logic fault, an compute the elay change as a function of resistance. To analyze electrical ehaviors of in the circuit level, consier the circuit in Figure. There are two cells: the riving cell with output noe an the faulty cell with output noe. In the figure, an are interconnect parasitic resistance, an C are lumpe interconnect parasitic an gate input capacitance. In Figure the efect is a gate-to-source insie an transistor. Circuits for other efects are similar, except that the faulty transistor may e PMOS or the may e gateto-rain. The faulty cell contains one faulty transistor, an the rest of transistors are goo. In this paper, we only consier the at input transistors, i.e. transistors riven y external signals. Shorts at other transistors can e analyze similarly y partitioning the faulty cell to make the faulty transistor riven y an external signal. For

2 example, an ND cell can e partitione into a NND cell riving an inverter, in orer to analyze the at one of the inverter transistors. riving cell PMOS faulty cell PMOS faulty n-mos Figure. The circuit with an gate-to-rain. Circuits with other s are similar. We assume there is only one single input transition on the faulty cell. When a signal transition at the input of the riving cell causes the transition at we consier the sum of the riving cell elay an the faulty cell elay. However, when the signal at is static, an the transition at is cause y a transition at other input of the faulty cell, we only consier the faulty cell elay. Here elay is compute at the 50% of point on the signal waveform, an enote as. When there is no, the riving cell elay is enote as D, an the faulty cell elay is enote as D. oth D an D can e compute y any commercial tool, such as SPICE.. gate-to-rain Static analysis The circuit in the static analysis is shown in Figure 3. an own are pull- an pull-own resistance of the riving cell respectively. represents the pull- resistance in the faulty cell. The pull-own path insie the faulty cell is ivie into two parts from the faulty transistor, represente y resistors own an own3. The linear resistance of the faulty transistor is inclue in own. C When a pull-own path in the riving cell is forme, s = off, s = on, s 3 = on an s 4 = off. The voltage at noe is erive as + own own =. () own own3 The voltage at noe own, can e erive similarly. Define the rige Threshol esistance (T) own, such that when < own, own is larger than the logic low threshol voltage LL. Then accoring to (), ( )( + ) LL own =. () own own3 LL Therefore when < own, own > LL, there is a logic fault at. When > own, there will e no logic fault at ut there might e a elay fault. When a pull- path in the riving cell is forme, similar voltage expressions at noe at noe an corresponing Ts can e erive. Transition analysis We present transition analysis y two cases. In one case, a signal transition propagates through the riving cell to the faulty cell. In the other case, a signal transition happens only at the faulty cell while the signal at noe is static. For each case, we assume is large enough such that there is no logic fault when the circuit is static. We moel the resistive as a elay fault, an propose the metho to compute the elay change ue to the. Case ssume a falling signal transition happens at noe an accoringly a rising signal transition happens at noe. During the transition, the faulty transistor is cutoff an a pull- path insie the faulty cell in forme. If there is no present, is ischarge only through own an C is charge only through. With the present of, a current path through is forme etween noe an. Then is partially ischarge to C ecause the initial voltage at is higher than that at. t the same time, is also charge y the faulty cell through. The circuit in transition analysis is illustrate in Figure 4. s s s 3 own3 s 4 own3 own own own C Figure 3. The circuit uner static analysis. Figure 4. With the present of, a current path is forme etween noe an.

3 Our elay moel works as follows. Through analyzing the circuit in Figure 4, we compute the riving cell elay an the faulty cell elay. Consiering oth elays are functions of, we compute the ratio etween the elay with some certain value of an the elay with =, then approximate as = D + D. (3) = = The computation of is as follows. First we introuce an effective resistance eff to replace the ischarging path - own3 - -C. The value of eff is compute y equalizing the average current of the two circuits in Figure 5, uring a certain time interval T. The value of T is the time for the voltage of in the circuit of Figure 5(a), ropping from its initial voltage 0 to the mile of the whole voltage range. The equivalent current metho is also use to calculate effective capacitance in [9]. In this paper we use it to compute eff. 0 (a) + own3 + C 0 eff Figure 5. eff is compute y equalizing the average current in the two circuits. We get C ln(), eff = ( + own3 + ). C ( C C) + C + ln( ) C Secon, ecause we replace path - own3 - -C with eff, the circuit ecomes a first orer linear system an the riving cell elay can e erive as () = C, (4) own f ) own 0.5 where f is the intrinsic falling elay of the riving cell, =( own + )//( + own3 + )// eff. The symol // represents the parallel computation of two resistances. Note when is infinity, = is the sum of intrinsic gate elay an gate loa elay uner the lumpe C elay moel. The computation of is similar. For the rising signal transition at path - - own3 - is a charging path. We insert a resistance eff at to equalize the charging effect of the path. The value of eff is compute similarly. Here the ifference is, T is the time for the voltage of C in the circuit of Figure 5(a), rising to the mile of the whole voltage range. Therefore, we get C ln() = ( + own3 ). C ( C C) + C + ln( ) C + C, eff + Then the faulty cell elay is erive as own r ) own 0.5 = α C, (5) where r is the intrinsic rising elay of the faulty cell, α=( )/ is introuce to scale r ecause the initial voltage for the rising transition at is not zero, an =( own + + eff + + own3 )//. Experiments are performe on a circuit, which consists of an inverter as the riving cell, an an NND gate as the faulty cell. TSM80 nm.8 technology is use. ssume LL = 0.6, then rige Threshol esistance (T) own = 770Ω accoring to our moel. esults of elay ~ compute y our moel an y SPICE simulation are shown in Figure 6. Our moel provies reasonaly accurate approximation of the elay change with present of. When < own, there is a logic fault on noe an when own, there is a ecreasing elay fault. Delay (ps) own logic fault ecreasing elay fault (ohm) SPICE Estimate Figure 6. Decreasing elay estimate an compute y SPICE with increasing values of. Case Consier an transistor T g, which is in series with the faulty transistor T f. ssume there is a rising signal riving T g, resulting in a falling transition at. The signal at noe which is riving T f, is static high. During the transition, a pull-own path through T f an T g is forme. The simplifie circuit is shown in Figure 7, where own3 represents the linear resistance of T f an the lock connecting output of the faulty cell, an own represents the linear resistance of the lock connecting T f an Gn.

4 own3 own Figure 7. C is ischarging through the pull-own path in the faulty cell. The final voltage at is epenent on the value of, an can e erive as = own (6) own Then the faulty cell elay is compute as = C, f ) ( own + own3 + ) 50% where f is the intrinsic rising elay of the faulty cell. Similarly, we approximate as = = C D. (7) Experiments results on the same circuit are shown in Figure 8. The logic high threshol HH is assume to e HH =., an corresponing T is = 56Ω. The figure shows that when <, there is a logic fault on noe an when, there is a increasing elay fault in the faulty cell. Delay (ps) increasing elay fault logic fault SPICE Estimate (ohm) Figure 8. Increasing elay estimate an the elay compute y SPICE with increasing values of.. gate-to-source In the case of an gate-to-source, it may affect the circuit ehaviors in two ways. ) The acts as a resistor that connects an Gn, thus reucing the voltage at ue to voltage ivision. The value of the resistor is + own, where own represents the linear resistance of the lock etween the faulty transistor an Gn. Note that whether the current path through to Gn is forme epens on the sie inputs of the faulty cell. Then the can e viewe as a resistive rige etween interconnect an GND, an moele using the metho propose in Li et al. [8]. ) The connects an through the faulty transistor, an currents flow through to the faulty cell output, then though some transistors to Gn. Therefore the voltage at is affecte an a functional fault possily happens at. elay fault at possily happens an the elay change can e erive similarly..3 PMOS gate-to-rain The gate-to-rain in a PMOS transistor can e moele as a rige resistance in series with a ioe etween the interconnect an. The ioe is always forwar-iase an is represente y a certain voltage rop across the rige. The ehavior of the ioe can e analyze similarly with the metho in Hao an McCluskey [3]. Due to the ioe, currents can never flow through to..4 PMOS gate-to-source Similar analysis to gate-to-rain s can e performe, except for the voltage rop effect ue to the ioe. n when a pull- path is forme in the riving cell, currents cannot flow through to ue to the ioe. 3. CONCLUSIONS In this work, we propose a circuit level fault moel for resistive gate oxie s in MOS transistors. The resistive is moele as a logic fault when the resistance is less than the value of rige threshol resistance (T). Otherwise it is moele as a elay fault. We erive expressions of T for all possile ehaviors. To etect a logic fault, the test pattern shoul e selecte to maximize T. With explicit expressions of T, it is possile to compare performance of ifferent test patterns analytically. Previous methos, for example the stuck-at fault moel [] an the resistive ehavior analysis in [5], are insufficient for that. For the case that the provokes elay changes in the circuit, we propose a fast yet reasonaly accurate elay estimation metho an provie close form elay functions in terms of the resistance. In Tale I, for each type of, we list elay ehaviors for ifferent input signals. T f is the faulty /PMOS transistor an T g is another /PMOS transistor. The rising/falling signal on T g or T f provokes a rising or a falling transition at the output of the faulty cell. In the tale, T f T g means the two transistors are in parallel, T f ~ T g means the two transistors are in series, ecrease means ecreasing elay, increase means increasing elay, an 0 means

5 there is no change in elay when the is present. The tale enumerates all input patterns that will cause increasing elay (or ecreasing elay) at the output ue to the efect. The amount of elay change is given y such formulae as (3) an (7). The tale an corresponing elay formula can guie TPG to fin the est test patterns that can maximize the etectaility. Tale I. ehaviors for each type of uner ifferent input signals. Short nmos g-s nmos g- pmos g- pmos g-s Input of faulty transisto r T f Input of other transistor T g Delay change rising static increase falling static ecrease static rising 0(T f T g ), increase(t f ~ T g ) static falling 0(T f T g ), ecrease(t f ~ T g ) rising static ecrease falling static ecrease static rising ecrease(t f T g ), increase(t f ~ T g ) static falling increase(t f T g ), ecrease(t f ~ T g ) rising static ecrease falling static increase static rising ecrease(t f T g ),0(T f ~ T g ) static falling increase (T f T g ),0(T f ~ T g ) rising static ecrease falling static increase static rising ecrease(t f T g ),0(T f ~ T g ) static falling increase(t f T g ),0(T f ~ T g ) [6] H. Hao an E. J. McCluskey, esistive s within CMOS gates, IT99, pp [7] H. Hao an E. J. McCluskey, ery-low-voltage testing for weak CMOS logic ICs, IT993, pp [8] Z. Li, X. Lu, W. Qiu, W. Shi an H. Walker, " circuit level fault moel for resistive opens an riges", CM Trans. on Design utomation of Electronic Systems, 8(4), 003, pp [9] J. Qian, S. Pullela an L. Pillage, Moeling the Effective capacitance for the C interconnect of CMOS gates, IEEE Trans. CD, 3(), 00, pp EFEENCES [] P. anerjee an J. raham, Generating tests for physical failures in MOS logic circuits, IT983, pp [] C. F. Hawkins an J. M. Soen, Electrical characteristics an testing consierations for gate oxie s in CMOS ICs, IT985, pp [3] M. Syrzycki, Moeling of gate oxie s in MOS transistors, IEEE Trans. CD, 8(3), 989, pp [4] D. Gaitone an D. M. H. Walker, Circuit-level moeling of spot efects, DFT 99, pp [5] H. Hao an E. J. McCluskey, On the moeling an testing of gate oxie s in CMOS logic gates, DFT 99, pp