BI-DIRECTIONAL MIXED SIGNAL CONNECTION MODULES FOR AUTOMATIC INSERTION

Transcription

1 BI-DIRECTIONAL MIXED SIGNAL CONNECTION MODULES FOR AUTOMATIC INSERTION Olaf Zinke Caence Design Systems San Diego, CA, USA Abstract Efficient simulation of mie signal esigns requires the ability to quickly echange analog an igital representations of a cell uring the esign an verification process. For the interconnection between analog nets an igital signals, connect moules are use. Mostly these connections elements are limite to being uni-irectional when inserte automatically. The paper escribes how true bi-irectional connect moules can be realie in VERILOG-AMS by using special language features. Introuction It is common to simulate analog an igital represente parts of a SOC simultaneously using Mie Signal Simulators like the Caence AMS Simulator. Mostly mie signal stanar languages (VERILOG-AMS, VHDL-AMS) are use throughout such esigns. They escribe the structure as well as the behavior of the esign or IC. The simulation tool ecies base on the kin of escription insie of the moel or of a part of the moel, which structure or behavior will be evaluate in the igital omain or in the analog omain uring the mie signal simulation. What about when analog an igital interconnect? - At these connection points iscrete igital signals have to be transforme into continuous analog information an vice versa. Both VERILOG-AMS an VHDL-AMS are capable escribing of such interaction behavior. Both are true mie signal languages with moel-internal cross-omain rea access of values. VHDL-AMS requires manual or netlister base insertion of these connection elements, whereat types an natures must match or be compatible (). VERILOG-AMS with its aitional automatic insertion of connect elements uring the esign elaboration phase gives the user more fleibility in terms of using the language as a esign language. The user is able to echange the implementation of a moel very quickly without the necessity of an afterwars manual type-matching or renetlisting of major parts of the esign. The user just interconnects igital an analog wires in the schematic or in the tet base esign an specifies the rules efining what connect moules shoul be use for the possible cases of inter-connection. During esign elaboration the isciplines get resolve an base on that the connect moules get inserte following the above mentione connect rules (). This paper talks about connect element moeling in VERILOG- AMS. Uni-Directional an Bi-Directional Connect Elements In a simple mie signal case analog nets an igital signals are connecte an only one of them is riving the other one. The connection is uni-irectional. In the A-to-D case the connection element etects the analog voltage level an applies the appropriate logic state to the igital receivers. In the D-to-A case the connection element reas the state of the igital rivers at the input of the connection element an applies the voltage to the analog output net accoringly. The connection moule features built into the VERILOG-AMS language enhance the D-to-A case by aing the capability of applying a ifferent state than what the output of the igital river elivers to the igital receivers being on the same wire like the igital rivers an the logic input of the connection element. This is useful for eample, applying elay time cause by a certain analog loa on a igital net. Because of the efinition of the VERILOG-AMS language this is possible with connection moules having one single input pin. Especially in large SOC esigns a thir case is very common. There are blocks, represente as analog behavioral or as schematic, connecte to bi-irectional communication or ata busses. That is, the analog block receives information an is also able to s information over the same connection. On the igital sie there coul be several blocks with INOUT connections at this bus. Each bus wire nees an INOUT connection moule. The ifficulty is that the connection moule for automatic insertion uring the elaboration phase can only have one pin on the logic sie. That is, the connect moule nees to be able to rea an write at the same time via one single port to ensure true bi-irectional behavior. Uni-Directional Eample In the uni-irectional analog-to-igital (a) case every change of the igital input state is etecte. The input state information is use to control voltage an impeance of the analog output. In the simplest case the output structure consists of a controlle ieal voltage source an a controlle serial output resistor. The iscrete real variables rset an vset (see EXAMPLE I) are set to the output impeance an output voltage levels that represent the analog output behavior for the given igital input state. Both trigger transition functions. A change of vset lets the ieal voltage source V() change to the appropriate voltage level with the specifie rise/fall time. At the same time a change of rset triggers the transition of the output resistance R = V(, aval) / I(, aval).

2 EXAMPLE I SIMPLE DIGITAL-TO-ANALOG CONNECT MODULE `inclue "isciplines.vams" `timescale ns / ps connectmoule a(val, aval); input Val; output aval; logic Val; electrical aval; // parameter eclaration an initialiation not shown begin case(val) 'b: begin vset=vlrive;rset=rlrive; 'b: begin vset=vhrive;rset=rhrive; 'b: begin vset=vrive;rset=rrive; 'b: begin vset=vrive;rset=rrive; case analog begin V() <+ transition(vset,,vrise,vfall); I(,aVal) <+ V(,aVal) / transition(rset,,rrise,rfall); moule Creating a Bi-Directional Connect Moule In the above eample there was no feeback from the analog sie back to the igital sie. The connection was uniirectional. In cases like shown in Fig. the connect moule has to work in both irections. How can we fee back information equivalent to the analog solution to the igital sie? The iea is to use the river/receiver segregation feature of the VERILOG-AMS language. Digital rivers an receivers are separate at igital wires connecte to connect moules. The connect moule etects what state the igital rivers connecte to the igital wire apply. Using this information an other conitions the connect moule can ecie what logic state the igital receivers connecte to the same wire will actually see. the right river strength at the analog output noe. The an states shoul apply an appropriate voltage Vout via a lower resistance Rout to the analog output noe, Z shoul apply a voltage in a high resistive way, which coul vary epent on the process an is parameterie (Fig. ). The unefine X state is hanle in a special way. If riven to the logic input of the connection moule, an X is irectly applie to the igital receivers. In this case the voltage source an resistance applie to the analog output noe will be set by user-efine parameters. Because there is no unefine state in the continuous analog omain, it is the choice of the simulation user to ecie about the voltage he wants having generate in this case. He may want to apply this voltage in a very low resistive way to force the analog voltage settling at the esire voltage level relatively inepent of the behavior of the connecte analog circuitry. B. From Analog to Digital The analog solver of the mie signal simulator resolves the analog output noe of the connection element uner the full recognition of the internal supply network an the analog structure of the connecte analog cells. The resulting voltage V(aVal) from aval to groun an current flow through Rout an through the Vout source represent the logic resolution on the analog sie of the wire. This logic resolution available as analog voltage/current information is etecte by the connection moule (Val_out) an fe back to the receivers in the logic block connecte to this INOUT wire. Val Val_out = f(v(aval), I(aVal)) Rout=f(Val_in) Vout=f(Val_in) I(aVal) V(aVal) aval electrical network Verilog(D) structure Fig. Bi-Directional Connect Moule Fig. + - Bi-Directional Connection A. From Digital to Analog Assuming for the moment there is only one logic block connecte to the wire, the connection moule inserte for this wire reas what the igital block rives on the net. The state coul be an active or, a Z or it coul be unefine X. This information nees to be translate to analog an applie with If the voltage at the analog connection is below the - threshol or above the -threshol, the an states are assigne to the igital INOUT port accoringly. If Vout leaves the or range i.e. after a rising ege of the igital input signal was etecte, Val_out stays unchange for the first moment. If the voltage remains in the X-range for longer than a preset time limit elay the output Val_out will change to X an stay X until the voltage moves back into the or range. This way too slow rise or fall transitions get etecte. This mechanism is able to etect the Z-conition at the analog connection moule noe as well. Therefore the current information is use. Detection is possible only if the esignate Z-voltage recognition level is within the X-range. If this is the case when a Z is etecte at the igital input an the absolute current into the analog connect moule port is less than a certain limit, then Val_out will be set to Z.

3 C. Implementation The statement Assign Val=Valout applies the igital output state to the receiver connecte to the logic INOUT port of the connect moule (Eample II). Cross statements are use for a precise etection of the voltage an the current threshol crossings relate to the analog connect moule port. The signals vstate an istate are use to monitor the analog output voltage an current. EXAMPLE II BASIC BI-DIRECTIONAL CONNECT MODULE `inclue "isciplines.vams" `timescale ns / ps connectmoule biir(aval, Val); inout aval, Val; electrical aval; logic Val; parameter real mahizcurrent =.u; parameter real elay = ; parameter real elay =.5 * elay; EXAMPLE II CONTINUED outofzcurrent=; begin istate=; outofzcurrent=; or istate) begin case(vstate) : Valout= (Val==='b)? 'b : 'b; : Valout= ((istate==='b)&(val==='b))?'b:'b; : Valout= (Val==='b)? 'b : 'b; case analog begin V() <+ transition(vset,,vrise,vfall); I(,aVal) <+ V(,aVal) / transition(rset,,rrise,rfall); moule // some parameter eclarations not shown electrical ; reg Valout, istate, inxrange, outofzcurrent; logic Valout; real vset, rset; integer vstate; assign Val = Valout; // initialiation not shown case(val) 'b: begin 'b: begin 'b: begin begin vset=vlrive;rset=rlrive; vset=vhrive;rset=rhrive; vset=vrive;rset=rrive; Valout='b; 'b: begin vset=vrive;rset=rrive; case begin vstate=; inxrange=; inxrange=; inxrange=; begin vstate=; inxrange=; inxrange) begin:xrangedelay #elay vstate=; inxrange=; inxrange) isable XRangeDelay; outofzcurrent) begin:outofzcurrentdelay #elay istate=; outofzcurrent=; outofzcurrent) isable outofzcurrentdelay; moule The signal inxrange is use to show the analog voltage being in the X-range but for not longer than the time limit parameter elay. When the connect moule rea an unefine X on the logic sie it also applies this X state back to the receivers. Table I summaries the functionality aroun the istate an vstate signals. D. Eample Fig. shows the simulate waveform of the bi-irectional case where the two igital rivers (signals igrv an igrv) are connecte to the igital port of the connect moule. At point M both rivers apply. The signal Val is the logic TABLE I FUNTION TABLE Val_in VSTATE ISTATE Val_out VSTATE V(aVal) > thresholhi thresholhi >= V(aVal) >= threshollo V(aVal) < threshollo ISTATE abs(i(aval)) <= mahizcurrent abs(i(aval)) > mahizcurrent

4 Fig. Eample Waveform A Fig. 4 Eample Waveform B resolution of both river signals. This is the logic input of the connect moule. Accoringly vset is set to the low voltage level. The voltage aval at the analog port of the connect moule is almost at the same low voltage level. Note that this voltage level is etermine by the analog circuitry connecte to the analog port of the connect moule as well. This results in vstate being at an Valout (the logic state the connect moule is applying to the igital receivers connecte to the igital port) being at. In this case Val an Valout are equivalent. At point M the igital rivers force opposite states. This results in a resolution to X on Val. Therefore also Valout turns X immeiately. Obviously the analog circuitry at the analog port is very high resistive, because only a low current is necessary to force.5 Volts to this noe. That is why istate is. But istate oes not influence Valout, because Val is at X. At point M5 both rivers are HiZ. Also Valout shows Z after the current through the analog port has settle an istate confirms that the analog circuitry at the analog port is in the Z- state also. In Fig. 4 the eternal analog circuitry at the analog port of the connect moule rives a voltage close to Volts. This results in a logic state at Valout when the igital rivers are at Z (see point M) or at also. In all other cases Valout elivers an X to the igital receivers Enhancements The above eample contains a minimum set of connect moule features. Enhancing this moel means aing features bringing the moel closer to the reality. The user shoul be aware that aing features means also lowering the simulation spee. There coul be very many connect moules inserte in the esign, so aing aitional features coul slow own the simulation remarkable. It woul be necessary to supply the user with several connect moules with ifferent etail level. That way the user coul choose a moel with respect to the esire etail-tospee ratio. A. Power Supply Depency One of the first enhancements the user woul think of is power supply epency of the buil-in threshols an the output voltage levels. This coul be one easily by bining the connect moule parameters to global power supply parameter. This way a static power supply epency is realie. If the simulation of the esign requires ynamic power supply epencies of the connect moule, this can be implemente in VERILOG-AMS by referencing or connecting to global power supply noes from insie of the connect moule. Effects like power on/off behavior or transient power supply noise become visible. For this purpose the Caence AMS Simulator allows the use of inherite connections (via VERILOG-AMS attributes) insie of connect moules as well. B. Depency on The Number of Digital Drivers The connect moule shown in EXAMPLE II uses the resolve logic state of the rivers on the igital pin as the logic input signal. The analog network insie of the connect moule is built inepently of the number of rivers on the igital net. EXAMPLE III shows a bi-irectional connect moule containing this epency. From insie of a connect moule information about the igital rivers on a igital net can be accesse. The access functions are efine in the VERILOG-AMS Language Reference Manual (). The function $river_count(<wire_name>) returns the number of rivers connecte. The favorable way to ask for the number of rivers is the igital initial block, because the number of rivers will not change uring the simulation.

5 EXAMPLE III BI-DIRECTIONAL CONNECT MODULE WITH DEPENDENCY ON NUMBER OF DIGITAL DRIVERS `inclue "isciplines.vams" `timescale ns / ps connectmoule biir(aval, Val); inout aval, Val; electrical aval; logic Val; electrical, y; reg Valout; // some eclarations not shown parameter real ghonrive=./rhonrive; parameter real ghoffrive=./rhoffrive; parameter real glonrive=./rlonrive; parameter real gloffrive=./rloffrive; real rhset, rlset; integer DrCount, i; integer XCount, ZCount, LCount, HCount; assign Val = Valout; initial DrCount=$river_count(Val); // initialiation not shown begin XCount=; ZCount=; LCount=; HCount=; for (i=; i<drcount; i=i+) case($river_state(val,i)) 'b: LCount=LCount+; 'b: HCount=HCount+; 'b: begin XCount=XCount+; Valout='b; 'b: ZCount=ZCount+; case rhset=./((xcount+hcount)*ghonrive+ (ZCount+LCount)*ghoffrive); rlset=./((xcount+lcount)*glonrive + (ZCount+HCount)*gloffrive); begin vstate=; inxrange=; inxrange=; inxrange=; begin vstate=; inxrange=; inxrange) begin : XRangeDelay #elay vstate=; inxrange=; EXAMPLE III CONTINUED or istate) begin case(vstate) : Valout= (Val==='b)? 'b : 'b; : Valout= ((istate==='b) & (Val==='b))? 'b : 'b; : Valout= (Val==='b)? 'b : 'b; case analog begin V() <+ vhrive; V(y) <+ vlrive; I(,aVal) <+ V(,aVal) / transition(rhset,,rrise,rfall); I(aVal,y) <+ V(aVal,y) / transition(rlset,,rrise,rfall); moule The function $river_state(<wire_name>,<river_counter>) returns the status of the specifie river an the function river_upate(<wire_name>) returns true if at least one of the connecte rivers on this net changes its state. If we woul stay with our current analog network implementation (serial resistance an voltage source to groun) it woul get ifficult to a epency on the number of igital rivers an their state. For every igital river we woul nee to switch such kin of resistance/voltage source branch in parallel. This leas to a topology change epent on the number of igital rivers. It is better if we use in this case a ifferent analog output structure (Fig. 5) that can be mae easily epent on the number of rivers without changing the topology. Vhrive an Vlrive are constant voltage sources. The Rh an Rl resistors are epent on the number of igital rivers an on their current states, i.e. Rh is calculate base on the number of igital rivers that are X or multiplie with the switche-on conuctance an ae to the switche-off conuctance multiplie with the number of rivers being Z or L. The voltage on the analog port an the absolute current ifference of the current through both of the resistances are use to etermine the logical state applie to the igital receivers. After characteriing accoring to the technology use, this connect moule moels the actual circuit behavior alreay very realistic. An aitional enhancement coul be to take the inxrange) isable XRangeDelay; outofzcurrent) begin : outofzcurrentdelay #elay istate=; outofzcurrent=; Ih Rh=f(rivers) Val aval Val_out = f(v(aval), Ih, Il) Rl=f(rivers) outofzcurrent) isable outofzcurrentdelay; V(aVal) Il outofzcurrent=; begin istate=; outofzcurrent=; Vhrive Fig. 5 Vlrive Connect Moule Structure

6 strength of each igital river into account an varying both resistances accoringly. Summary Bi-irectional connect moules have been create using VERILOG-AMS language features. Connect moule eamples with ifferent level of moele etail were shown. These moules can be use for rule base automatic insertion accoring to the VERILOG-AMS language reference manual. Automatic Insertion of connect moules uring the esign elaboration phase enables an efficient mie-signal simulation of schematic as well as tet base esigns. References () IEEE Stanar VHDL Analog an Mie-Signal Etensions," Institute of Electrical an Electronics Engineers, New York, December 999. () IEEE Stanar Verilog Harware Description Language, Institute of Electrical an Electronics Engineers, IEEE 64-, New York, September. () Verilog-AMS Language Reference Manual, Open Verilog International, Los Gatos, Version..