Digital Load Share Controller Design of Paralleled Phase-Shifted Full-Bridge Converters Referencing the Highest Current

Transcription

1 Digital Loa Share Controller Design of Parallele Phase-Shifte Full-Brige Converters Referencing the Highest Current Hyun-Wook Seong, Je-Hyung Cho, Gun-Woo Moon, an Myung-Joong Youn Department of Electrical Engineering, KAIST Guseong-ong, Yuseong-gu, Daegeon, Republic of Korea, Abstract -- For a high power eman an N+1 reunancy system, this paper presents a igital loa share (LS) controller esign an its implementation for parallele phase-shifte fullbrige converters (PSFBC) use in istribute power systems. By aopting the igital control strategy, separately use ICs for both PSFBC an LS control functions in the analog system can be merge into a cost-effective igital controller. To compensate an stabilie PSFBC an LS loops with the irect igital esign approaches, a small-signal moel of the overall system is erive in the iscrete-time omain successively. Then, the steay-state an ynamic loa sharing performances are also investigate. Experimental results from two ientical 1.2 kw parallele PSFBC moules are presente to verify the propose work. Inex Terms Digital Control, Micro-Controller Unit (MCU), Loa Share (LS), an Phase-Shifte Full-Brige Converter (PSFBC). I. INTRODUCTION Distribute power systems such as server an network systems nee the high-current capacity, high efficiency, high maintainability, high reliability, etc [1]. To meet these requirements, the parallele phase-shifte full-brige converter (PSFBC) with an equally istribute loa current will be one of the most suitable caniates especially in high power applications. By sharing the loa current equally in each moularie PSFBC, the system can maximie reliability, improve the operational reunancy, an reuce cost of maintenance [2]. However, separate ICs for PSFBC control an loa share (LS) control shoul be utilie. Recently, igitally controlle DC-DC converters seem to be of growing interest in many inustries ue to the highspee computing processor an variously provie peripherals such as PWM moules, A/D converter (ADC) moules, an several external interfaces. Since most of micro-controller units (MCU) or igital signal processors (DSP) offer the sufficient number of PWM an ADC moules, it is feasible to implement the voltage-moe control of the PSFBC an its LS control simultaneously with one MCU. Moreover, easy moifications an the real-time monitoring of control parameters can lea to ease of the implementation an the reuction of the evelopment time. The previous efforts to equalie the moules inuctor currents are presente in the literatures [3]-[6]. Among all these control methos, the active LS control metho, with a loa share bus carrying reference current signal, is more accurate than the passive roop metho [7]. However, not only iscrete-time omain analysis for the active LS control metho but also the moularie PSFBC as the parallele DC-DC converter have not been introuce so far. Therefore, to cope with a high power eman an N+1 reunancy system while achieving an accurate current balance, the igitally controlle PSFBC using active LS control metho is presente in this paper. Prior to esign a igital LS controller, the voltage-moe controller esign of PSFBC is escribe in section II. In G (s) QA QC ILo Llkg n:1 LO K C SRB CO RO VO DLS V S QB QD SRA K V LS Bus DRIVER DRIVER ADuM eff PWM u[n] G c() S/H ADC S/H ADC ADC S/H vo[n] IO[n] e[n] uls[n] els[n] G LS() ILS[n] ZOH vref MCU Fig. 1. Digital LS control block of one parallele PSFBC /1/$ IEEE 796

2 section III, base on the esigne PSFBC igital controller, the small-signal moel of the LS loop in the iscrete-time omain is erive an then compensate with the stability an ynamic issue. After that, the experimental results from two ientical 1.2 kw parallele PSFBC moules are presente in section IV. Then, section V reaches a conclusion. II. DIGITAL VOLTAGE-MODE CONTROL OF PHASE-SHIFTED FULL-BRIDGE CONVERTER Fig. 1 escribes the igital LS control block iagram of the moularie PSFBC. It consists of both an inner voltagemoe PSFBC control loop an an outer LS control loop employing an LS ioe, D LS. The effective uty-to-output transfer function of the PSFBC, G (s), can be erive from the average small-signal moel consiering the change of the uty ratio cause by the output inuctor current I LO an the input voltage V S [8]. It can be expresse as (1) which is well presente in [8], [9]. v G () s nv O S 2 1 R 1 R O O LC eff s s RC O O L O LC O O R O 1 ( ) (1 ) 2 where R 4n Llkg f. L S lkg an f S are enote by a transformer leakage inuctor an the switching frequency respectively. By consiering both the sample-an-hol (S/H) effect an the computation time-elay, the iscrete-time transfer function of PSFBC can be expresse as (2). That is, G () contains the impulse sampler, the ero-orer hol (ZOH), an the time elay function le from one-cycle elaye igital control. (1) sts 1e st G() Ζ{ e G()} s (2) s Z{*} enotes -transformation of *, where T S an T inicate the sampling perio an the computation time-elay respectively. Thus, the voltage feeback control loop of the PSFBC, T V (), can be erive as (3) incluing voltage sensing gain K V an the PSFBC controller G C (). TV() KV G() GC() (3) Fig. 2 shows the boe plots of the iscrete-time voltagemoe controlle PSFBC system using the inicate parameters on it, where the close loop banwith is set at 7.5kH with a phase margin of 6. un [] ( 1)( 2)( 3) GC() K (4) P 2 en [] ( 1) The PSFBC controller G C () expresse in (4) is esigne as 1-integrator for the infinite DC gain, 2-high frequency pole so as to ensure the maximum phase margin, an 3-ero which compensates the phase elays ue to the 2-pole in G () an 1-integrator in G C (). Besies, extra phase elays ue to ZOH an T inclue in G () are consiere for the esign accuracy. Fig. 3 shows the measure frequency response of T V () which agrees quite well with that shown in Fig. 2 except for a further reuce phase margin ue to non-ieal evices in the real system. Hence, it can emonstrate the valiity of the esigne G C (). Although the form an parameters of G C () can be change accoring to the requirements of the application, in 8 6 TV()_phase -45 Magnitue (B) Magnitue (B) TV()_mag Phase (eg) Frequency (H) Phase (eg) G() GC() TV()_phase Fig. 3. Measure frequency response of T V (). -54 Frequency (H) Fig. 2. Boe plots of the iscrete-time voltage-moe controlle PSFBC system (G (), G C (), an T V ()). Fig. 4. Experimental waveform of the ynamic loa response. 797

3 (a) (b) Fig. 5. Small-signal moel of two parallele PSFBCs using the output impeance (a) LS moel an (b) Thevenin equivalent LS moel. this case, the values in (4) can impose the limitation on the output-voltage eviation within 6mV, i.e. 5% of V O with a.25a/μsec slew rate, uring the ynamic loa transient from 5% to 1% output current as shown in Fig. 4. Base on the esigne PSFBC controller G C () an its experimental results, the igital LS controller G LS () esign will be presente in the following section. III. DIGITAL LOAD SHARE CONTROL OF PSFBC REFERENCING THE HIGHEST CURRENT To erive the LS control loop, the small-signal moel of two parallele PSFBCs using the output impeance concept is escribe in Fig. 5(a). Accoring to the concept of output impeance for LS system presente in [11] an [12], the PSFBC can be substitute by a controlle voltage source an the open-loop output impeance Z OL (). The Thevenin equivalent transformation facilitates the LS system to be simpler as shown in Fig. 5(b), which is consist of the moifie controlle voltage source, the close-loop output impeance Z CL (), the output current sensing gain K C, an the LS controller G LS (). Z OL () an Z CL () for the PSFBC can be expresse as (5) an (6) respectively by using the step- invariant iscretiation metho. st 1e S slo ZOL () Z{( )( s 2 LO slc O O s 1 R O (5) 1 1 )} 2 LO 2 1 sroco 1 ( slc O O s 1) R 2 O srlc O O O sl O R O R ZOL () ZCL() 1 TV ( ) (6) Fig. 6 epicts i-v characteristics of LS system of which current imbalance is epenant on Z CLn () an v On. Since Z CL () is the fixe circuit parameter an cannot be ajuste, the LS controller shoul moulate the output voltage of each moule from v On to v On. That is, in the active current sharing metho using the LS ioe D LS, the parallele moule having the highest current gives the conuction of D LS while the LS ioes of the other moules are reverse-biase. It means only one master unit communicates on the LS bus an the other slave moules ajust the reference voltage accoringly by using the error signal between their current sensing signals an the LS bus signal to correct the current imbalance. Because of no LS error from the master position, the LS feeback control loop T LS () in the slave position is a matter of concern. Thus, the LS feeback control loop T LS () can be erive as (7). KC TV() 1 TLS () GLS () KV 1 TV( ) ZCL( ) (7) KC TV() GLS () K Z () V OL Fig. 6. i-v characteristics of the LS system. 798

4 Fig. 7 shows the boe plots of the iscrete-time LS systems, where the current sensing gain K C is.77 an other parameters are inicate in Fig. 2. As shown in Fig. 7(a), the uncompensate LS loop also appears an integrator inclue in T V () by canceling of 1+T V () as note in (7). It provies that the steay-state LS error ΔI O can be eliminate by (8) erive from Fig. 5. Vref 2 Vref 1 TLS () IO (8) KCGLS() 1 TLS() That is, since T LS () has an infinite DC gain on account of an integrator, ΔI O epens on the G LS () regarless of T LS (). Magnitue (B) Phase (eg) (a) Uncompensate LS loop G LS () T LS () Therefore, if G LS () also inclues an integrator of which DC gain is infinite, no steay-state LS error can be ensure. The LS controller can be esigne from satisfying this prerequisite. Moreover, the LS controller shoul inclue 1- low frequency ero to utilie its phase boost an 1-pole to alleviate the high frequency ripples as follows: uls[] n ( LS1) GLS () K, (9) LS els[] n ( 1)( pls1) where K LS =.797, LS1 =.9993 (9H) an p LS1 =.9349 (91H). Equation (9) is the esigne LS controller base on the above-mentione conitions. It offers that the close loop banwith is allocate at 3H with a phase margin of 69 as note in Fig. 7(b). Although the banwith of T LS () can be ajuste by the LS control gain K LS, its upper bounary for the stability shoul be limite to the banwith of T V (). It is reason for remarkable phase elays le from the S/H effect an the computation time-elay T ue to the igital system. Moreover, T LS () shoul be low enough in the banwith of T V () to avoi interactions between T LS () an T V (). Fig. 8 shows the simulate ynamic responses of the PSFBC LS control accoring to K LS variations. Since any parallele moule can be a master moule uring the LS control an I O_slave continuously tracks I O_master so that the LS error is converge to ero, the step sie can be efine as (I O_master -I O_slave ) generally. As can be seen in Fig. 8, as K LS increases in orer to exten the banwith of T LS (), the settling time is shortene while the phase margin is ecrease. If the banwith of T LS () is close to that of T V (), the LS feeback loop will be unstable eventually. Therefore, esigners shoul take the trae-off relations between the stability an fast ynamics into account. In this case, for example, the banwith of T LS () is set at 3H to limit the current overshoot an unershoot within 5% of (I O_master -I O_slave ). Accoringly, it can achieve a settling time of 2.5ms G LS () Uncompensate LS loop T LS () Frequency (H) (b) Fig. 7. Boe plots of the iscrete-time PSFBC LS system (a) 1/Z CL (), T V ()/(1+T V ()), an uncompensate LS loop an (b) G LS () an T LS (). I O_master I O_slave Line Banwith (H) PM( ) KLS(1-3 ) Overshoot (%) Settling time within 3% (ms) Time (ms) Fig. 8. Simulate ynamic responses of the PSFBC LS control. 799

5 IV. EXPERIMENTAL RESULTS To verify the analysis an valiity of the esigne igital LS controller, two ientical 1.2kW PSFBC moules have been built, where the system an esign parameters are note in Table I. The esigne igital controllers, i.e. G C () an G LS (), of each moule are implemente on a TMS32F2827. It offers that 6MH system clock, 8 channels for PWM, 13 channels for ADC, three 32-bit CPU timers, an so on. Table II illustrates the steay-state LS errors accoring to the total loa current variations. In spite of the aitional phase elays ue to the igitally controlle-loop, it can be conclue that the steay-state LS errors are nearly eliminate by an integrator in the LS loop as analye above. Fig. 9 shows the experimental waveforms for ynamic response of output currents from 5A to 1A an vice versa. This waveform exhibits goo loa sharing accuracy at both the steay-state an the ynamic loa transients. Moreover, since the output-voltage overshoot an unershoot are limite within 6mV, 5% of output voltage 12V, the esigne LS controller oes not affect the voltage-moe controlle loop. Consequently, the experimental results agree well with the esign an analysis. TABLE I SYSTEM AND DESIGN PARAMETERS Input Voltage, V S Output Voltage, V O Maximum Output Power of Each Moule, P O_max. Switching Frequency, f S Computation Time-Delay, T PSFBC 4V 12V 1.2kW 85kH 1/85kH Turn-Ratio, N P : N S 24 : 1 Leakage Inuctor, L lkg Output Inuctor, L O 12μH 1.2μH Output Capacitors, C O 33μF x 5 Voltage Sensing Gain, K V.392 Current Sensing Gain, K C.77 TABLE II STEADY-STATE LS PERFORMANCE I O1 (A) I O2 (A) I O /2 (A) ΔI O (A) ΔI O /(I O /2) (%) Fig. 9. Experimental waveforms (5A 1A 5A). V. CONCLUSION This paper presente the igital LS controller esign of parallele PSFBC moules for the istribute power system. The active LS control metho using a LS bus with ioes was implemente in this system. The small-signal moel for the parallele PSFBC LS system incluing the S/H effect an computation elays was erive in the iscrete-time omain. For the compensation, 3-pole an 3-ero PSFBC voltagemoe controller an 2-pole an 1-ero LS controller containing an integrator simultaneously was aopte. Then, the steay-state an ynamic LS performances were investigate. By experimental results, ignorable steay-state errors, no affection to the voltage-moe control loop, an fast ynamic responses were achieve with a cost-effective igital controller. REFERENCES [1] M. Joran, UC397 loa share IC simplifies parallel power supply esign, Unitroe Application Note U-129. [2] Stefan Huth, DC/DC-Converters in Parallel Operation with Digital Loa Distribution Control, IEEE ISIE 96 proc., vol. 2, June 1996, pp [3] Shiguo Luo, Zhihong Ye, Ray-Lee Lin, an F.C. Lee, A Classification an Evaluation of Paralleling Methos for Power Supply Moules, IEEE PESC 99 proc., vol. 2, June 1999, pp [4] B.T. Irving an M.M. Jovanovic, Analysis, Design an Performance Evaluation of Droop Current-Sharing Metho, IEEE APEC proc., vol. 1, Feb. 2, pp [5] V.J. Thottuvelil an G.C. Verghese, Stability Analysis of Parallel DC/DC Converters with Active Current Sharing, IEEE PESC 96 proc., vol. 2, June 1996, pp [6] R.H. Wu, T. Kohama, Y. Koera, T. Ninomia, an F. Ihara, Loa- Current-Sharing Control for Parallel Operation of DC-to-DC Converters, IEEE PESC 93 proc., June 1993, pp [7] Y.Panov, J. Rajagopalan, an F.C. Lee, Analysis an Design of N Parallele DC-DC Converters with Master-Slave Current-Sharing Control, IEEE APEC 97 proc., vol. 1, Feb. 1997, pp [8] Vlatko Vlatkovic, Juan A. Sabate, Raymon B. Riley, Fre C. Lee, an Bo H. Cho, Small-Signal Analysis of the Phase-Shifte PWM Converter, IEEE transactions on power electronics, vol. 7, No. 1, Jan. 1992, pp [9] Jeong-Gyu Lim an Se-Kyo Chung, Digital Control of Phase-Shifte Full-Brige PWM Converter, Journal of power electronics, vol. 8, no. 3, July, 28, pp

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