A Single-phase Current Source PV Inverter with Power Decoupling Capability using an Active Buffer

Transcription

1 A Single-phase urrent Source P nverter with Power Decoupling apability using an Active Buffer Yoshiya Ohnuma Koji Orikawa Jun-ichi toh Nagaoka University of Technology Kamitomioka-cho Nagaoka ity Niigata, Japan ohnuma@npe.co.jp, orikawa@vos.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp Abstract This paper proposes a new circuit configuration an a control scheme for a single-phase current source inverter with a power ecoupling circuit which is calle as the active buffer. The propose inverter achieves low-d-input voltage ripple an also provies sinusoial current that can achieve unity power factor, without large passive components in D bus such as smoothing inuctors an electrolytic capacitors, which are conventionally require in orer to ecouple the power pulsation cause by single-phase power source. n this paper, the funamental operations of the propose inverter are emonstrate experimentally. From the experimental results, the input voltage ripple is 8.87% an the output current THD is 4.4%. n aition, the output power factor over of 99% an a maximum efficiency of 94.9% are obtaine. Finally, it is confirme that the maximum power ensity of the conventional circuit an the propose circuit are.75 kw/l at the switching frequency 70 khz an 4.86 kw/l at the switching frequency 80 khz, respectively.. NTRODUTON n recent years, solar power generation systems are wiely use in response to the fast grows an high emans of electrical energy. Due to the environmental avantages, solar power generation systems are often applie in the housing an inustries areas. One of key components of the solar power systems is the photovoltaic (P) inverter [1]-[8]. The P inverters are require to achieve the maximum power point tracking (MPPT) function an to provie a sinusoial waveform that can achieve unity power factor into the gri. n orer to satisfy the requirements, many single phase circuits with a power ecoupling circuit has been propose, which can be classifie as (i) passive power ecoupling circuits with passive components an (ii) active ecoupling circuits with semiconuctor switches [10]-[13]. One of the most popular power ecoupling circuits is twostage converters, which compose of a boost chopper with a semiconuctor switch an a voltage source inverter as shown in Fig. 1, are generally use [1]. However, the converter requires two large inuctors (the boost inuctor an the interconnecte inuctor) which inherently increasing the size of the inverter. n aition, a large electrolytic capacitor is necessary in orer to compensate the power pulsation when the inverters are connecte to the single-phase gri because the power is fluctuating at twice of the gri frequency. n a high temperature operating environment, the use of the electrolytic capacitor is not preferre in terms of the lifetime an the power ensity of the converter because the lifetime of electrolytic capacitor ecreases ue to frequent charge/ ischarge operations an the long hours of high temperature operation. n Ref. [11], a buck converter with a power ecoupling circuit has been propose. An avantage of this converter is that the number of semiconuctor switch is only one in the power ecoupling circuit. However, a large inuctor is require in orer to achieve sinusoial current that can achieve unity power factor. n Ref. [1]-[13], the power ecoupling circuits with soft-switching technique has been propose. At the resonance point, unity power factor can be achieve perfectly. However, the operation of the circuit epens on the conition of a loa. Moreover, the maximum value of the circulation current increases. As a result, applications of the circuit are limite an the conuction loss increases. On the other han, matrix converters with a power ecoupling capability have been propose [14]-[15]. n those converters, high efficiency can be achieve because the number of switches where the current flows is reuce an the smoothing capacitor is not require at a D link part. Nowaays, the current source inverter allows great features that the inverter can achieve both the MPPT function an the gri-connecte control by one converter. However, a large smoothing inuctor is require to ecouple the power pulsation cause by the single-phase power generation. Therefore, conventional circuits with a power ecoupling capability have problems that the size an cost increase epening on the number of passive components, an also the power ensity is low. This paper proposes a new single-stage current source inverter with a power ecoupling circuit, which is calle as the active buffer [16], to overcome those rawbacks. The propose inverter is constructe base on a current source

2 inverter with an active buffer. The buffer circuit consists of one switch, two ioes an one small capacitor. Therefore, the size an the number of passive components in the propose circuit can be reuce compare with that of conventional circuits. As a result, the propose circuit can achieve high power ensity. The power pulsation with twice the gri frequency is ecouple by the active buffer capacitor. Therefore, the propose inverter can control the variable input-d-voltage to achieve the MPPT an provies a sinusoial current into the gri without the large inuctor. The values of the active buffer capacitor can be reuce by controlling the capacitor voltage, allowing for the use of small capacitors such as film capacitors or laminate ceramic capacitors. Other passive components are require at the input an output filters in the propose inverter in orer to eliminate the switching ripple. n aition, ioes that are connecte in series to the switches in the inverter are not require in the propose inverter. Note that, the propose inverter is constraine at the operation with unity power factor. The funamental operations of the propose inverter are first emonstrate an explaine. Then, the principle of the controls strategy is illustrate. Lastly, the valiity of the propose controls is confirme in experimental.. RUT TOPOLOGY A. ircuit onfiguration Fig. 1 shows one of the conventional P inverter. The conventional P inverter, which consists of the boost chopper an the voltage source inverter, is use wiely. The inverter requires the two huge inuctors; the boost inuctor L c an the interconnecte inuctor L ac. Aitionally, a huge electrolytic capacitor is also require in orer to compensates the power pulsation with a twice of the gri frequency when the inverter is connecte to the single-phase gri. Due to the above reasons, ownsizing for this converter becomes ifficult an challenge. Fig. presents the circuit structure of the propose converter. The propose converter is constructe base on the current source inverter with an active buffer circuit. The propose converter achieves the D-voltage control for the MPPT, operation on the inverter for an interconnection an power pulsation with a small capacity. These functions are realize by the combine controls between the current source inverter an the active buffer circuit. The low-voltage ripples are obtaine except a switching ripple even when a small smoothing inuctor L c is use. Moreover, the ioes that are require in the current source inverter are not necessary to achieve unity power factor. This is because the free-wheeling moe is operate in the active buffer. Aitionally, recovery of the ioes oes not occur because there is no path to flow the current on the boy-ioes of the MOSFETs. B. Operation moes Fig. 3 illustrates the switching pattern of the propose inverter when the gri voltage is the positive. The current pathway oes not occur from the gri to the active buffer capacitor because the active buffer capacitor voltage must be Figure 1. onventional voltage inverter with a boot chopper. Figure. Propose P inverter. higher than the gri voltage. Therefore, assuming that the input is a continuous current source N, the current pathways of the propose inverter have four moes base on the switching pattern. n the moe 1, the input power (P power) is irectly supplie to the single-phase gri. The buffer power is controlle by the moe an 3. n the moe, the current N flows into the capacitor in the active buffer circuit. n contrast, in moe 3, the buffer capacitor is ischarge through the S 0. The moe 4 is a current freewheeling moe for the input current. Thus, the propose inverter performs both functions of a boost chopper (moe 1, moe 4) an the buffering function for the power pulsation compensation (moe, moe 3). The switches S 3 an S 4 are not switche except the polarity of the gri is reverse. Thus, the power control with PWM is hel with combinations of S 0 an S 1, or S 0 an S. t means that the losses of the inverter are ramatically reuce.. ONTROL STRATEGY Fig. 4 epicts the principle of power pulsation compensation. When both the gri voltage v ac an the output current i ac have sinusoial unity power factor, the instantaneous output power p out is expresse as follows; p out = 1 = sin ( ωt) 1 cos ( ωt ) (1), where is the peak amplitue of gri voltage, is the peak amplitue of the output current, an ω is the gri angular frequency. Base on (1), the power pulsation with twice the gri angular frequency appears in the output power. n orer to

3 (a) Moe 1. (b) Moe. (c) Moe 3. () Moe 4. Figure 3. Operation moes of the propose inverter. Figure 4. ompensation principle of power pulsation. ecouple the power pulsation, the buffer circuit instantaneous power p buf is require, as given by p buf 1 = cos( ωt ) (), where the polarity of p buf is efine as positive when the buffer capacitor ischarges. The mean power of the buffer circuit is zero because the buffer capacitor absorbs only the power pulsation. onsequently, the instantaneous input power p in will be constant: 1 p = = in N N (3).

4 The propose inverter is controlle in four moes as shown in Fig. 3. Therefore, assuming that the input current N is continuous, the inverter current i inv an the capacitor current i c can be expresse as iinv = ic moe1 moe moe3 moe3 N (4), where moe1 through moe4 are the uty ratios of the each moe. The uty ratios are constraine by the continuous current ( N ), as follows: + + =1 (5). moe1 + moe moe3 moe4 n orer to obtain a sinusoial output current, i inv is constraine as (6). The capacitor current i c shoul be controlle as (7), base on (), in orer to compensate the power pulsation. i i inv c = sin( ωt) (6) = cos(ωt) (7) v c Therefore, moe1, moe an moe3 are controlle by the following equations: moe1 = sin(ω t) moe3 (8), N moe + moe3 = = cos( ωt )(9), v where is efine as moe + moe3. When the capacitor current i c is positive, i.e., when is positive, moe 3 is selecte in orer to ischarge the capacitor. n contrast, when the capacitor current i c is negative, i.e., when is negative, moe is selecte. The ratio of over N can be ob taine as follows base on (3), an substituting (10) into (8) an (9). N = (10) N Therefore, moe1, moe an moe3 are obtaine by (11) an (1) by using (8), (9) an (10). * N moe1= sin( t) Acp moe3 c N ω (11) moe moe3 = 0 = 0,,,, (1) where N * is the reference value of the input D voltage. Note that N * has to satisfy (13) because all uty commans shoul be positive value an satisfy (5). * Acp N (13) From (13), the maximum of the input D voltage is limite by half of the of single phase maximum voltage. Fig. 5 shows a control block iagram of the propose circuit. Base on (8), (9) an (10), the uty ratio commans are calculate from the etecte gri voltage v ac, capacitor voltage v c, input current i in, comman of the input voltage * N, minimum voltage of the active buffer capacitor min, an capacitance of the active buffer capacitor c. Table presents the pulse transform table for the generation of gate pulses. The gate pulses are given by comparing the pulse transform tables with a triangle carrier. Note that the capacitor voltage is controlle by a P controller.. EXPERMENTAL RESULTS n orer to emonstrate the valiity of the propose inverter, a 400-W prototype circuit has been teste. n this paper, the power supplies are connecte at the input an output of the propose circuit for the simplicity since this paper aims to confirm a funamental operation. Moreover, the input an output sies are controlle as the current source moe an voltage source moe with assuming that the gri is 100, respectively. The input an output filters are consiste of a 1-mH (%X L = 1.5%) inuctor an a 3.3-μF capacitor. A 50-μF film capacitor is use for the active buffer capacitor. n the experiment, the gri voltage is 100 rms, the input voltage comman is set to 70, an a carrier frequency is 0 khz. Fig. 6 shows the experimental waveforms of the propose circuit. Fig. 6 (a) illustrates the input an output waveforms when the prototype is operate with the rate power. From the experimental results, the output power factor is 99.9%, an the total harmonics istortion (THD) of output current is 4.4%. Simultaneously, D voltage is controlle accoring to the reference value of 70. Moreover, the voltage ripple is 9.33%. Fig. 6 (b) shows the capacitor voltage, where the capacitor voltage is fluctuating with twice of the gri frequency. Furthermore, the amplitue of the voltage fluctuation matches to theoretical value. Hence, it is confirme that the propose circuit achieves the power pulsation compensation with active buffer.

5 min pn ω c { sin(θ ) 1} Figure 5. ontrol block iagram. TABLE. SWTHNG TABLE. (a) nput an output waveform. Fig. 7 presents the efficiency an power factor characteristics subjects to the output power. The output power factor is 99% at the rating power an the maximum efficiency is 94.9%. Aitionally, high efficiency an power factor are confirme achieving within a wie range of output power. Fig. 8 shows the harmonics analysis results of the propose circuit. The THD of the output current is less than 5% within the output power from 100 W to 400 W. From this result, it is clear that the P interconnection with the propose circuit can be achieve. Besies, D voltage ripple is suppresse to less than 1% within the output power from 100 W to 400 W. This is attribute that the power pulsation are compensate by the active buffer circuit. (b) apacitor voltage an output waveforms. Figure 6. Experimental waveforms.. OMPARSON TO ONENTONAL BOOST HOPPER n this section, a power ensity of the propose circuit is compare with the conventional boost chopper in orer to

6 clarify a superiority of the circuit. Table provies the esign specifications of the prototype. n this consieration, a P with a rate voltage of 100 an a gri of 00 are assume. A. ircuit Design an alculation of olume 1) Switching Devices: S an D Table presents the evice information of the prototype. The basis of selection for each component such as a switches an ioes is in common. Thus, the same components are use in both the propose circuit an conventional boost chopper. n the selection of the MOSFETs, the switches S 0, S 1, S 3, which can achieve high spee switching, an the switch S, which has a low on resistance are selecte. Similarly, the fast recovery ioes D 0 an D 1 are selecte. Figure. 7. Efficiency an output A power factor. ) D Link apacitor: c n the conventional circuit, the average capacitor voltage c is booste up to 350. Besies, the allowable voltage ripple is set to.5% where the voltage ripple is efine as (14) with using a fluctuation range of the voltage Δ c. rip Δ = (14) On the other han, the propose converter has proven able to control the capacitor voltage significantly. The minimum voltage an maximum voltage of the capacitor are set to 8 to 430 respectively. The require lowest capacitance is calculate from (15). Figure. 8. THD of output current an input voltage ripple. TABLE. SPEFATONS OF THE PROTOTYPE ONERTER. P = (15) rip OUT c 4πf A Besies, the current ripple ripple_c, which flows into the capacitor, is obtaine by TABLE. DEE NFORMATON OF PROTOTYPE ONERTER. P = OUT ripple _ c (16) Note that, consiering the current ripple from the boost chopper an inverter, twice the ripple current, which is calculate by (16), is use as a selecte value. The electrolytic capacitor is chosen as a D link capacitor of the boost chopper because the 60 μf is neee in orer to confirm the esign specifications. n contrast, a laminate ceramic capacitor can be use because the calculate value with (15) is 30 μf. Note that, the D link capacitor is not affecte by the switching frequency. Besies, the volume of the capacitor is erive from capacitors in the marketplace. 3) nuctor: L c, L ac Each inuctor is esigne base on the ripple ratio of inuctor current. The ripple ratio of the boost inuctor an the interconnecte inuctor are set as 10% an 5%, respectively. Note that the ripple ratio is efine by (17) using the ripple current Δ L an the average current of inuctors L. rip Δ L L = (17) L n case of the boost inuctor L c, the require inuctance is obtaine by (18). L ( ) N N c = (18) LripL f sw

7 where f sw is the switching frequency. Here, volumes of the inuctors are evaluate using Area prouct concept [17]. 4) Filter: L f, ac, c The stanarize filter inuctance L f at the switching frequency of 10 khz is set to 1% of the output power capacity. The filter inuctance L f is etermine so that the ripple current is same accoring to the switching frequency. alues of ac an c are selecte so that the cut-off frequency is one-tenth of the switching frequency. 5) ooling fin The volume of the cooling fin is estimate by SP base on the power loss that is calculate from a simulation [18]. Here, natural air cooling is consiere as the cooling metho. n this paper, the SP value is 3, the volume of the cooling fin is calculate so that the chip temperature is below then 15 eg. when the ambient temperature is 45 eg... OMPAROSON OF POWER LOSS This chapter shows the loss analysis using the circuit simulator Piece-wise Linear Electrical ircuit Simulation (PLES). Fig. 9 shows the efficiencies of the conventional circuit an the propose circuit when the switching frequency is 10 khz an 100 khz, respectively. When the switching frequency is 10 khz, in the propose circuit, the conuction loss of the ioes is ominant in the total loss because the number of employe ioes is two. The total loss increases ue to the increasing of the switching loss when the switching frequency is 100 khz.. OMPARSON OF OLUMES Fig. 10 shows pareto-front curves, which shows the relationship between the power ensity an the efficiency accoring to variation of the switching frequency. As a result, it is confirme that the maximum power ensity of the conventional circuit an the propose circuit is.75 kw/l at the switching frequency 70 khz an 4.86 kw/l at the switching frequency 80 khz, respectively. n aition, the propose converter can achieve higher efficiency at high switching frequency comparing with that to the conventional circuit. Fig. 11 shows ratios of each volume at the maximum power ensity. As a result, it can be seen that the volume of the propose circuit is reuce by approximately 40% compare with that to the conventional circuit. n the conventional circuit, a D link capacitor an an interconnecte inuctor are the cause of the large size. Especially, the volume of the D link capacitor cannot be ecrease accoring to the increasing of the switching frequency. On the other han, the volume of the buffer capacitor in the propose circuit can be ecrease accoring to the increasing of the switching frequency.. ONLUSON This paper proposes a new circuit topology an a control scheme for a single-phase current source inverter with a Figure 9. omparison of loss analysis. Figure. 10. Pareto-front curves. Figure. 11. omparison of converter volumes. power ecoupling circuit which is calle as the active buffer. The propose inverter achieves low-d-input voltage ripple an also provies clear sinusoial current into the singlephase gri, without large passive components in the D bus, which are conventionally require in orer to ecouple the power pulsation cause by single-phase power source. n this paper, the funamental operations of the propose inverter are emonstrate experimentally. From the experimental results, the input voltage ripple is 8.87% an the output current THD is 4.4%. n aition, the output power factor over of 99% an the maximum efficiency of 94.9% are

8 obtaine. Finally, it is confirme that the maximum power ensity of the conventional circuit an the propose circuit coul be.75 kw/l at the switching frequency 70 khz an 4.86 kw/l at the switching frequency 80 khz, respectively. REFERENES [1] M. alais, J. Myrzik, T. Spoone, an. G. Ageliis, nverters for single-phase gri connecte photovoltaic systems-an overview, in Proc. 00 EEE 33r Annual Power Electronics Specialists onference, 00. pesc 0, vol., pp , 00. [] S. Kjaer an J. Peersen, A review of single-phase gri-connecte inverters for photo-voltaic moules, EEE Trans. n. Ap., vol. 41, no. 5, pp , 005. [3] D. ao, S. Jiang, an X. Yu, Low ost Semi-Z-source nverter for Single-Phase Photo-voltaic Systems, EEE Trans. Power Electron., vol. 6, no. 1, pp , 011. [4] S. Harb, H. Hu, N. Kutkut,. Batarseh, an Z. J. Shen, A three-port Photovoltaic (P) micro-inverter with power ecoupling capability, in 011 Twenty-Sixth Annual EEE Applie Power Electronics onference an Exposition (APE), no., pp , 011. [5] Z. hao, H. Xiangning, an Z. Dean, Design an control of a novel moule integrate converter with power pulsation ecoupling for photovoltaic system, in Proc. nternational onference on Electrical Machines an Systems, EMS 008, pp , 008. [6] T. Shimizu, K. Waa, an N. Nakamura, Flyback-Type Single-Phase Utility nteractive nverter With Power Pulsation Decoupling on the D nput for an A Photovoltaic Moule System, EEE Trans. Power Electron., vol. 1, no. 5, pp , 006. [7] B. Singh, B. N. Singh, A. hanra, K. Al-Haa, A. Paney an D. P. Kothari, A review of single-phase improve power quality A- D converters, EEE Trans. n. Electron., vol. 50, No. 5, pp , 003. [8] Q. Li an P. Wolfs, A Review of the Single Phase Photovoltaic Moule ntegrate onverter Topologies With Three Different D Link onfiguration, EEE Trans. Power Electron., vol. 3, no. 3, pp , 008. [9] H. Hu, S. Harb, N. Kutkut,. Batarseh, an Z. Shen, A review of power ecoupling techniques for micro-inverters with three ifferent ecoupling capacitor locations in P systems, EEE Trans. Power Electron., vol. PP, no. 99, p. 1, 01. [10] J.. rebier, B. Revol, an J. P. Ferrieux, Boost-chopper-erive PF rectifiers: interest an reality, EEE Trans. n. Elec., vol. 5, no. 1, pp , 005. [11] L. Huber, L. Gang, an M. M. Jovanovic, Design-oriente analysis an performance evaluation of buck PF front en, EEE Trans. Power Electron., vol. 5, no. 1, pp , 010. [1] G. Moschopoulos, P. K. Jain, A Novel Single-Phase Soft-Switchie Rectifier With Unity Power Factor an Minimal omponent ount, EEE Trans. n. Electron., vol. 51, No. 3, pp , 004. [13]. Licitra, L. Malesani, G. Spiazzi, P. Tenti an A. Testa, Singleene soft-switching electronic ballast with unity power factor, EEE Trans. n. Ap., vol. 9, no., pp , [14] M. Saito, T. Takeshita, an N. Matsui, A single to three phase matrix converter with a power ecoupling capability, in Proc. 004 EEE 35th Annual Power Electronics Specialists onference, 004. PES 04, 004, pp [15] M. Saito an N. Matsui: A Single- to Three-phase Matrix onverter for a ector-ontrolle nuction Motor", EEE nustry Applications Society Annual Meeting, 008., AS '08, pp. 1-6, (008) [16] Y. Ohnuma an J.-ichi toh, A control metho for a single-to-threephase power con-verter with an active buffer an a charge circuit, Proc. EEE Energy onversion on-gress an Exposition EE 010, pp , 010. [17]. W. T. McLyman, Transformer an nuctor Design Hanbook, 3 r E., New York, NY: Marcel Dekker, 004. [18] J. W. Kolar, J Biela an J, Minibock: Exploring the Pareto Front of Multi Objectice Single-Phase PF Rectifier Design Optimization -99.% Efficiency vs. 7kW/m 3 Power Density,PEM 009- hina,(009)