One-Inductor Single-stage Differential Boost Inverter Operated in Discontinuous Current Mode for Single-Phase Grid-Tied Photovoltaic System

Transcription

1 One-Inuctor gle-stage Differential Boost Inverter Operate Discontuous Current Moe for gle-phase Gri-Tie Photovoltaic ystem Ayato agehashi, e Hoai Nam an Jun-ichi Itoh Department of Electrical Engeerg Nagaoka University of Technology, NUT Nagaoka, Niigata, Japan sagehashi@stn.nagaokaut.ac.jp, lehoaam@stn.nagaokaut.ac.jp, itoh@vos.nagaokaut.ac.jp Abstract In this paper, a novel sgle-stage boost verter usg one uctor is propose for a gri-tie photovoltaic (P) verter. The propose verter shares one uctor with two boost converters by utilizg iscontuous current moe (DCM). The output voltage is controlle by the ifferential voltage between boost converters. Usg this topology, the neutral pot of the gri can be connecte to a termal of the solar panel. As a results, common-moe noise can be suppresse. The operation of the propose verter is confirme with 1-W prototype with a DC put voltage of 1 an an AC output voltage of 1. The output current THD is 1.4%. Keywors DC/AC converter, Discontuous current moe, Micro-verter I. INTRODUCTION In recent years, P systems have been wiely use as an alternative power supply from natural energy. In such system, the P verter is require for terconnectg the gri an the P system. In particular, the P verter is strongly require to mimize an achieve high efficiency[1]-[5]. The generate power of the P system epens heavily on the weather conition an the solar raiation. Therefore, the conventional P systems where only one verter is connecte with several solar panels, if only one solar panel is shae by clous or ra, the output power of the whole system worsens. In orer to solve this problem, a micro-verter has been propose as an alternative metho for P verter [6]-[1]. In particular, each micro-verters are connecte to each solar panels separately. Therefore, the generate power will be crease partial shaow conition because the generate power of each solar panel is controlle epenently. Consequently, problems on iviual solar panels oes not fluence heavily on the operation of the whole system. However, the mimization of the micro-verter is necessary terms of the stallation area orer to connect to each solar panel separately. One of the ma factors preventg the mimization of the micro-verter is the passive components, i.e. the uctor an the capacitor. In general, the P verter is compose of a boost converter an an verter. The boost converter is use to control the DC-lk voltage, whereas the verter converts the DC power to AC power. In this case, a high-voltage DC-lk capacitor is require with a large capacitance, which absorbs a power fluctuation cause by the sgle-phase gri. On the other han, the system volume of the DC/AC converter creases because an boost uctor of a boost converter an terconnecte uctors of an verter are necessary. On the other han, the sgle-stage boost verter for the DC/AC converters have been propose orer to unify the boost converter an the verter [11]-[15]. The sgle-stage boost verter can reuce the number of the switchg evices an the uctors. It is two uctors for the boost operation an four switchg evices compose two boost converter circuits. Therefore, the sgle-stage boost verter can be mimize ue to the reuction of circuit elements compare with the typical DC/AC topology. In aition, the leak current cause by the floatg capacitance between the solar panel an the groun is significantly reuce ue to the voltage fluctuation at the neutral pot is small between the solar panel an the gri. However, the sgle-stage boost verter still use two uctors. Consequently, the number of the uctor is necessary to further reuce orer to mimize the circuit volume. In this paper, a novel boost verter is propose orer to convert from DC to AC clug the boost operation usg only one small put uctor. First, the conventional two stage DC/AC converter for the P system, the conventional sglestage boost verter an the propose boost verter are explae. econly, the operation moes an switchg patterns of the propose boost verter is shown. Thir, the put uctor current control an the output capacitor voltage control are explae. In aition, the calculation metho of each uty ratio comman values for DCM is establishe. Fourth, the operation of the propose boost verter by simulation after the esign metho of the put uctor at the critical moe of DCM is confirme. Next, the losses of the switchg evices an uctors are compare between the conventional two stage DC/AC converter an the propose boost verter. Fally, the operation of the propose verter is confirme experiment. As a result, the conversion from DC

2 to AC is realize by the propose boost verter which reuces the number of uctors compare with the conventional twostage DC/AC converter an the conventional sgle-stage boost verter. II. DC/AC CONERTER TOPOOGY A. Conventional two-stage AC/DC converter Fig. 1 shows the conventional two stage DC/AC converter topology for the P verter. The conventional two stage DC/AC converter is compose the boost converter an the H- brige verter orer to convert from DC to AC. The DC lk voltage requires the higher voltage than the maximum gri voltage when the verter is connecte to the gri. Therefore, the large capacitor is necessary to connect between the boost converter an the verter when the put voltage is lower than the gri voltage. Aitionally, the boost uctor an the terconnecte uctors prevent orer to mimize the system. As a result, a number of passive components, switchg evices an the value of the capacitance are require to reuce orer to mimize the system of the conventional two stage DC/AC converter. a C c Fig. 1. Conventional two-stage DC/AC converter. a C a C b g b b g g g Cb B. Conventional sgle-stage boost verter Fig. shows the conventional sgle-stage ifferential boost verter. Two boost converters compose the conventional sgle-stage ifferential boost verter. This verter regulates the voltage of output sie capacitors an Cb to susoial waveform clug the offset voltage higher than the put voltage. In aition, the output current is controlle by potential ifferences of the output capacitors. Therefore, compare to the conventional two stage DC/AC converter, the conventional sgle-stage boost verter requires only four switches an two uctors. In this case, the total volume of the boost uctors of the sgle-stage boost verter is smaller than that of the conventional two stage DC/AC converter. However, it is necessary to further reuce the number of the uctors orer to mimize the system volume. C. Propose sgle-phase boost verter Fig. 3 shows the circuit iagram of the propose sglephase boost verter. In prciple, the propose boost verter is combe of two boost converter, requirg a switchg evice an two biirectional switches. Note that if only typical uniirectional switches are use, the propose boost verter requires more switchg evices compare with the conventional sgle-stage boost verter. On the other han, the propose boost verter is operate DCM. Consequently, the number of the put uctor is reuce to only one because the put uctor current is share for the voltage control of each output capacitor C a an C b. Hence, the converter size can be reuce. Furthermore, the number of the switchg evices of the propose verter can be reuce to only three if the biirectional switches can be employe with GaN-base monolithic biirectional switches, which has same on resistance as the uniirectional switches [16]. Fig. 4 shows the operation moe of the propose boost verter. The operation moe is shown only the output Fig.. Conventional sgle-stage ifferential boost verter. b a b a C a C b Cb Fig. 3. Propose sgle-stage ifferential boost verter. 1 1 (a) Moe I (b) Moe II 1 1 (c) Moe III () Moe I Fig. 4. Operation moe for each capacitor voltage control. g

3 capacitor C a cause by the operation moe of the output capacitor C b similarly. The output capacitor voltages are controlle similar to the boost operation an the step-own operation. The put uctor current is controlle to positive irection at Moe I an II perios. At Moe III an I, the put uctor current is controlle to negative irection orer to get the esire output capacitor voltage. In this operation moe, the boost verter operate the boost moe when the output current comman value is positive. The operation is the step-own moe when the other irection of the output current comman value. Furthermore, the susoial waveform of the output sie is realize by the ifferential voltage between output capacitor voltages an Cb which is controlle to verse phase. pacitor voltage control _avg * + _avg i out * + PI + i * i a * When i a *> DCM DCM When i a * Fig. 5. Control block for output capacitor voltage control III. CONTRO METHOD FOR BOOT INERTER Fig. 5 shows the voltage control block for the output capacitor C a the boost verter. The PI controller controls only the average voltage of the output capacitor C a. In aition, the output current comman is ae to the uctor current comman value the mor loop as a fee forwar regulation orer to control the output current [17]. The output capacitor voltage is necessary to be higher than the put voltage orer to achieve the susoial waveform at the output sie of boost verter. Hence, the output capacitor voltage comman value must satisfy (1) awtooth rrier Moe I Moe II Moe III Moe I I peak t out_ peak C _ avg I ave Current flowg to C a t where C_avg is the output capacitor voltage comman value, out_peak is the maximum amplitue of the gri voltage, is the put voltage. The put uctor current comman value is calculate after ecig the output capacitor voltage comman value by (1). The put uctor current comman value is ecie by () i a * out ( i iout*) i s(f outt) out_ rms P where i is the output capacitor comman value voltage control, i out* is the output current comman value, is the output capacitor voltage, P out is the output power, out_rms is the effective value of the gri voltage, f out is the frequency of the gri. Note that the put uctor current comman value for the other output capacitor voltage Cb is omitte ue to explanation by vertg the output current comman value. The uty of the boost verter is then compare with sawtooth waveform to generate the switchg signal. Fig. 6 shows the relationship between the put uctor current an the uty ratio of the boost verter. Duty ratio comman values 1 an are the perio for the control of the output capacitor voltage. Duty ratio comman values 3 an 4 are the perio for the control of the output capacitor voltage Cb. These uty ratio comman values are controlle orer to share the put uctor current. Furthermore, the uty ratio comman value is the zero current perio orer to I peak Current flowg from C b Fig. 6. Waveform of relationship between uctor current an uty ratio. prevent the terference of the current control between the output capacitor C a an C b. The uty ratio for the put uctor current control is calculate by the relationship between the maximum value an the average value of the put uctor current. In the control of the output capacitor voltage, the maximum value an the average value of the put uctor current is shown by (3) an (4). I peak_ ca 1Tsw Tsw I peak_ ca I ave_ ca ( 1 ) where is the put uctor, 1 an are the uty ratio Fig. 6. The relationship between 1 an is calculate by the maximum value an the average value of the put uctor current. The uty ratios 1 an are explae by (5) an (6).

4 ( ) P ( ) out 1 iave_ * Tsw out_ rmstsw peak C_avg (6) 1 Cb The uctor current is controlle to the DCM by uty ratio. imilarly, base on the output capacitor voltage Cb, the uty ratio of the put uctor current 3 an 4 is calculate by (7) an (8). 3 ( Cb ave_ Cb* ) CbTsw i ( Cb P out ) out_ rms T sw + out_marg Fig. 7. Relationship between put voltage an output capacitor voltage at uctor esign. 8 P out =1 W t (8) Cb 4 3 As a result, the DCM operation of the put uctor current is achieve. In aition, the put uctor current share each operation moe put uctor. Input uctor [mh] 6 4 P out = W P out =3 W I. CONIDERATION OF INDUCTOR A. Design of put uctor for boost verter Fig. 7 shows the waveform of the put voltage, output capacitor voltages an Cb the boost verter. In this case, the average output capacitor voltages are ecie by (1). Furthermore, each output capacitor voltages have a marg out_marg orer to prevent the put voltage an output capacitor voltages from becomg same voltage. The boost verter shares the current of each operation moes on only one put uctor. Therefore, the uty comman values of operation moes are satisfie (9) (9) In this case, the conition is the critical moe; i.e. it is the worst case at the DCM operation of the uctor current. Note that the uty comman value of the zero current perio is ae to (9) if the zero current is necessary. The conuction loss of switchg evices can be reuce ue to the current ripple of the uctor current is the mimum at the critical moe of the DMC operation. Hence, the best conition for the put uctor is the critical moe of DCM operation at the rate power. The put uctor value of the critical moe is esigne by (1) which are relationship between uty comman values from (5) to (8) an the conition of the critical moe (9). 1 3 Input voltage [] Fig. 8. Designe uctor value of boost verter at critical moe of DCM (clue 1% marg). P out out_ rmstsw Cb Cb where g_rms is the effective value of the gri voltage, P out is the output power, T sw is the switchg perio of the boost verter. Moreover, the put uctor value have a 1% marg compare with the esign value when the prototype circuit of the boost verter use the put uctor esigng by (1). Fig.8 show the esigng uctor value when the put voltage is change at each output power conitions. The esign conitions are of the gri voltage an 1 khz of the switchg frequency. In aition, the mimum voltage of the output capacitor is higher than the put voltage by % of the maximum value of the gri voltage. The put uctor is crease when the put voltage is crease. On the other han, the put uctor value become small when the output power become high. B. Inuctor comparison with conventional system The value of the put uctor for boost verter is uner mh when the put voltage is change. Therefore, it is consiere how the put uctor of the boost verter can be ecrease compare with the conventional two-stage system.

5 Fig. 9 shows the structure of the uctor when uctors are esigne. Table 1 shows the esign conition of circuit parameters an material parameters about circuit specification an the uctor core. The Ferrite is selecte for the material of the uctor core. In aition, the shape of the uctor core is EE type. The space factor is suppose from.4 to.6 at the esign of the uctor. The boost uctor of the conventional two stage type is esigne by the ripple current value of the uctor. Therefore, it is esigne by (11). DC D I fsw DC space factor of wire.4~.6 where is the put voltage, DC is the DC lk voltage, f sw is the switchg frequency, DI is the ripple current of the uctor at peak to peak. The terconnecte uctor of the conventional two stage type is also esigne by (11). is the peak voltage of the gri when the terconnecte uctor is esigne. In aition, f sw is two times compare with boost uctor esign ue to the verter is operate at PWM. Fig. 1 shows esign uctor values of the conventional two stage type an the boost verter. The boost uctor an the terconnecte uctor are.1 mh an 6.1 mh at the put voltage is 48. On the other han, the put uctor of the boost verter is 4.1 mh. The put uctor value of the boost verter is reuce by 98.% compare with the boost uctor of the conventional two stage type. In aition, the effect for mimization is large ue to the conventional two stage type have the terconnecte uctor without the boost uctor. As a result, the boost verter can reuce the circuit volume compare with the conventional two stage type.. IMUATION REUT l g A. Operation of bosst verter Table shows the simulation conitions, whereas Fig. 11 Table. imulation conitions of boost verter. Material : Ferrite Fig. 9. Designg uctor structure of each circuit toporogy. Table 1 Design conition of uctors hape type EE core Material N87 Material conition of Initial permeability m i ± 5% Inuctor Flux ensity B s 49 mt Flux ensity H c 1 A/m Resistivity r 1 Wm Output power P out 3 W Circuit conition Output voltage out witchg frequency f sw 1 khz Design conition of DClk voltage DC 35 conventional circuit Ripple ratio of current DI 3 % Output power P out Output voltage out pecification Output frequency f out Input voltage witchg frequency f sw Boost uctor Conventional circuit Interconnecte uctor Boost verter Boost uctor Input voltage Inuctor current I 3 W 5 Hz 48 1 khz. mh 6.1 mh 4 mh Inuctor value [mh] Boost uctor (Conv.) Interconnecte uctor (Conv.) Input uctor (Prop.) Output voltage out Output current I out Output capacitor voltage, Cb Input voltage [] Fig. 1. Comparison of esigne cutor values between conventional two-satage type an boost verter when the put voltage is change. Fig. 11. Operation each waveform of boost verter circuit simulation.

6 shows the simulation results of the boost verter operation. It is confirme that the boost verter can generate the susoial waveform of the output voltage when the put power supply is DC source. In aition, the voltage of the output capacitor an Cb is controlle over the put voltage at each operation moe perios. In consequence, the boost verter is achieve the boost moe an the step-own moe. Fig. 1 shows the magnifie waveform of the put uctor current. It is confirme the put uctor current is operate each perio for the voltage of the output capacitor an Cb. As a result, the put current is realize DCM operation orer to share the put uctor current for each operation moe. In this simulation, the put uctor current have the zero current perio between the voltage control of an Cb. Fig. 13 shows the neutral pot voltage waveform of the gri sie at the operatg boost verter simulation. The neutral pot voltage is kept the constant value by the average value of the output capacitor voltage. Aitionally, the voltage ripple of the neutral pot voltage is uner the 1. As a result, the voltage changg of the gri sie is suppresse ue to the voltage ripple of the neutral pot voltage is low. B. oss analysis Fig. 14 shows simulation results of the loss analysis. It is compare with two DC/AC converters, the conventional two stage type an the boost verter. In this case, the loss analysis results clue only the switchg evices an the uctor. The uctor loss is obtae from GeckoMAGNETIC of the simulation software. From the results, the loss of the boost verter is reuce compare with the conventional two-stage Fig. 1. Magnifyg operation waveform of put uctor current. Output voltage out Output current I out Neutral pot voltage n type. The switchg evice losses of the conventional type are 4.7 W. The loss of the boost verter is 7.6 W. The switchg evice losses of the boost verter are 38.% larger than conventional two stage type. It is cause by the large effective value of the put uctor current of the boost verter compare with the conventional two stage type. On the other han, uctor losses are 13.7 W of the conventional two stage type ue to the uctor is connecte to boost converter sie an verter sie. In the boost verter, the uctor loss is 6.6 W cause by connectg the small uctor. Therefore, the uctor loss of the boost verter is 51.8% smaller than the conventional two stage type. As a results, the converter loss of the boost verter can be reuce compare with the conventional two stage type ue to the uctor current is share boost verter. Fig. 15 shows the RM uctor current for each uctors. These are the boost cutor an the terconnecte uctor of the convental two stage type conpare with the put uctor of the boost verter. The boost uctor current is 6.5 A at 48 of the put voltage. Aitionaly, the terconnecte uctor current is 1.5 A. On the other han, the put uctor Devices oss [W] Inuctor current I [A] Efficiency 94.% Conventional two-stage type Inuctor loss witchg loss Conuction loss Device Conv. : G6654B Prop. : G66516T Efficiency 95.% Propose boost verter Fig. 14. oss analysis of conventional circuit an propose circuit simulation Input uctor (Prop.) Boost uctor (Conv.) Output power P out : 3 W Output voltage out : witchg frequency f sw : 1 khz DC lk voltage : 35 Interconnecte uctor (Conv.) 1 3 Input voltage [] Fig. 13. Measurement waveform of neutral pot voltage of propose circuit. Fig. 15. Comparison of RM of each uctro current.

7 current is A. It is 67.5% large compare with the boost uctor current. Therefore, it is confirme the effective current the boost verter is large compare with the convemtional two stage type. In consecuence, the loss of the switchg evice is cerese the boost verter. However, the uctor loss of the boost verter is reuce ue to the uctor voalue of the boost verter is smaller than each cutor of the conventional two stage type. C. Inuctor energy of boost verter Fig. 16 shows the uctor energy of each uctor of the conventional two stage type an the boost verter. Energies of the boost uctor an the terconnecte uctor are 43. mj an 6.9mJ. On the other han, the put uctor energy is 8 mj. The put uctor energy is reuce by 84% compare with the total uctor energy of the conventional two stage type. Therefore, the uctor volume of the boost verter is reuce compare with the conventional two stage type. As a results, The volume of the DC/AC converter can be reuce usg the boost verter. this case, the put uctor of the boost verter is esigne by (1). The put uctor value have 1% marg compare with the mimum esign value orer to prevent the critical moe when the conition is the rate power. Fig. 18 an 19 shows each operation waveform of the boost verter when the output power is 1 W. It is confirme the susoial waveform of the output voltage at 1 when the put power supply is DC source. In aition, the output current THD is measure 1.4%. The boost verter is realize the low current THD of the output current. On the other han, each output capacitor voltage is kept the constant value of the average voltage ue to voltage control orer to become over the put voltage. Moreover, the output capacitor voltage is Input voltage [1 /iv] Inuctor current I [ A/iv] I. EXPERIMENTA REUT Fig. 17 shows the experiment iagram of the boost verter. The experimental conition is connecte only resistor loa orer to confirm the prototype system of the boost verter. In Output voltage out [5 /iv] Inuctor energy [mj] Total energy 5. mj Conventional two-stage type Interconnecte uctor Boost uctor Input uctor Reuce by 84% Total energy 8. mj Propose boost verter Fig. 16. Comparison of uctor energy between comventional two-stage type an boost verter. Output current I out [ A/iv] THD 1.4% Time [1 ms/iv] Fig. 18. Experimental results of put an output waveforms. pacitor voltage [1 /iv] pacitor voltage Cb [1 /iv] Inuctor current I [ A/iv] Output current I out [1 A/iv] Time [1 ms/iv] Fig. 19. Experimental waveform of each output capacitor voltage. Device:CT8KE(Rohm) Inuctor current I [1 A/iv] :3 mh 3 4 R loa 1 W 1 :1 C a C b f sw : khz 1.5 mf Time [ ms/iv] Fig. 17. Experimental circuit iagram usg propose circuit. Fig.. Magnifyg DCM waveform of put uctor current.

8 oscillate at the output frequency. As a results, it is confirme the control of the boost verter is operate. Fig. shows the magnifie waveform of the uctor current. The put uctor current is operate DCM ue to zero current perio. Therefore, there are zero current perio between the voltage control of the output capacitor voltage an Cb. It is confirme the put uctor current similar to Fig. 6. In consequence, the put uctor current is share between each output capacitor voltage control the boost verter. In aition, the verter operation is realize by the boost verter confirmg from experimental results. II. CONCRUION In this paper, the boost verter usg only one put uctor is propose applie for the micro-verter orer to mimization of the volume. In aition, It is consiere the esign metho of the put uctor, the simulation of the circuit operation an the comparg the losses of converter between the conventional two stage type an the propose boost verter. As a results, it is confirme the uctor loss of the propose boost verter is reuce by 51.8% compare with the conventional topology the theoretical consieration. Therefore, the operation of the boost verter is confirme experimental results. In consequence, the propose boost verter can be converte DC to AC usg only a put uctor. In the future, the operation an the efficiency of the boost verter will confirm when the gri is connecte at 3 W. REFERENCE [1]. ariakis, E. Koutroulis, F. Blaabjerg : Optimization of ic-base H5 an Conergy-NPC Transformerless P Inverters, IEEE Journal of Emergg an electe Topics Power Electronics, ol. 3, No., pp (15) [] Y. Zhou, Hongbo i, Hui i : A gle-phase P Quasi-Z-ource Inverter With Reuce pacitance Usg Moifie Moulation an Double-Frequency Ripple uppression Control, IEEE Transactions on Power Electronics, ol. 31, No. 3, pp (16) [3] R. Chattopahyay,. Bhattacharya, N. C. Foureaux, I. A. Pires, H. e Paula,. Moraes, P. C. Cortizio,. M. ilva, B. C. Fil-ho, Jose A. e. Brito : ow-oltage P Power Integration to Meium oltage Gri Usg High-oltage ic Devices, IEEJ Journal of Inustry Applications, vol.4, no.6, pp , (15). [4]. ariakis, E. Koutroulis, F. Blaabjerg : Optimization of ic-base H5 an Con-ergy-NPC Transformerless P Inverters, IEEE Journal of Emergg an electe Top-ics Power Electronics, vol. 3, no., pp , (15). [5]. Yamaguchi, T. himizu : gle-phase Power Conitioner with a Buck-boost-type Power Decouplg Circuit, IEEJ J. Inustry Applications, vol.5, no.3, pp , (16). [6] C. iao, W., Y. Chen, C. Chou : A P Micro-verter With P Current Decouplg trategy, IEEE Trans. on Power Electronics, ol. 3, No. 8, pp (17). [7] M. A. Rezaei, K. ee, A. Q. Huang : A High-Efficiency Flyback Micro-verter With a New Aaptive nubber for Photovoltaic Applications, IEEE Trans. on Power Electronics, ol. 31, No. 1, pp (16) [8] A. C. Nanakos, G. C. Christiis, E. C. Tatakis : "Weighte Efficiency Optimization of Flyback Microverter Uner Improve Bounary Conuction Moe (i-bcm)", IEEE Transactions on Power Electronics, ol. 3, No. 1, pp (15) [9] W. J. Cha, Y. W. Cho, J. M. Kwon, B. H. Kwon : "Highly Efficient Microverter With oft-witchg tep-up Converter an gle- witch-moulation Inverter", IEEE Transactions on Inustrial Electronics, ol. 6, No. 6, pp (15) [1] D. Meneses, O. García, P. Alou, J. A. Oliver, J. A. Cobos : "Gri- Connecte Forwar Microverter With Primary-Parallel econary- eries Transformer", IEEE Transactions on Power Electronics, ol. 3, No. 9, pp (15) [11] M. Jang,. G. Ageliis : A Mimum Power-Processg-tage Fuel- Cell Energy ystem Base on a Boost-Inverter with a Biirectional Backup Battery torage, IEEE Trans. on Power Electronics, ol. 6, No. 5, pp (11). [1] R. O. ceres, I. Barbi : A boost DC-AC converter: analysis, esign, an experimen-tation, IEEE Transactions on Power Electronics, vol. 14, no. 1, pp , (1999). [13] D. B. W. Abeywarana, B. Hrezak,. G. Ageliis : An Input Current Feeback Metho to Mitigate the DC-ie ow-frequency Ripple Current a gle-phase Boost Inverter, IEEE Transactions on Power Electronics, vol. 31, no. 6, pp , (16). [14] W. Zhao, D. D. C. u,. G. Ageliis : Current Control of Gri- Connecte Boost Inverter With Zero teay-tate Error, IEEE Transactions on Power Electronics, vol. 6, no. 1, pp ,. (11). [15] Y. Tang, Y. Bai, J. Kan, F. Xu : Improve Dual Boost Inverter With Half Cycle Moulation, IEEE Transactions on Power Electronics, vol. 3, no. 1, pp , (17). [16] T. Morita et al. : mwcm GaN-base monolithic biirectional switch usg normally-off gate jection transistor, 7 IEEE International Electron Devices Meetg, Washgton, DC, 7, pp [17] H. N. e, K. Orikawa, J. I. Itoh : Circuit-Parameter-Inepenent Nonlearity Compensation for Boost Converter Operate Discontuous Current Moe, IEEE Transactions on Inustrial Electronics, vol. 64, no., pp , (17).