INTERNATIONAL JOURNAL OF MICROWAVE AND OPTICAL TECHNOLOGY, Priyanka Malik 1, Rishu Chaujar 2, Mridula Gupta 1 and R.S. Gupta 1,*

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1 36 VOL.5, NO.6, NOVEMBER 200 Physics base Threshol Voltage nalysis of Gate Material Engineere Trapezoial Recesse Channel (GME-TRC) Nanoscale MOSFET an its multilayere gate architecture Priyanka Malik, Rishu Chauar 2, Mriula Gupta an R.S. Gupta,*,* Semiconuctor Devices Research Laboratory, Department of Electronic Science, University of Delhi, South Campus, New Delhi (Inia) 2 Department of Electronics, Deen Dayal Upahyaya College, Karampura, University of Delhi, New Delhi-005 Tel.No.: , Fax No: bstract: In this paper, a novel evice structure: Multi-Layere Gate Material Engineere Trapezoial Recesse Channel (MLGME-TRC) MOSFET has been propose an a twoimensional (2D) analytical threshol voltage moel base on the solution of Poisson s equation in cylinrical coorinates, utilizing the cylinrical approximation, has been evelope. The propose esign improves the gate leakages an increases stanby power consumption to a great extent which arises ue to the continue scaling of O2 gate ielectrics. The moel accurately evaluates the channel potential, electric fiel, threshol voltage, rain-inuce barrier lowering (DIBL), ION/IOFF ratio an sub-threshol slope. The evice simulators: TLS an DEVEDIT have been use to verify the accuracy of the propose moel, an a goo agreement between their results is obtaine. Inex Terms: TLS, Corner effect, DEVEDIT, GME, NJD, TRC MOSFET.. INTRODUCTION During the past ecae, CMOS technology has seen excellent spee an performance, achieve through improve esign, the use of higher quality material; an most importantly, gate length reuction. However, scaling methoology relies heavily on the use of successively thinner gate ielectrics ( 3 nm) an higher levels of channel oping ( cm -3 ) as feature sizes ecrease in orer to simultaneously achieve the esire turn-off an rive current capabilities [, 2]. significant consequence of aggressively own scaling the gate ielectric (silicon-ioxie, O 2 ) in MOS transistor results in irect tunneling of carriers between the gate electroe an silicon () substrate [3, 4], an thus the gate an channel regions are no longer isolate from each other. This large irect tunneling current increases power consumption an egraes evice performance making O 2 gate ielectric an unesirable material in this thickness regime [4]. Therefore, there has been much interest in fining a high-permittivity (high-k) gate insulator with greater physical thicknesses to prevent irect gate tunneling. But, the use of high-k gate material may result in ielectric thicknesses comparable to the evice gate length, resulting in increase fringing fiels from the gate to the source rain regions an compromise short channel performance. Thus, an ultra thin O 2 interlayer between the high-k layer an silicon substrate was introuce (resulting in a multilayer gate structure) to improve the interface quality an stability. The CMOS transistors esigne with multi-layer high-k gate ielectrics achieve the expecte high rive current performance an lower leakage current, thereby proving its efficacy for high performance CMOS logic applications. lso, with the reuction of channel length, evice encountere with IJMOT ISRMT

2 362 VOL.5, NO.6, NOVEMBER 200 various short channel effects (SCEs) an HCEs. To achieve higher spee an current riving efficiency; an lower SCEs an HCEs, Gate material Engineering (GME) architecture (5-7) incorporation with Recesse Channel (RC) MOSFET (8, 9) can be consiere as a potential caniate to suppresses an overcome the punch through an DIBL an thus proving its efficacy for high spee ULSI circuits. Thus, MLGME-TRC MOSFET consiere in this stuy integrates the esire features of multi-layere an gate material architecture, such as improvement in gate controllability an reuction in gate leakage, tunneling effects, SCEs an improvement in carrier transport efficiency; an those allie with RC MOSFET such as excellent hot carrier immunity, SCE an punchthrough suppression, thereby enhancing the gate controllability over the channel an the electrical an switching characteristics in terms of DIBL, subthreshol swing an hot carrier effects. In orer to gain an insight into the effectiveness of propose esign, the analysis takes into account the structural parameters (θ,l p ) [0], negative unction epth (NJD) an substrate oping (N ). II. NLYTICL MODEL FOR SURFCE POTENTIL ND ELECTRIC FIELD (a) Surface potential analysis: In the present analysis, the channel region is ivie into two parts, since the gate is mae up of two ifferent materials laterally merge together. ssuming the concave corner to be part L of a cyliner, having raius p ro = 2 ( + tanθo 2) [], Poisson equation in cylinrical coorinates for potential, i.e. ψ ( r, θ ), is given by 2 ψ ( r, θ) ψ ( r, θ) 2 ψ ( r, θ) qn + + = r r r r θ () The potential profile in the raial irection can be approximate by a parabolic function [2] an the channel region has been ivie in to two parts; hence the potential uner the gate region M an M2 can be represente as ψ ( r, θ) = ( ) ( ) ( ) 2 0 θ + θ r+ 2 θ r for 0 θ θ0 ; ro + EOT r ro + EOT + y (2) ψ ( ) ( ) ( ) ( ) 2 2 r, θ = 02 θ + 2 θ r+ 22 θ r for θ0 θ θ0 + θ02 ; ro + EOT r ro + EOT + y (3) Where, EOT is the effective oxie thickness an y is the epletion layer thickness, given by: ox 2 EOT = tox + tox2, y =.5φ F ox2 qn Base on bounary conitions, as shown in Fig. the Poisson s equation is solve separately uner the two gate regions (M an M2) an the coefficients in (2) an (3) can be calculate as: o ( θ ) = VSUB. γ roln( + EOT ro) (4a) 2 ( ro + EOT + y) ( Vg ψs ( θ) 2y ) ( θ ) =. γ roln( + EOT ro) ( ro + EOT + y). ( Vg ψ S ( θ ) ) 2 y ( θ ) =.. 2y γ roln( + EOT ro) ( Vg ψs ( θ) ) (4b) (4c) where, =,2 for regions uner M an M2 respectively. Using these coefficients, potential can be obtaine as; ψ ( r, θ) = VSUB +. ( Vg ψs ( θ) ). γ ro ln( + EOT ro) 2 2 ( ro + EOT + y) ( ro + EOT + x) 2 + r r 2y y 2y (5) IJMOT ISRMT

3 363 VOL.5, NO.6, NOVEMBER 200 Using this potential, Poisson equation can be solve at the surface of the channel, r = r + EOT, o ψ ( r = r + EOT, θ) = ψ ( θ) (6) o S V ψ ( r + EOT, θ) +. = 0 γ roln( + EOT ro) g S o 2 ψ S ( ro + EOT) y qn 2 2 θ λ ( y ro EOT) (7) 2( ro + EOT)( y ro EOT) Where, = (8) 2 2 λ y Introucing a new variable ( θ) = ψ ( r + EOT, θ) V + S o g ( r + EOT) y qn. ( y ro EOT ) γ roln( + EOT ro) o Therefore, Vg. ψ ( ) oln( o) S θ = γ r + EOT r + ( θ) ( ro + EOT) y qn ( y ro EOT) (9) (0) an substituting (9) in (7), Poisson equation reuces to a secon orer ifferential equation in 2 ( θ) ( θ) ( θ ) i.e. = 0 () 2 2 θ λ On solving ifferential equation in (), we get Using (9), ( θ = 0) =, ( θ = θo + θo2) = 22 an bounary conition we get, = Vbi Vg +. γ roln( + EOT ro) ( ro + EOT) y qn ( y r EOT) o (3) 22 = + Vs ( VFB VFB2) (4) Using bounary conitions, as shown in Fig., an equations (0), (), (2) an (3), we can obtaine the value of 2 an 2 as sinh( θo λ) + sinh( θo λ) + ( Vg Vg ) K 2 = K+ K2 (5) sinh( θ λ) + sinh( θ λ) + ( V V ) K 2 = K + K o2 22 o g2 g 2 2 where 0 02 K = cosh( θ λ)sinh( θ λ) an (6) K = cosh( θ λ)sinh( θ λ) (7) (b) Electric Fiel analysis The electron velocity through the channel is relate to the electric fiel pattern along the channel. Thus, the electric fiel is given as E ( θ S ) = ( r, ) r r ( ) o EOT S r. θ ψ θ r. θ ψ θ = + = ( θ)sinh ( θom θ) λ + m= 2( θ)sinh θ + θ0 θom λ m= ( θ) = sinh( θ λ) o (2) where, r = ro + EOT Electric fiel component, uner M is given as (8) IJMOT ISRMT

4 364 VOL.5, NO.6, NOVEMBER 200 E S ( θ ) ( ) cosh ( θ θ) λ r. λsinh( θo λ) 2 cosh( θ λ) o = Electric fiel component, uner M2 is given as E S 2 (9) ( ) 2 cosh ( θo + θo2 θ) λ ( θ ) = r. λsinh( θo2 λ) 22 cosh(( θ θo ) λ) (20) III. THRESHOLD VOLTGE MODEL In GME-TRC MOSFET, ue to existence of metal gates, M an M2, with ifferent work functions, the surface potential minima are etermine by region uner M. Thus, substituting ψ ( r + EOT S o, θ min) = 2 φ F an Vgs = Vth in the expression for surface potential uner M, we can obtain an expression for threshol voltage. The position of minimum surface potential θ min lies uner the first metal gate M an can be evaluate as ψ ( r EOT, ) S o + θ θ= θ = 0 (2) min θ an the minimum surface potential is ( ro + EOT) y qn ψs( θmin) = Vg + M ( y r EOT) θo θmin θmin sinh 2 sinh λ + λ θmin sinh λ o (22) Using above equation, the threshol voltage is given as V th ( r + EOT) y qn = 2φ F + M ( y r EOT) θ 2exp 2 λ 0 o 2 o IV. SUB-THRESHOLD SLOPE (23) In the sub-threshol regime, as the rain voltage increases, the gate slowly loses its control over the channel; as a result, the electron concentration is not only controlle by the gate bias, but also by the nearness of the source an rain epletion regions. Thus, for a evice to have a goo turn-on or switching characteristics, this evice characteristic shoul be as small as possible an can be expresse in terms of minimum surface potential an is given as kt S = ln(0) (24) q ψ ( r + EOT, θ ) V S o min gs where, k is boltzmann s constant an T is room temperature (300K) 6. Results an Discussion Source X N D + L M Gate High-K L g Ψ (r,θ) Ψ 2(r,θ) t ox2 t ox O 2 NJD M M2 L s V L bi eff x L p t epletion ege: y Potential= Ψ (r,θ)= Ψ 2(r,θ)= V SUB, Electric fiel=0 TRC Drain N D + V bi + V s IJMOT ISRMT

5 365 VOL.5, NO.6, NOVEMBER 200 θ 0 r 0 θ 0 θ 02 θ θ 0 Fig..Schematic structure of MLGME-TRC MOSFET, where channel length L g = L + L 2 =74nm, with work function Ф M =4.77V an Ф M2 = 4.0V for MLGME-TRC an GME-TRC MOSFET an for TRC MOSFET, channel length L g =L =74nm an work function Ф M =4.77V having Negative unction epth (NJD)=0nm, Groove Depth =20nm, N =x0 7 cm -3, N D =x0 20 cm -3, t ox = t ox2 =2nm, L eff =(2 x L s ) + L p,where L p =28nm, L s =4nm unless state otherwise. The schematic structure of MLGME-TRC, GME- TRC an TRC MOSFETs are shown in Fig.. with metal gates, M an M2 of lengths L an L2 respectively. In MLGME-TRC MOSFET, the gate consists of multi-layere-gate ielectrics having a thickness t ox an t ox2 of the lower an the upper gate ielectrics, with the corresponing permittivites, ox an ox2, respectively; an for GME-TRC an TRC MOSFETs: t ox = t ox2. Fig.2 reveals that, TRC-MOSFET with GME architecture improves the evice performance with the use of two metal gates i.e. M(control gate) an M2 (screening gate) where Φ M > Φ M2, in terms of improve gate control an riving current capabilities. This is ue to the step in surface potential at the interface of two metals, as shown in Fig.2, which results in screening of channel region uner metal gate M from rain potential variations. This step in potential forces the electric fiel to be reistribute on the rain sie. This electric fiel iscontinuity at the interface of the two gate metals causes the overall channel fiel to be more uniform across the channel, as shown in Fig.3(a), resulting in the enhancement of carrier transport efficiency across the channel an hence, improves the short channel effects (SCEs), in terms of threshol voltage roll-off an DIBL, as shown in fig.4 an Table.. Moreover, in GME-TRC MOSFET, ue to the step in potential profile, the barrier height seen by the electrons at rain en of the gate is lower as compare to TRC MOSFET, leaing to increase number of electrons tunneling from the channel, resulting in more sewer gate leakage current tening to increase sub-threshol slope for GME-TRC MOSFET as compare to TRC MOSFET, as evient from Table.. Further, there is a significant improvement in I ON /I OFF ratio for GME-TRC MOSFET in comparison with TRC MOSFET, resulting in enhancement of switching characteristics of the propose esign. This performance enhancement in GME-TRC MOSFET is mainly because of the increase gate control an reuce SCEs. Surface Potential (V) Φ M2=4.V N =5x0 6 cm -3 NJD=4nm MODEL TRC MLGME-TRC V s =0.5V Normalize Position along the channel Fig.2. Potential profile for ML-GME-TRC, GME-TRC an TRC MOSFETs for ifferent structural parameters Fig.2. clearly epicts that for MLGME-TRC MOSFET, there is a significant enhancement in IJMOT ISRMT

6 366 VOL.5, NO.6, NOVEMBER 200 Electric fiel(v/cm) Electric fiel(v/cm).5e+06.0e E E E E E E+06.5E+06.0E E+05 (a) TRC GME-TRC MODEL V s =0.5V Normalize Position along the channel (c) V s =0.5V -5.0E E+06 NJD=4nm -.5E+06 M ODEL -2.0E Normalize Position along the channel Electric fiel(v/cm) Electric fiel(v/cm).5e+06.0e E E E E E+06.0E E+05 (b) MLGME-TRC MODEL Normalize Position along the channel () V s =0.5V V s =0.5V -5.0E E+06 N =5x0 6 cm E+06 MODEL -2.0E Normalize Position along the channel Fig.3 electric fiel profile for ML-GME-TRC, GME-TRC an TRC MOSFETs for ifferent structural parameters step in potential leaing to the better screening of metal gate M, as a consequence of the incorporation of multi-layere high-k ielectric system that facilitates physically thicker gates, thereby permitting the scaling of gate oxie thickness an thus, increasing gate control over the channel. This results in enhancement of electric fiel at the interface, an reuction at the rain en, as shown in Fig.3(b), thereby, improving the current riving capabilities across the channel an hence, improves the threshol voltage roll-off an DIBL, as shown in Fig.4 an Table., ue to the improve gate control an hot carrier immunity for MLGME-TRC MOSFET. Moreover, the amalgamation of multi-layere architecture on GME-TRC MOSFET also improves the sub-threshol slope an I ON /I OFF ratio, as reporte in Table. an Fig.5. Fig.2 also reflects that, as NJD increases magnitue of minimum surface potential ecreases, leaing to reuce gate controllability on the channel. s NJD increases, the peak electric fiel at the rain en reuces, as shown in Fig.3(a an c), ue to better screening of the channel from rain bias variation an improve carrier mobility, respectively; which reflect evice reliability in terms of HCEs an SCEs. Threshol Voltage, V th(v) MODELED Φ M2=4.V N =5x0 6 cm -3 NJD=4nm TRC MLGME-TRC V gs =0.0V Drain to Source voltage,v s (V) Fig.4. Threshol voltage variation for ML-GME-TRC, GME- TRC an TRC MOSFETs for ifferent structural parameters Further, higher NJD results in increase barriers height at corners, leaing to reuce carrier velocity. Due to this, carriers require more energy to surmount these barriers, thereby raising the threshol voltage an DIBL as is evient from Fig.4 an Table., respectively. Higher NJDs, however, provie better switching ue to reuce sub-threshol swing an better I ON /I OFF ratio, as is evient from the Table. an Fig.5, respectively. trae-off can, thus, be mae epening upon the esign requirements whether the threshol voltage is the nee of the esign or is it the switching behavior. IJMOT ISRMT

7 367 VOL.5, NO.6, NOVEMBER 200 Parameters DIBL Subthreshol slope, S (mv/ec.).6e+06 Φ M2=4.V, NJD=4nm, N =5x0 6 cm -3 ML-GMETRC t ox =3.9, t ox2 =20 TRC GME- φ M =4.77V, TRC φ M2 =4.V NJD=4nm N =5x0 6 cm ION/IOFF.4E+06.2E+06.0E E E E E+05 Table.. DIBL an sub-threshol voltage slope variation for ML- GME-TRC, GME-TRC an TRC MOSFETs for ifferent structural parameters. Moreover, as substrate oping ecreases, the magnitue of minimum surface potential increases an electric fiel at the rain en ecreases, as shown in Fig.2 an 3 (a an ), leaing to the better gate controllability across the channel an reuce HCEs an threshol voltage an DIBL, as inicate in Fig.4 an Table., owing to the improve mobility across the channel. Figure clearly preicts that higher substrate oping results in higher threshol voltage, lesser subthreshol slope, as inicate from the Fig.4 an Table.. Thus, higher substrate oping is beneficial for better evice switching spee, i.e. from OFF state to ON state, as shown in Fig.5. TRC GME-TRC MLGME-TRC Fig.5. I ON /I OFF ratio for ML-GME-TRC, GME-TRC an TRC MOSFETs for ifferent structural parameters CONCLUSION In this work, a novel structure, MLGME-TRC MOSFET has been propose, analyze an investigate using evice simulators: TLS an DEVEDIT. The analytical an simulation results reveal that MLGME-TRC MOSFET proves to be superior to GME-TRC an TRC MOSFETs in terms of reuce DIBL, threshol voltage roll-off an HCEs; an enhance carrier transport efficiency an switching spee of the evice in terms of I ON /I OFF ratio. The tuning of GME-TRC structure in terms of various structural parameters has also been one an compare with MLGME-TRC MOSFET. Moreover, stuy shows that the sub-threshol slope increases in case of GME-TRC MOSFET ue to the increase gate leakage current. However, this egraation can be minimize by incorporation of multi-layere architecture on GME-TRC MOSFET. This results in improve switching spee of the evice an hence, presenting as an attractive solution for the ongoing integrating processes in igital esign technology an low stanby power (LSP) applications. IJMOT ISRMT

8 368 VOL.5, NO.6, NOVEMBER 200 CKNOWLEDGEMENTS uthors are grateful to Department of Science an Technology (DST) for proviing the necessary financial assistance to carry out this research work. REFERENCES [8] H. Ren, Y. Hao, Soli-State Electronic, 46, 665, (2002). [9] E. Takea, H. Kume an S. sia, IEEE Trans Electron Devices, 30, 68, (983). [0] Z. Xiao-Ju, G. Xin, W. Jun-Ping, an H. Yue, Chin. Phys. Soc, 5, 63, (980). [] X.J. Zhang, H.X. Ren, Q. Feng an Y. Hao, [2]. Kranti, S. Halar, an R.S. Gupta, Microelectronics Engineering, 56, 24, (200). [] Ono M, Saito M, Yoshitomi T, Fiegna C, Ohguro T an Iwai H 995 IEEE Trans. Electron Devices [2] Taur Y et al 997 Proc. IEEE [3] Rana F, Tiwari S an Buchanan D 996 ppl. Phys. Lett [4] Momose H S, Ono M, Yoshitomi T, Ohguro T, Nakamura S I, Saito M an Iwai H 996 IEEE Trans. Electron Devices [5]. Chauhary, M.J. Kumar, IEEE Transnsaction On Electron Devices, 5, 463, (2004). [6] Priyanka Malik, Sona P. Kumar, Rishu Chauar, Mriula Gupta an R.S.Gupta, GTE MTERIL ENGINEE - [7] Priyanka Malik, Rishu Chauar, Mriula Gupta an R.S.Gupta, Two-imensional nalytical Moel for Trapezoial Recesse Channel (TRC) MOSFET using Gate Material Engineering, ISMOT Chin J. Semiconuctors, 25, 44, (2004) (in chinese).. IJMOT ISRMT