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1 (12) United States Patent Dugger et al. lllll llllllll ll lllll lllll lllll lllll lllll US689897B2 (1) Patent o.: US 6,898,97 B2 (45) Date of Patent: May 24, 25 (54) FLOATG-GATE AALOG CRCUT (75) nventors: Jeffery Don Dugger, Atlanta, GA (US); Tyson S. Hall, Cleveland, T (US); Paul Hasler, Atlanta, GA (US); David V. Anderson, Alpharetta, GA (US); Paul D. Smith, Marietta, GA (US); Matthew Raymond Kui, Austell, GA (US); Abhishek Bandyopadhyay, Atlanta, GA (US) (73) Assignee: Georgia Teh Researh Corp., Atlanta, GA(US) ( *) otie: Subjet to any dislaimer, the term of this patent is extended or adjusted under 35 U.S.C. 154(b) by 93 days. (21) Appl. o.: 1/397,21 (22) Filed: (65) Mar. 24, 23 Prior Publiation Data US 23/ Al Ot. 2, 23 Related U.S. Appliation Data (6) Provisional appliation o. 6/366,714, filed on Mar. 22, 22. (51) nt. Cl.7... GllC 27/ (52) U.S. Cl /45; 365/185.3; 365/185.11; 326/37; 326/39 (58) Field of Searh /45, 185.3, 365/185.11; 326/37, 39 (56) Referenes Cited U.S. PATET DOCUMETS 4,631,4 A 5,289,41 A * 12/1986 Tanner et al /221 * 2/1994 Shima /45 5,343,555 A 5,537,512 A * 8/1994 Yayla et al /35 * 7/1996 Hsia et al /39 5,914,894 A * 6/1999 Diorio et al / ,986,927 A 5,99,512 A * 11/1999 Minh et al /185.1 * 11/1999 Diorio et al /314 22/11869 Al 1/22 Brad! et al /37 OTHER PUBLCATOS Matt Kui, AiChen Low, Paul Hasler, "A Programmable Continuous-Time Floating-Gate Fourier Proessor," EEE Transations on Ciruits and Systems- Analog and Digital Signal Proessing, vol. 48, o. 1, Jan. 21, pp Matt Kui, Aihen Low, Paul Hasler, "A Programmable Continuous-Time Analog Fourier Proessor Based on Floating-Gate Devies," EEE nternational Symposium on Ciruits and Systems, May 28-31, 2, pp * ited by examiner Primary Examiner-Van Thu guyen Assistant Examiner-]. H. Hur (74) Attorney, Agent, or Firm-Thomas, Kayden, Horstemeyer & Risley, LLP (57) ABSTRACT n one exemplary embodiment, a programmable analog array (PAA) ontains a onfigurable analog matrix having two floating-gate field effet transistors (FETs). Also ontained in the PAA is an interonnet iruit that is programmable to onfigure the onfigurable analog matrix to operate in one or more of several matrix modes. A few examples of suh matrix modes inlude a swithing matrix mode, a memory matrix mode, and a omputing matrix mode. n an exemplary method of onfiguring the PAA. PAA, the the method inludes programming an interonnetion, for example, between a first terminal of the first floating-gate FET and a first terminal of the seond floating-gate FET. The method further inludes programming an interonnetion, for example, between a gate terminal of the first floatinggate FET and a fixed voltage soure, for setting a floating gate harge on the first floating-gate FET. 19 Claims, 21 Drawing Sheets FleldPrograrnmabJeAnalo9Array (FPM) ill 5635;2 566 s;o,

2 External programming devies 16 FPAA ontrol and onfiguration logi signals D 1: aooaoaoou ou aaaaoao a ::JO:::=::JC o 15 Field Programmable Analog Array (FPAA) nput & Output signals to/from FPAA M 19 Devies for display, omputing, ontrol et. d \JJ.... =... '-<,J;;.. Ul 'Jl =... '"""'..., '"""' FG. 1 e rj'j. -..a-.. b ""-l

3 Field Programmable Analog Array (FPAA) 15 d \JJ.... =... FPAA ontrol and onfiguration logi signals from external programming devies Analog Configurable input/output analog blok interfae (CAB) matrix iruit _J 26 1r _27 FPAA ontrol and onfiguration iruit 225 FS8 to other iruitry inside FPAA 211 Analog input & output signals to/from FPAA '-<,J;;.. Ul 'Jl = , '"""' FG. 2 e rj'j. -..a-.. b ""-l

4 26 Configurable Analog Blok (CAB) matrix 315 Configurable analog blok (CAB) Configurable analog blok (CAB) 32 nteronnet iruit 32 [--Progra-b-1_e.iia-ri;8-re-tor L!!:.1.P-!_r::i_:!i-]!.?.!!_l_!:!:_:!!9_---j [----Program-mbi e ii a-ri; 8-e-tar l -!!----i--!..r:i:i.:! j Configurable analog blok (CAB) Configurable analog blok (CAB) to/from FPAA ontrol and onfiguration iruit 225 FG to/from analog i/o interfae iruit d \JJ.... =... '-<,J;;.. Ul 'Jl =......, '"""' e rj'j. -..a-.. b ""-l

5 319 Appliation speifi iruitry Configurable Analog Blok (CAB) Analog omputation iruitry : i Matrix 63 i '" ::::=::J 423 nteronnet iruit 25 [--Prgram-mab-ie-ha-riware-tor l_!!.1:1.p.!::1.!i-9!-i!.!.-:..?.--!!----; r --Program-n:;at; 1 9 t;3 r=ciwa-re-toi n l----!--:-!-.p.!.-! j 43 Analog memory iruitry r --M;;; L... =::::J to/from interonnet iruit 32 FG Digital ontrol iruitry 315 d \JJ.... =... '-<,J;;.. Ul 'Jl =...,J;;....., '"""' e rj'j. -..a Q ""-l

6 nput Capaitor 566 MOS Tunneling Capaitor d \JJ.... = ::-:. r ;n F56:: ll::,:;: g p+ll : n-well p-substrate \ n-well J : (567) n+ """" '-<,J;;.. Ul \._ 562 \., (4r+.) \. _'J \ FG. 5 e rj'j. -..a Q ""-l

7 U.S. Patent May 24, 25 Sheet 6 of 21 US 6,898,97 B2 t9 a..... b [J [J J'"L -:rl TL_... <.? s <.? '.s CJ Q.. ' (.'.) Cl 1-:l_ C Ci ::: -::i...r:- -::i...r: i_r b [J [J :r- :r- TL LL (.'.) """... (. err ---i :i...r- Ci :::P (') b <.? (") (.'.) Cl b-1 (.'.) [J Cl... Cl!) /Q_ \., : \.. / [/) Cf) o Cl (9 CL.{).\\.. ' (\.!..-_/ ,l// ---_i r- :::P (!) - o A (") o

8 j " ) Programmable hardware for implementing iruit interonnetions 31 nput pin of Output pin of Voltage bus FPAA 15 FPAA 15 inside FPAA J';. 75 J'; 76 f;" 79 " 712 " 713 ) J j \;_ Control signal from,,... FPAA ontrol & onfig. iruit 225 analog swith fusible link,' ' analog swith digital swith fusible link : : Programmable hardware for setting iruit parameters 32 : Fixed : Variable Fixed variable : voltage\ voltage j"' 7J J \.f S2 \..f j r- r:; ; AC,J Ground r:y :... ' J FG. 7a ' ' d \JJ.... =... '-<,J;;.. Ul 'Jl = J..., '"""' e rj'j. -..a Q ""-l

9 G ' : Programmable hardware for 31 '! implementing iruit interonnetions ' 1 S1... : : L ' ' Control signal from --' FPM ontrol & onfig. irwit 225 analog swith S w : Programmable hardware for 32 i : setting iruit parameters 1 PG2! PG4 ' ' tr analog swith ' d \JJ = '-<,J;;.. Ul 'Jl =......, '"""' digital swith fusible link FG. 7b fusible link e rj'j. -..a-.. b ""-l

10 U.S. Patent May 24, 25 Sheet 9 of 21 US 6,898,97 B2 z >- J_ LO f- J) o ) ----) J f- ::i o > L!) t) CJ ----) z >- u..

11 U.S. Patent May 24, 25 Sheet 1 of 21 US 6,898,97 B2 -ClJ <l'...><:: CJ _Q ClJ O> -ro <l'. (1) :: ::::J Ol '+= +-' -... CJ CJ - :::J - ro - (.) =U Q.<;:: o.. - <l'. Q. en i3 Q) : :::J CJ t). O> CJ ("<") ::::: ::::J CJ E = (.)..:::: 13 2 Q) -:. (.!) - LL

12 nput optial signal to sensor array (:ii (/) us ro. Q) E f.= UJ us C\l. Q) E f= Appliation speifi iruitry <"l - ll Cll.S2 [/J 915. e 15 l.. J Q) E i= 11) E f= w w o<.,d- -;;o'- <oo<.. 92\J.,._e,<::-C:J C::Je"'.-:...'<',.._e,<:> "'?> 'V -... ".) -... <::-,O<. f':>o'-,o <oo' "' :J;,,_'O C:;; 'l-'o :; '::i'o Cj... } Digital ontrol signals from/ to digital ontrol iruitry ' 925 J \ Analog omputation iruitry 92 f-++ <v """ '?- f-++ <v "'O l?-(j H-+ <v '1-' 're; <v.-,'o '?- <v<:- '?-G <v '?-G d \JJ = '-<,J;;.. Ul 'Jl =... '"""' '"""'..., '"""' o<. o' o<.....,o<. e<::- _,e.<:-"' <::-"' e;,e"' ACE: analog omputing element <v ""' <v '1,,<$' r.f -+-+,,J '?-G '?-G "?-(;<v "' FG. 1...«--'l-1 <v r:,1'- 'i" '?-G D-=- <v <::-"' '?-G Transformed eletrial signal output to analog i/o interfae iruit (through interonnet iruit 32) e rj'j. -..a Q ""-l

13 Appliation speifi iruitry L_, -,V1 nput optial signal Time basis Signal generator - iruit i.-- :optial sensor elerr*3nt (sensor 2b)! t V2.. : FG. 11 Analog omputation iruitry 92 Analog omputing element (ACE 2b) 921 -L.l i -1-l l t t ii t Transformed eletrial output signal d \JJ.... =... '-<,J;;.. Ul 'Jl =... '"""'..., '"""' e rj'j. -..a-.. b ""-l

14 Configurable Analog Blok (CAB) 125 Appliation speifi iruitry nteronnet iruit d \JJ.... =... '-<,J;;.. Ul 135 Analog memory iruitry 14 Digital ontrol iruitry 'Jl =... '"""'..., '"""' to/from interonnet iruit 32 FG. 12 e rj'j. -..a-.. b ""-l

15 nput signal r ,.., \ Appliation speifi iruitry \ 125 Programmable 151 Programmable bandpass filter 1 peak detetor 1. Programmable Programmable bandpass filter 2 peak detetor 2 Programmable - Programmable r bandpass filter 3 peak detetor 3.. Programmable - Programmable., bandpass filter n peak detetor n L, 128 Analog memory \ 135 iruitry Programmable 153. analog memory 1 Programmable Programmable ' analog memory 2 analog memory 3.. Programmable analog memory n Output signals may be ombined). d \JJ.... =... '-<,J;;.. Ul 'Jl =... '"""',J;;....., '"""' 'l r 14 Digital ontrol iruitry - FG. 13 nteronnet iruit 13 e rj'j. -..a-.. b ""-l

16 Programmable bandpass filter 1 Vrp1 Appliation speifi iruitry Programmable peak detetor 1 157) 159 Vrpeak 125 Analog memory iruit Programmable analog memory < : Vp2 : : t ' r--1 d \JJ = '-<,J;;.. Ul nput signal 154 Vrn3 ";'" -::- Output signal 'Jl =... Ul """"..., """" -=- -::- -::- FG. 14 e rj'j. -..a Q ""-l

17 U.S. Patent May 24, 25 Sheet 16 of 21 US 6,898,97 B2 "'!"""" "- >. \!_ "'!""""'\ --j :.;:: ('"{ ::J - rn.s...+-' E - ::J > -7 QJ rn'u.2 o Ol "O > ns Lt) T C) - _. ro <( ::::J. O> - - (/J u..

18 U.S. Patent May 24, 25 Sheet 17 of 21 US 6,898,97 B2 CJ) Q) ) ::..}i <'.] a. ::1 + tu (.) (.) : UE-.. "t: Cl> "t ue-.. C)) j Q) E> Cj +._ a <l -e-..9. en r i CJ :i [> -;! T --m ::1. C) C - -en Fl1.E' + Clo. ) CJ - \...) LL \..) \..)

19 U.S. Patent May 24, 25 Sheet 18 of 21 US 6,898,97 B2 -m ::l.. ) - (/) >"' (J).2 >- O> > ->.. E o L.. - Q) m L.. - : -Cf) 1 - o L.. a... ro OJ w - CJ) t) (!) - u.. : t..., Q) :J rn en L.. (9 u "(3,_ Q).. -;:) ro.. a:i :: -ll

20 Analog omputation iruitry 42 d \JJ.... =... Analog omputation iruitry 42 '-<,J;;.. Ul '! J FG. 15d ji i = FG. 15e '='. ' rf.j. =-... \C "'""..., "'"" e \JJ. -..a Q ""-l

21 U.S. Patent May 24, 25 Sheet 2 of 21 US 6,898,97 B2. >'( a O> v; -:::J. : <O ).,...._..._,, v ) g"-a g t) (!) - LL '- Cl; e w - n i;;; O>

22 _, w l Float;"giJale <'----4 _ --, / ) 16 d \JJ.... =... "'""' \.-, i ' 1 Vx Row'n' Floating-gate Programming \ soure \.159 /,l! \ -"' H '\'...._,,'.! \.. / - \, '..... :.;l,'' ry'... _... '. :;J;::,".. fy) ' HfY \ Dn Vy 163 Row 1 drain./ programming soure Row 1 Signal out Vy 164 Row 'n' drain / programming soure '-<,J;;.. Ul 'Jl =... '"""'..., '"""' Vz \_165 Col 1 Gate Programming soure Vz Col 2 Gate Programming soure Vz Coln Gate Programming soure FG. 16 Row'n' Signal out e rj'j. -..a-.. b ""-l

23 1 FLOATG-GATE AALOG CRCUT CROSS REFERECE TO RELATED APPLCATOS This appliation laims the benefit of U.S. Provisional Patent Appliation Ser. o. 6/366,714 filed Mar. 22, 22, whih is inorporated herein by referene in its entirety. STATEMET REGARDG FEDERALLY SPOSORED RESEARCH OR DEVELOPMET The U.S. government may have a paid-up liense in this invention and the right in limited irumstanes to require the patent owner to liense others on reasonable terms as provided for by the terms of Grant o. EA awarded by the ational Siene Foundation of the U.S. FELD OF THE VETO The present invention generally relates to the field of analog iruits. More speifially it relates to programmable analog arrays that an be programmed at a transistor level. BACKGROUD AD PROR ART US 6,898,97 B2 Hardware design of a digital logi iruit is often initiated 25 by evaluating a prototype iruit that is programmed into a reonfigurable devie suh as a field programmable gate array (FPGA) or a programmable logi devie (PLD). While this design approah has ertain handiaps related to ost and optimal usage of logi elements, the advantages pro- 3 vided in using programmable devies for digital design has proved far more attrative and has been used by engineers for many years. To a large extent, the advantage of a digital programmable devie lies in its flexibility to permit interonnetion hanges to be arried out at a primitive level that 35 often extends down to the level of a logi gate, suh as a AD or an OR gate. This feature allows engineers to design and evaluate a wide variety of logi iruits using a single FPGA. n many situations, this level of design flexibility down to a logi gate is unneessary. For example, 4 ertain standard iruit onfigurations suh as flip-flops, ounters and registers an be pre-designed into an FPGA thereby freeing the designer of the task and/or skills needed to implement suh mundane funtions. These pre-designed iruits are typially referred to as maros, and suh maros 45 have been inorporated into several FPGAs, often in onjuntion with logi gate primitives that are also available for the digital designer. While not neessarily referred to as maros, digital memories have also been inorporated into several FPGAs albeit to a limited extent ditated by market needs and osts. Digital memories as standalone devies have proven to provide a large degree of iruit density at relatively low osts, and hene are often used as independent integrated iruit pakages loated external to an FPGA pakage. Unlike digital hardware design, analog hardware design involves a different set of requirements that are unique to analog iruits. Suh requirements inlude interonneting several disrete omponents suh as transistors, resistors, and apaitors to form a iruit with minimal parasiti parameters so as to obtain maximum bandwidth response. These disrete omponents have to be seleted from a wide variety of omponent values. For example, the value of a resistor for one iruit may be 1 ohms, while for a seond iruit it may be 1.45 kilo ohms. Aommodating suh a 65 variety of values in suh a variety of disrete omponents, to ater to flexible design of analog iruits inside a 2 programmable/reonfigurable integrated iruit is a hallenging task. This ondition has led to limited implementations of programmable devies in the analog domain. One suh devie is termed a field programmable analog array 5 (FPAA). Various manufaturers have sought a onvenient ompromise by providing pre-onfigured iruits inside FPAAs akin to FPGA maros. Suh pre-onfigured iruits inlude op amps, filters, and osillators. This approah has several 1 advantages in terms of optimizing spae inside integrated iruits, providing good iruit performane due to optimal layout, and allowing engineers who are relatively unskilled in analog iruit design to inorporate analog iruits into their designs by using interonnetions that an be onfig- 15 ured by programming the FPAA. 2 On the other hand, this approah has proved very limiting to analog designers desirous of using an FPAA to reate a design at a primitive level extending down to a transistor. Some manufaturers have sought to address this limitation by providing transistors, sometimes in array onfigurations, that an be programmably interonneted to eah other together with some disrete analog elements suh as resistors, that are also inorporated into an FPAA. The hoie of the type of transistors and their performane parameters is often a ompromise that is driven by the market and is often onstrained by semiondutor integration tehnology. While digital memory devies are very popular and widely available, analog memory devies are relatively obsure and are limited in their performane. Some manufaturers have utilized harge-storing elements suh as apaitors that are onfigured as arrays. The harge-levels inside the apaitors are often digital in nature where ertain harge-thresholds are utilized to represent binary as well as multi-level digital values. Typially, analog memory devies have been manufatured as standalone devies, and where integrated into FPAAs have provided limited performane harateristis. t is therefore desirable to provide a programmable analog devie that inorporates analog memory elements as well as disrete analog elements, speifially transistors, with maximum interonnet flexibility, programmable design parameters and optimal iruit density. t is even more desirable to integrate memory funtionality together with transistor omputational funtionality inside a single ommon element. When suh a ommon element, for example a transistor element that has analog storage apaity, is used independently or interonneted with other transistor elements 5 inside the FPAA, the resulting onfiguration an provide omputing as well as memory funtions in a ompat pakage. t is also desirable that various operating parameters of the transistor element, suh as voltage bias, urrent flow, gain, and analog memory values may also be program- 55 mable. This feature will provide a level of programmability that extends beyond traditional FPAAs where the design engineer typially programs the interonnetions inside the FPAA to reate an analog iruit, but is unable to further program other iruit parameters, suh as the operating 6 parameters of a transistor ontained in the analog iruit. SUMMARY OF THE VETO The present invention provides methods and systems for onfiguring a floating-gate transistor devie to perform a omputational funtion upon an input signal that is oupled into a floating-gate of the floating gate field-effet transistor, wherein the omputational funtion is dependent upon a

24 US 6,898,97 B2 3 harge that is programmed into the floating-gate of the floating-gate field effet transistor. Also provided is a onfiguration iruit that is used to onfigure iruit parameters of the floating gate field-effet transistor in order to perform the omputational funtion. 5 Another embodiment an be desribed as a method of using a floating-gate pfet as a omputation devie, the method omprising oupling an input signal into a floatinggate of the floating-gate pfet, and providing a harge at the floating-gate of the floating-gate pfet in order to produe 1 an output signal that is a mathematial ombination of the input signal and a weight that is proportional to the harge at the floating-gate. DESCRPTO OF THE DRAWGS Many aspets of the invention an be better understood with referene to the following drawings. The omponents in the drawings are not neessarily drawn to sale, emphasis instead being plaed upon learly illustrating the priniples of the present invention. Moreover, in the drawings, like referene numerals designate orresponding parts throughout the several views. FG. 1 illustrates a field programmable analog array (FPAA) inorporating the invention, implemented in an exemplary integrated iruit pakage that is programmable using one or more external programming devies. FG. 2 shows the main funtional bloks of the invention housed inside the FPAA of FG. 1. FG. 3 shows some funtional bloks inside one of the 3 main funtional bloks, the CAB matrix, of FG. 1. FG. 4 shows some funtional bloks inside a CAB iruit that is ontained in the CAB matrix of FG. 3. FG. 5 shows the layout, ross-setion, and iruit symbol of a floating-date pfet, one of several MOSFETS that may be used to form a matrix blok ontained inside the CAB iruit of FG. 4. FG. 6 shows a matrix iruit that is formed using the floating-date pfet of FG. 5. FGS. 7a and 7b illustrate embodiments of interonnet hardware that are inorporated inside the FPAA of FG. 1. FG. 8 shows floating-gate pfets interonneted to form a multiplier iruit that is used in the FPAA of FG. 1. FGS. 9, 1, and 11 are a set of illustrations provided in a hierarhial manner, to explain an exemplary transform imager appliation that has been implemented using the iruits ontained in FPAA of FG. 1. FGS. 12, 13, and 14 are a set of illustrations provided in a hierarhial manner, to explain an exemplary epstrum proessor using floating-gate transistors for a speeh proessing appliation, that has been implemented using the iruits ontained in FPAA of FG. 1. FGS. 15a, 15b, 15, 15d, 15e, and 15/illustrate iruitry that uses floating-gate pfets inorporated into the iruits ontained in the CAB iruit to provide an analog multipliation funtion oupled with adaptive gain. FG. 16 shows a matrix iruit formed of several floatinggate pfets, whih is used to illustrate an exemplary programming proedure to program a matrix. DETALED DESCRPTO OF THE PREFERRED EMBODMETS While the desription below refers to ertain exemplary embodiments, it is to be understood that the invention is not limited to these partiular embodiments. On the ontrary, the intent is to over all alternatives, modifiations and equivalents inluded within the spirit and sope of the invention as defined by the appended laims. Also, the terminology used herein is for the purpose of desription and not of limitation. The desription of several omponents of this invention has been arried out using figures drawn in a hierarhial fashion, wherein eah progressive figure provides greater details of a omponent than was provided in an earlier figure. FG. 1 illustrates a field programmable analog array (FPAA) 15 inorporating the invention, implemented in an exemplary integrated iruit pakage that is programmable using one or more external programming devies suh as programming devies 16 and 17. Programming devie 16 is an integrated iruit, whih for example, may be a digital memory C ontaining FPAA ontrol and onfiguration logi in the form of a software or firmware program that an be ommuniated to FPAA 15 via link 11. Programming devie 17 is a omputing devie, suh as a PC, a miroontroller iruit, a miroproessor iruit, or a dediated ontrol logi iruit that an be used alternatively to provide ontrol and onfiguration logi to FPAA15 via link 11. The term FPAA ontrol and onfiguration logi as used above, enompasses several ontrol and programming parameters, suh as shemati apture, boolean equation entry, and hardware desription languages. Examples of hardware desription languages inlude Verilog and very high speed integrated iruits (VHSC) hardware desrip- tion language (VHDL). FPAA 15 ommuniates its input/output (i/o) signals, whih may be analog as well as digital signals, to one or more external devies suh as devies 18 and 19. The analog signals are arried over analog links ontained inside 35 link 111, while the digital signals are arried over digital links ontained inside link 111. Devie 18 is an integrated iruit that reeives and/or transmits analog and/or digital signals from FPAA 15, and further proesses these signals if neessary. Devie 18 (as well as devie 16) may be 4 loated on the same printed iruit board that houses FPAA 15. The symboli representation of devie 19 as shown in FG. 1, is intended to enompass a variety of display, omputing, and/or ontrol devies. Suh devies inlude output devies, for example light emitting diodes, PC 45 monitors, transmitters, reeivers, and eletri motors; and input/output devies suh as PCs, miroontrollers, and ontrol iruits. n digital appliations, the proess of programming a programmable digital devie suh as an FPGA or a PLD, is 5 traditionally performed to implement pre-determined interonnetions between various logi elements inside the devie. This approah is also typially used in analog appliations to program onventional FPAAs. Unlike these traditional proesses, that are limited to implementing inter- 55 onnetions between elements inside programmable devies FPAA 15 not only permits setting up interonnetions between elements, but additionally permits programming one or more devie and/or iruit parameters inside FPAA 15 to enable analog iruit operation in several alternative 6 modes. t must be pointed out, that even though FG. 1 shows link 11 and the two programming devies 16 and 17 loated external to FPAA 15, it will be obvious to persons of ordinary skill in the art that many funtions of these ele- 65 ments an be inorporated into FPAA 15 if so desired. FG. 2 shows the main funtional bloks of the invention housed inside FPAA 15 of FG. 1. These bloks inlude a

25 US 6,898,97 B2 5 6 onfigurable analog blok (CAB) matrix 215, an analog input/output interfae iruit 22, and an FPAA ontrol and onfiguration iruit 225. Configurable analog blok (CAB) matrix 215 is onneted to the analog input/output interfae iruit 22 via link 212, and to FPAA ontrol and onfigu- 5 ration iruit 225 via link 26. FPAA ontrol and onfiguration iruit 225 is onneted to the analog input/output iruit 22 via link 27, and to external programming devies via link 11. FPAA ontrol and onfiguration iruit 225 uses link 26 to program the interonnetions as well as onfigure iruit parameters of the analog iruit elements ontained in onfigurable analog blok (CAB) matrix 215. The onfigurable analog blok (CAB) matrix 215 will be explained in further detail using FG. 4 and other figures. n ertain appliations, FPAA ontrol and onfiguration iruit 225 may use link 27 to program the interonnetions and operating parameters of the i/o devies ontained inside analog input/output iruit 22. Programming interonnetions inludes, for example, setting up an interonnetion 2 between the output terminal of a line driver and an output pin of FPAA 15, after seleting a suitable line driver and a suitable output pin. The seletion of the line driver as well as the output pin may be manually arried out by an operator, or may be automatially performed by the program. Setting up operating parameters inludes, for example, setting the gain, the output drive urrent, the input sensitivity, and/or the bandwidth of op amps that have been onfigured as either reeivers or drivers onneted to i/o pins. Link 28 from FPAAontrol and onfiguration iruit 225 may be used to set up interonnetions for other iruitry, suh as digital logi iruits that may be optionally housed inside FPAA Analog input/output interfae iruit 22 may inorporate several devies suh as analog op amps, omparators, input reeivers, and line drivers that ouple analog signals into link 211. Link 211 represents the analog links ontained inside link 111 shown in FG. 1. Analog input/output inter- 4 fae iruit 22 may also inlude other interfae devies suh as an analog-to-digital onverter that may be used to transmit a signal out of FPAA 15, or a digital-to-analog onverter that may be used to reeive a signal into FPAA 15. nteronnet iruit 32 performs several funtions, two of whih are exemplified by the bloks drawn in dashed lines. The ontents of these bloks will be desribed in more detail using other figures. "Programmable hardware for implementing iruit interonnetions" blok 31 may be used for example, to route signals from FPAA ontrol and onfiguration iruit 225 (shown in FG. 2) to set up interonnetions between elements that are loated inside eah of the individual CAB bloks. t may also be used, under program ontrol of the FPAA ontrol and onfiguration iruit 225, to provide interonnetions for one or more signals from one CAB to another through links 319, 32, 321 and 322. "Programmable hardware for setting up iruit parameters" blok 32, may be used under program ontrol of the FPAA ontrol and onfiguration iruit 225, to onfigure for example, the iruit parameters of various elements, digital as well as analog, loated inside one or more CABs. FG. 4 shows the funtional bloks inside CAB 315 of FG. 3. Appliation speifi iruitry 415, analog omputation iruitry 42, analog memory iruitry 43, and digital ontrol iruitry 435 that are onneted to interonnet iruit 425 via links 419, 423, 421, and 422, are four examples of funtional bloks that may be ontained in CAB 315. t must be pointed out that though shown as distintly funtional bloks, several funtions suh as omputation and memory, may be jointly performed by a ommon element, and therefore may be inorporated into a ommon blok. For example, bloks 42 and 43 may in some instanes, be replaed by one ommon blok that performs both funtions onurrently. Similarly, the digital ontrol iruitry blok 1 may also be merged into other bloks or may be eliminated altogether in ertain ases. Appliation speifi iruitry 415 ontains pre-onfigured iruits-analog and/or digital, that an be used independently or in onjuntion with elements loated inside other 15 bloks of CAB 315. Analog omputation iruitry 42 ontains omputing elements; while analog memory iruitry 43 ontains analog memory elements. Both these bloks show a matrix blok 63 whih will be explained in 25 3 detail using other figures. Digital ontrol iruitry 435 is an optional blok that may be used in onjuntion with digital iruits loated inside appliation speifi iruitry 415. One example of suh a iruit housed in the digital ontrol iruitry 435 is a state-mahine program to operate a digital iruit loated in appliation speifi iruitry 415. nteronnet iruit 425 performs several funtions in manner similar to that performed by the interonnet iruit 325 of FG. 3. For example, it may provide interonnetion for one or more signals from the appliation speifi iruitry 415 to the analog omputation iruitry 42 using links 419 and 423. Similar interonnetions an also be provided to other bloks of CAB 315, using links 421 and 422. nteronnet iruit 425 also permits routing of ontrol signals used to onfigure the interonnetivity of elements inside the various bloks. For example, it an be used to onfigure the onnetions of analog elements in the analog omputation iruitry 42. nteronnet iruit 425 is also used to route signals that are used to set up operating parameters of analog iruits inside, for example, analog memory iruit 43. Suh signals may, for example, be analog voltages and/or analog urrents. t will be understood that interonnetion iruit 425 of FG. 4 and interonnetion iruit 32 of FG. 3 are 45 shown as two distint bloks for illustration purposes only. n many appliations, these two bloks will be implemented in an integrated manner at predefined loations inside an FPAA. FG. 5 shows the layout, ross-setion, and iruit symbol 5 of a floating-date pfet, one of several MOSFETS and other types of floating-date transistors that an be used to form the matrix 63 blok shown inside analog omputation iruitry 42 and analog memory iruitry 43 of FG. 4. A floating gate transistor is so named beause it inorporates a floating 55 gate that is a polysilion gate surrounded by Si 2. When an inherent or externally-injeted harge is present on the floating gate, the harge is stored permanently beause the floating gate is ompletely surrounded by an insulator. This property of a floating gate transistor permits its use as an 6 analog memory element wherein the stored harge onstitutes the ontents of the analog memory. Additionally, the harge on the floating gate an be also used to ontrol the soure-drain urrent flow in the floatinggate transistor, beause the floating gate harge ats as a gate 65 bias-voltage. This urrent-ontrol property an be used in reating iruits for various omputing funtions suh as swithing, multipliation, and addition. The property also

26 7 provides linear and non-linear signal transformation harateristis for the floating-gate transistor that an be exploited in several appliations. Drawing attention to FG. 5, signals on the floating gate terminal 563, as well as the soure and drain terminals 561 US 6,898,97 B2 and 564 of pfet 52 apaitively ouple into hannel 567 by way of the floating gate 566. The urrent through hannel 567 is dependent on the harge at the floating gate 566. To add harge, Fowler-ordheim tunneling may be used to tunnel eletrons off the floating gate. This tunneling is 1 arried out via tunneling apaitor 571. To remove harge, hot-eletron injetion may be used. While inreasing harge at the floating gate 566 auses the hannel urrent to derease, dereasing harge at the floating gate auses the hannel urrent to inrease. By ontrolling the amount of harge present at the floating gate 566, floating-gate pfet 52 an be onfigured to operate as a swith, with "saturated" urrent flow between drain and soure produing a swith O ondition, while urrent flow blokage between drain and soure produing 2 a swith OFF ondition. pfet 52 an also be onfigured to operate in a partially-onduting mode, by suitably adjusting the amount of harge present at the floating gate 566. Drawing attention to FG. 6, whih inorporates floatinggate pfet 52 as a nodal element, it an be seen that suh floating-gate pfets an be arranged in the form of a matrix 63. Matrix 63 an be programmed to operate in several modes. Examples of some modes inlude operation as a swithing matrix, a memory matrix, and a omputing matrix. FPAA ontrol and onfiguration iruit 225 (shown in FG. 2) is used together with interonnet iruit 32 (shown in FG. 3) and interonnet iruit 425 (shown in FG. 4) to provide the onfiguration logi to program matrix 63 for operating in a desired mode. n general, the programming operation involves setting up interonnetions in matrix 63, followed by programming eah nodal element to operate in an appropriate mode. For example, if matrix 63 has to be programmed as a swithing matrix, the gate, soure, and drain terminals of the various pfets an be suitably interonneted to eah other (interonnetion not shown) followed by programming of eah nodal element, suh as pfet 52, to operate as a swithing element. Typially, programming pfet 52 as a 45 swithing element may involve adjusting the harge at the floating gate to ause the pfet to operate in either an O or an OFF ondition. The analog voltages and/or urrents needed to perform the harge adjustment will be provided and/or ontrolled by the FPAA ontrol and onfiguration 5 iruit 225 (shown in FG. 2) in onjuntion with interonnet iruit 32 (shown in FG. 3) and interonnet iruit 425 (shown in FG. 4). t will be understood that in a typial appliation this harge adjustment has to be done on eah of the pfets individually. The harge adjustment, whih is 55 done to enable ertain pfets as O swithes and others as OFF swithes, may be arried out at one instane in time or may be arried out at regularly or irregularly seleted instanes in time. FG. 7a illustrates one embodiment of the programmable hardware inorporated inside interonnet iruit 32 of FG. 3 and interonnet iruit 425 of FG. 4. A sequene of operations in programming an FPAA suh as FPAA 15, will, in one example operation, involve using the "programmable hardware for implementing iruit interonnetions" 65 blok 31 to set up interonnetions for various elements suh as the floating gate arrays of array 63 (shown in FG. 8 6), followed by using the "programmable hardware for setting iruit parameters" blok 32, to set up iruit parameters suh as adjusting the floating gate harge of a floating-gate transistor. This sequene of operations an be 5 reiteratively applied if so desired. Blok 31 shows a asaded swith iruit that an be programmed to onnet terminal 71 to one of several terminals suh as terminals 72, 73, 74, 75, and 76 by operating one of the swithes in the asaded swith iruit. A swith of the asaded swith iruit may omprise an analog swith (for example, a MOSFET swith) or a digital swith (for example, a deoder iruit), the swith being operable under program ontrol of the FPAA ontrol and onfiguration iruit 225 (shown in FG. 2) by use of a 15 ontrol voltage to operate the analog swith, a logi level to operate the digital swith. A swith may also omprise a fusible link. The fusible link is operable under program ontrol of the FPAA ontrol and onfiguration iruit 225 (shown in FG. 2) by use of a programming voltage applied to a seleted fusible link to ause it to melt and provide an open-iruit. A fusible link that is melted (blown) onstitutes an "off" onnetion, while one that is not blown onstitutes an "on" onnetion. Operation of blok 31 an be further explained using an 25 example wherein it is desired that D2 (drain terminal of floating-gate transistor 52 in FG. 6) that is provided at input terminal 71, be onneted to Dl (drain terminal of floating-gate transistor 615 in FG. 6) that is provided at terminal 72. To perform this operation, FPAA ontrol and 3 onfiguration iruit 225 (shown in FG. 2) provides a ontrol signal to swith 77 thereby ausing swith 77 to operate and provide a onnetion path between D2 and Dl. t will be understood, that D2 is used here merely as an example, and multiple nodes/terminals of iruitry on- 35 tained in FPAA 15 an be onneted to multiple input terminals that are assoiated with swithing iruits suh as the swithing iruit shown in FG. 7a. Suh nodes/ terminals will typially inlude voltage/ground buses, transistor terminals, apaitor terminals, as well as input, output, 4 and input/output pin terminals of the FPAAintegrated iruit pakage. Blok 32 shows a asaded swith iruit that an be programmed to onnet S2 (soure terminal of floating-gate pfet 52 in FG. 6) at input terminal 711 to one of several programming soures by operating one of the swithes in the asaded swith iruit. Examples of these programming soures inlude, but are not limited to, a fixed voltage soure, a variable voltage soure, a fixed/variable urrent soure, an AC signal soure, and a ground onnetion. A swith may omprise an analog swith (for example a MOSFET devie) or a fusible link, that an be operated under program ontrol of the FPAA ontrol and onfiguration iruit 225 (shown in FG. 2). This program ontrol may omprise use of a ontrol voltage to operate an analog swith or a programming voltage to onfigure a fusible link. A fusible link that is blown onstitutes an "off" onnetion, while one that is not blown onstitutes an "on" onnetion. t will be understood that the asaded swith arrangement shown in bloks 31 and 32, are for example pur- 6 poses only. Several other iruits, arranged in a similar asaded onnetion or in other non-asaded swith onnetions, an be used to provide interonnetions to other terminals ontained inside FPAA 15. For example, bloks 31 and 32 may ontain a seond set of asaded swith iruits that an be used to onnet PG2 (programgate terminal of floating-gate pfet 52 in FG. 6) to PGl (program-gate terminal of floating-gate transistor 615 in

27 US 6,898,97 B2 9 FG. 6), or to onnet PG2 to a variable voltage soure for harging the floating-gate of floating-gate pfet 52. t will also be understood that many alternative iruits an be utilized to provide the swithing funtions of bloks 31 and 32. For example, while swithes 77, 78, 79, 5 712, 713 are shown as a serially-onneted hain of singlepole-double-throw swithes, the asaded series of multiple swithes an be replaed by a single swith having a multi-throw arrangement. Furthermore, while some appliations may permit the 1 programmed swith positions of the swithes shown in FG. 7a to remain undisturbed when power is removed from FPAA 15, in other appliations the swith positions may require fresh programming eah time after FPAA power-up. The use of fusible links suh as desribed with referene to 15 FG. 7a, is generally assoiated with one-time programming proedures, and using these links in FPAA 15 may be used to haraterize FPAA 15 as a one-time programmable devie. FG. 7b illustrates a seond embodiment of the programmable hardware inorporated inside interonnet iruit 32 of FG.3 and interonnet iruit 425 of FG. 4. Swithing matrix bloks 31 and 32 perform funtions that are equivalent to those that are performed by bloks 31 and 32 of FG. 7a. This equivalene will be reognized by persons of ordinary skill in the art. FG. 8 shows floating-gate pfets 615 and 52 that have been interonneted at their soure, gate, or drain terminals, and suitably programmed (using the interonnet iruitry illustrated in FGS. 7a and 7b) to perform a mathematial omputing funtion, in this partiular example-a multipliation funtion. Other pairs of floating-gate pfets loated in matrix 63 (shown in FG. 6) may also be suitably programmed suh that matrix 63 as a whole, is onfigured to 35 operate in a omputing matrix mode. The explanation of the multipliation funtion uses material from the following douments, whih are inorporated herein by referene in their entirety: "Mel-frequeny epstrum enoding in analog floating-gate iruitry" by Paul D. Smith, Matt Kui, Rihard Ellis, Paul Hasler, & David Anderson. "Programmable ontinuous-time floating-gate Fourier proessor" by Matt Kui, AiChen Low, & Paul Hasler. Drawing attention to FG. 8, the soure terminals of pfets 615 and 52 are shown onneted to two transistors and 695. These two devies (whih may be a part of the appliation speifi iruitry 415 of FG. 4) are used to as drain-indued-barrier-lowering (DEL) devies. DEL devies are used to inrease iruit linearity by way of soure degeneration in pfets 615 and 52. f suh a 5 degeneration is unneessary, DEL devies 685 and 695 may be omitted. The DEL devies may also be used to provide appropriate feedbak signals to permit stable ontinuous floating-gate urrents in pfet floating-gate devies, allowing implementation of useful Hebbian-type learning rules. 55 A generalized equation to define a floating-gate pfet with a DEL devie onneted to its soure terminal an be stated as ls=ls W exp(-fl Viny) where s is the subthreshold nfet or pfet hannel urrent in saturation for a hange in the FET's gate saturation voltage; ls is a bias urrent; Wis 6 a weight that is a soure urrent measure of the floating-gate harge; and VY is the exponential slope of this element between apaitive input and hannel urrent. Referring to FG. 8, the iruit onstitutes a four-quadrant multiplier where a differential input signal (fl Vin) is multi- 65 plied by a stored weight value. This stored weight value is the differene of the programmed values of the floating-gate harges that have been set in pfets 615 and 52. The weight term may be dependent on several fators suh as the size of the floating-gate, the harging proess, and the amount of harge present at the floating gate. The iruit of FG. 8 ouples two floating-gate pfets 52 and 615 in a way that subtrats out their ommon-mode responses, and the output drain urrent l u, an be defined by the equation l u,=ls (W+ exp(-fl Viny)+w- exp(-fl Vj V )), assuming that the input voltages are within the linear ringe V. This equation an be simplified by approximating the expnential terms as linear funtions, by l urls (W+ + w-)+s (W+ -w-) fl Viny, where w+ and w- are the weights orresponding to pfets 52 and 615 that are provided with Vin + and Vin - voltages. The output urrent reflets the four-quadrant produt of the input voltages multiplied by the weights. t is relevant to point out that the multiplier iruit of FG. 8 performs a "multipliation" funtion between a signal and a weight, unlike a "mixing" funtion between two signals that is typially arried out in a mixer iruit. The multipliation funtion an be broadly defined as multiplying an input signal with a stored value/weight. This stored value an be onsidered a gain term. So if the gain term is zero, and the inoming signal is multiplied by this zero value, the output signal from the multiplier iruit will be of negligible amplitude. FGS. 9, 1, and 11 are a set of illustrations provided in a hierarhial manner, to explain an exemplary transform imager appliation that has been implemented using the 3 iruits ontained in FPAA 15. This explanation uses material from the following doument: "A Matrix transform mager allowing high-fill fator" by Paul Hasler, Abhishek Banlyopadhyay, and Paul Smith, and this doument is inorporated herein by referene in its entirety. FG. 9 shows some of the funtional bloks that are shown in FG. 4, onfigured in one sample embodiment as the transform imager; while FGS. 1 and 11 show the iruitry of FG. 9 in more detail. FG. 9 shows CAB 95 ontaining the main funtional bloks used in the transform 4 imager appliation, and the relevant interonnetions that are programmed into the interonnet iruit 925. FG. 1 shows the CAB 95 of FG. 9 in more detail. Drawing attention to FG. 1, appliation speifi iruitry 915 ontains an array of time basis elements 923 (time basis 1... n), and an array of optial sensor elements 924. Eah of the time basis elements operates as a funtion generator providing a signal that is available throughout a orresponding olumn of the array of optial sensor elements 924. For example, time basis 2 provides a signal that is available to sensor elements 2a, 2b,... 2m of its olumn. Time basis elements may omprise several iruits, some examples inluding an osillator, a pattern generator, or an analog memory element. These elements may be optionally onfigured and ontrolled via digital signals that are provided by digital ontrol iruitry 935 (shown in FG. 9) through interonnet iruit 925. The array of optial sensor elements 924 is formed of individual optial sensors, eah of whih uses a minimum of additional omponents in its immediate viinity, thereby allowing reation of an optial sensor matrix array that provides optimal optial fill-spae. Fill-spae is typially desribed by a fill-fator, whih is defined as a ratio of the available optial image sensor area to the overall area used by the optial proessing iruitry. Eah optial sensor an be used as a pixel proessing element that outputs a urrent proportional to the multipliation of the time basis signal and a photosensor urrent.

28 US 6,898,97 B Analog omputation iruitry 92 ontains an array of analog omputing elements 926 where the size of the array mathes that of the array of optial sensor elements 924, with eah analog omputing element (ACE) orresponding to a unique optial sensor element in the array of optial sensor elements 924. An ACE is formed of one or more floating-gate transistors that aept a urrent from an optial sensor element and transform this urrent through various proesses suh as multipliation, swithing, and levelshifting to provide image transformation at a pixel level. FG. 11 shows details of one set of exemplary elements that are a part of the arrays loated inside the appliation speifi iruitry 915 and the analog omputation iruitry 92. Signal generator iruit 917 may be programmable to generate several signals. For example, it may generate a 15 low-frequeny sine wave that is fed into the orresponding olumn in the array of optial sensor elements 924. Optial sensor element 918 that is part of this olumn, and is used as an example element, aepts this signal at its gate terminals. The two transistors 931 and 932, whih may be floating-gate pfets or other types of transistors, are interonneted to an optial sensor diode 941, using the interonnet iruitry ontained inside FPAA 15 as was explained earlier. n this example iruit, the two transistors 931 and 932 are onneted as a differential-pair. 25 The input optial signal that is direted towards the optial sensor diode 941, auses an optial sensor diode urrent to be generated that is shared between the two transistors. The urrent sharing is dependent upon the gate voltages Vl and V2, present at the individual gates of the 3 two transistors at any given moment in time, oupled with any floating-gate harges that may be individually programmed at these two gates, if the two gates are floatinggate transistors. For the differential-pair onfiguration of transistors 931 and 932 operated with sub-threshold bias urrents (typially used in imaging appliations due to the presene of lowlevel image sensor urrents), the differential output urrent an be expressed as: "( k(v1 - V2)) i - 12 = fsensortan1\--u-t- 35 an output signal to a orrespondingly-onneted programmable peak detetor. For example, programmable bandpass filter 151 provides a signal into programmable peak detetor 152. The high-end and low-end orner frequenies of eah programmable bandpass filter an be suitably set, indepen- 4 dent of the settings in other programmable bandpass filters. This feature allows the array of programmable bandpass filters to be programmed to operate with a frequeny spaing that is user-seletable to be linear, non-linear, otavewhere k is the gate oupling effiieny into the transistor 45 surfae potential (typially.6 to.8v), and Ur is k T/q. f V 1 - V 2 inputs are suh that the transistors operate in their linear range, k(v1 - V2)) Ji - 12 = fsensor ( U_T_, whih is the produt of the sensor output urrent and the differential voltage input. The differential output urrents are summed and further proessed in analog omputing element 921 (loated inside the analog omputation iruitry 92 of FG. 1), whih is a floating-gate transistor. The floating-gate transistor may be onfigured as an analog memory element, or as a non-linear omputing iruit to arry out mathematial transformation operations. t an be understood that the transform imager appliation desribed using FGS. 9, 1, and 11 provides pixel-level image proessing in a modularly-expandable matrix onfiguration, with various omputing parameters that are 65 programmable using floating-gate transistors inside the FPAA 15. This onfiguration allows formation of dense optial sensor arrays beause additional iruitry, suh as the analog omputing element 921 an be loated away from the optial sensor area. Some example appliations for this kind of proessing inlude image filtering, omputing spatial 5 derivatives, and 2D spatial transforms. Matrix transforms an be generally desribed by the formula Y =ArPB, where P denotes a row and olumn array of pixels, A is a transform matrix orresponding to the transform arried out upon an image plane by a basis 1 funtion, and B is a transform matrix that is subsequently arried out. As an example implementation using the iruit shown in FG. 1, the values of A may be applied via the time basis iruits 923, while the values of B may be stored in the analog omputation iruitry 92. FGS. 12, 13, and 14 are a set of illustrations provided in a hierarhial manner of an exemplary epstrum proessor using floating-gate transistors for a speeh proessing appliation. The proessor, whih will be desribe below, has been implemented using iruits ontained in FPAA The desription uses material from the following doument, whih is inorporated herein by referene in its entirety: "Mel-frequeny epstrum enoding in analog floating-gate iruitry" by Paul D. Smith, Matt Kui, Rihard Ellis, Paul Hasler, & David Anderson. FG. 12 shows some of the funtional bloks that are shown in FG. 4, onfigured in one sample embodiment as a epstrum proessor; while FGS. 13 and 14 show the iruitry of FG. 12 in more detail. Drawing attention to FG. 13, appliation speifi iruitry 125 ontains an array of programmable bandpass filters 126 (programmable bandpass filters 1... n), and an array of programmable peak detetors 127 (programmable peak detetors 1... n). Eah of the programmable bandpass filters reeives an input signal that is provided in ommon to all filters, and provides oriented, or logarithmi. Eah of the programmable peak detetors, whih an be programmed using a ontrol voltage to provide a userseletable frequeny response, provides a signal to a orrespondingly-onneted programmable analog memory ontained in programmable analog memory array 128 of 5 analog memory iruitry 135. For example, programmable peak detetor 152 provides a signal into programmable analog memory 153. nteronnet iruitry 13, whih is one embodiment of the interonnet iruitry 425 of FG. 4, is used for example, 55 to set up interonnetions in the analog memory iruit 135; and to program parameters suh as weights in the floating gate transistors ontained inside analog memory iruit 135 as well as appliation speifi iruitry 125. The interonnetions and programming is arried out using signals 6 generated by digital ontrol iruitry 14 as well as signals that may be inorporated inside the interonnet iruitry 13. The onept of epstral analysis involves deomposing an input signal into ertain omponent parameters. However, speeh signals are non-stationary in the time-domain. Thereby, the time-frequeny spetrum of speeh signals is not onstant. Traditional approahes to epstral analysis

29 US 6,898,97 B2 13 involves the use of short-term Fourier analysis using disrete Fourier transform (DF1) and inverse DFT. Mel-epstrum analysis, whih is a variant of epstrum analysis, is implemented traditionally in the disrete domain, by splitting a signal into ritial band energies and then performing the 5 disrete osine transform (DCT) on the sequene of ritial band energies. The band splitting iruitry typially inludes analog-to-digital onversion iruitry. FGS. 12, 13, and 14 illustrate an analog approah using floating-gate transistor arrays as mel-epstrum omputational bloks. By using a purely analog approah, digitization noise that may be introdued during analog-to-digital onversion is eliminated. Analog proessing also allows proessing of higher-order properties of signals. One example of suh a higher-order property would be the high-frequeny information that is present in speeh signals 15 during friatives and/or diphthongs. The spetral ontent of these transitive sounds appear as a spike in the time-domain. A signal spike in the time-domain equates to a broadspetrum signal in the frequeny-domain. Capturing suh spikes, whih provide valuable speeh information, is rela- 2 tively easier to implement in the time-domain. t will be reognized, that FGS. 12, 13, and 14 are being used merely to illustrate one exemplary appliation. This approah and its variants may be used in several other appliations, suh as speeh reognition iruits inorporat- 25 ing analog epstrum, analog hidden Markov models (HMM), and vetor quantization (VQ) iruits. FG. 14 shows an exemplary iruit ontaining programmable bandpass filter 151, whih is ontained in the array of programmable bandpass filters 126, onneted to program- 3 mable peak detetor 152, whih is ontained in the array of programmable peak detetors 127. Also shown is programmable analog memory 152 that is ontained in the programmable analog memory array 128. The programmable bandpass filter 151 used here is a apaitively oupled urrent 35 onveyor (C 4 ) inorporating one or more differential stages. For the sake of brevity, only one half of the differential iruit is shown in programmable bandpass filter 151. t will be understood that in the differential iruit, positive input terminal 154 will have a orresponding negative input 4 terminal that is not shown in FG. 14. Also, positive output signal line 156 will have a orresponding negative output signal line that is not shown. The high-end and low-end orner frequenies an be programmed by adjusting the bias urrents in the various transistors of the iruit. Suitable 45 appliation of bias voltages upon voltage terminals labeled Vrpl, Vrp2, Vrp3, Vrnl, Vrn2, and Vrn3 are used to adjust the bias urrents, suh bias voltages being provided through the interonnet iruit 13. Programmable peak detetor 152 omprises a retifier 5 element, for example FET 157 that is onfigured as a diode, together with a apaitor 159. FET 158, whih is onneted in parallel with apaitor 159, onstitutes a variable resistor whose resistane an be programmed via a voltage Vrpeak. The value of the R-C ombination of apaitor 159 and FET 158 an be programmed to set the high-end orner frequeny for utoff of the signal in the programmable peak detetor 152. Programmable analog memory 152 uses two floating-gate transistors shown in this example iruit onneted to provide a multiplier funtion as was explained with referene to FG. 8. This allows the output signal of programmable peak detetor 152 to be multiplied by a suitable weight that is programmed into the floating-gate transistors by using the interonnet iruit 13. FGS. 15a, 15b, 15, 15d, 15e, and 15 illustrate iruitry that uses floating-gate pfets inorporated into the analog 14 omputation iruitry 42 (shown in FG. 4) to provide an analog multipliation funtion together with adaptive gain. Suh a funtion is useful in many appliations, for example, low-power analog adaptive filtering and neural networks. The desription uses material from the following doument, whih is inorporated herein by referene in its entirety: "mproved orrelation learning rule in ontinuously adapting floating-gate arrays using logarithmi predistortion of input and learning signals" by Jeff Dugger and 1 Paul Hasler. FG. 15a shows a soure-degenerated pfet 17, whih when operated in a sub-threshold mode, produes a urrent that is a produt of an exponential funtion of its gate voltage and a weight fator. This urrent is defined by the equation: (Equation 1) where lb is the bias urrent, w is the weight funtion, and V ga is a voltage saling fator. f the amplitude of the gate voltage is made small enough, the equation above an be interpreted as a linear approximation, whereby pfet 17 an be operated as a transondutane amplifier with adaptive gain being provided by the weight funtion. The weight funtion may be tailored using a harge stored in the gate of pfet 17 by using a weight-update iruit. This weight-update iruit may inorporate a learning rule that is based on orrelations between the gate and drain voltages of pfet 17. One suh learning rule is defined by the equation: diw (Equation 2) T-= dit where, y, V g, Vg 1, and Vinj are onstants whih depend on devie parameters, bias onditions, and iruit onfigurations. While it is desirable to obtain a learning rule that is purely dependent on orrelations between the gate and drain voltages; it an be seen that the weight funtion in the learning rule equation above is influened by exponential funtions of the gate and drain voltages that are additionally dependent on the gate voltage variane as well as drain voltage variane. t is also desirable to make the gate voltage of pfet 17 small enough to obtain a linear model while simultaneously keeping it large enough to enounter orrelation behavior. Determining a suitable gate voltage setting that an satisfy these onfliting requirements may result in harmoni distortion that adversely affets the weight funtion. Suh harmoni distortions may be minimized by using a pre-distortion iruit onneted to the gate of pfet 17, while the effet of the drain voltage variane term on the weight funtion may be minimized by inorporating a drain non-linearity transform iruit onneted to the drain of 55 pfet 17. Sample pre-distortion iruits will be explained further using other figures. Drawing attention to the iruit of FG. 15a, pfet 17 is onfigured to operate with a floating-gate harge that is at an equilibrium ondition. This equilibrium ondition is reahed 6 while arrying out tunneling to add harge and hot-eletron injetion to remove harge from the floating-gate. The addition and removal of harge an our onurrently, fairly-onurrent, or in a sequential manner, suh ations being depending upon the iruit onfiguration into whih 65 pfet 17 is plaed. Various parameters ontribute to the total harge at the gate. This will be explained with referene to FG. 15b.

30 US 6,898,97 B2 15 The proess of arrying out both addition and removal of gate harges in suh a onurrent manner, leads to an unstable ondition for pfet 17 wherein the gate harge affets the soure-drain urrent to generate positive feedbak. This will our if pfet 17 is operated independent 5 of any other devies suh as pfet 171. Therefore, pfet 171 is onneted to pfet 17 to provide iruit stabilization. n ertain iruit onfigurations, pfet 171 may omprise a MOSFET that is used to provide a soure-follower iruit, while in some other appliations a floating-gate MOSFET 1 suh as pfet 171 of FG. 15a may be used to provide a degenerated floating gate iruit. The injetion urrent, inj' during harge equilibrium has a non-linear dependene upon the voltages present at the soure, drain and gate terminals of pfet 17. This non- 15 linear dependene allows use of the iruit as a multiplier, whih is one of several omputational funtions that an be exploited in omputational appliations. Suh omputational appliations inlude for example, weight adaptation where the weight is a funtion of the gate harges that an 2 be suitably manipulated, and analog memory where the variable harge equates to a variable stored analog value. FG. 15b illustrates harateristis of the floating-gate harge in pfet 17 of FG. 15a. The total harge Q 1 g equals a harge that is provided to the gate through apaitor Cg and 25 a floating-gate harge that is set via tunneling and hoteletron injetion. This is further elaborated by the floatinggate voltage equation where V 1 g omprises two terms that are assoiated with the stored harge at the gate, and a third term that is assoiated with the harge that is provided by an 3 input signal via Cg. Referring bak the desription of FG. 15a where predistortion iruits were mentioned, FG. 15 illustrates pfet 17 with a gate pre-distortion iruit 191, a drain non-linearity transform iruit 192, and a soure non- 35 linearity transform iruit 193. These iruits are explained further with referene to FGS. 15d and 15e. FG. 15d illustrates one exemplary embodiment of a gate pre-distortion iruit onneted to the gate of pfet 17. The pre-distortion iruit omprises a urrent mirror funtion that provides a voltage input into the gate of pfet 17. This gate voltage is defined by the following equation: (Equation 3) where V mg is hosen in orrespondene with V ga to anel the exponential dependene of the output urrent on the input signal, as desribed in equation 1. FG. 15e illustrates one exemplary embodiment of a drain non-linearity transform iruit onneted to the drain of 5 pfet 17 to minimize drain voltage variane terms that affet the weight value. The drain pre-distortion iruit inludes transistors 176, 177, and 178. The equation for the drain voltage Vd an be defined as: er ur Vmd = ---. Cwarp k (Equation 4) 55 t is desirable to set e=e (1 +e ), where e is an error signal used to drive learning and equation 6 an be orrespondingly interpreted as: (Equation 5) A hart of de urrent value versus drain voltage amplitude orresponding to various distortion fators is then used to 16 determine a pre-distortion fator that an then be inorporated into the iruit of FG. 15. FG. 15/ shows a blok diagram representation of a omputation iruit using the iruitry explained with referene to FGS. 15a, 15b, 15, 15d, and 15e, that may be used in several appliations. A weight adaptation iruit omprised of non-linear multiplier 193 may be used to produe a non-linear multipliation funtion. The multiplier funtion is inherent to the operation of pfet 17 in FG. 15, whih is one example iruit. Multiplier 193 produes a non-linear output signal that ontains produt terms related to a first input signal and a seond input signal. f for example, the first signal is an input signal x, and the seond input signal is an error signal e, the non-linear output signal may be stated by an exemplary equation,f(x)=a x 2 +b xe+ e 2. As an be seen this equation has a first order term (b xe), as well as seond order (a x 2, e 2 ) produt terms. t will be understood that several other suh equations, wherein additional higher-order terms that are raised to powers of "n" (other than 1 and 2 as in the example equation), for example x 3, may be used to provide non-linear funtionality. t an be understood that multiplier 193 an thus be used to obtain various polynomial funtions of an input signal and an error signal over time, due to the non-linear funtionality of the injetion urrent in the floating-gate pfet 17. f it is desired that this non-linear relation between the input and error signals be redued solely to the term bxe, the other polynomial terms have to be eliminated. This elimination may be performed by inorporating the drain nonlinearity transform iruit 192 and the soure linearity transform iruit 193 explained earlier, resulting in a pure multipliation between the input and error signals. ntegrator 194 performs an averaging operation on the results of multiplier 193, produing various statistial funtions of the input and error signals provided to multiplier 193. Multiplier 196 produes an output signal that is a produt of the input signal fed into it, and a seond signal that is derived from integrator 194 of the weight adaptation 4 iruit. This multipliation funtion may also be termed as a tap-weight for use in an adaptive filter funtion or as a synapse for use in a neural network struture beause it provides the neessary multipliation of an inoming signal by a signal-dependent adaptive parameter, whih is the key 45 feature ommon to both adaptive and neural signal proessing systems. FG. 16 shows a matrix iruit 16 formed of several floating-gate pfets, whih an be used to illustrate an exemplary programming proedure to program a matrix. t an be notied that the individual terminals of these floatinggate pfets have been pre-onfigured with some interonnetions to one another, or to voltage soures, suh as the soure-bias voltage. FG. 16 provides one example wherein the interonnetions of a matrix iruit do not neessarily have to be onfigured using the "programmable hardware for implementing iruit interonnetions" blok 31 (shown in FG. 7a). Blok 31 as well as "programmable hardware for setting iruit parameters" blok 32 (also shown in FG. 7a) may be used in a seletive manner to 6 arry out other operations as will be desribed below. n the exemplary iruit of FG. 16, swithes 161and162 may be a part of the "programmable hardware for implementing iruit interonnetions" blok 31, while swithes 163, 164, 165, 166, 167, 168, and 169 may be a part of the 65 "programmable hardware for setting iruit parameters" blok 32. Drawing attention to swithes 161 and 162 whih are similar in funtionality, eah swith omprises a double

31 US 6,898,97 B pole onfiguration where the positions of the two poles are omplementary to one another. This onfiguration permits a drain onnetion suh as Dl, to be routed out as a "Row 1 signal out" by default. When neessary, swith 161 an be operated to isolate the path to the "Row 1 signal out" terminal, and Dl may be onneted to swith 163 instead. Programming a floating-gate pfet inorporates several operations. The first step omprises seleting a partiular pfet that is to be programmed. This seletion proess may be explained by using pfet 615 as an example. Swith 161 is ativated to allow Dl to onnet into swith 163. Swith 163 is ativated to onnet Dl into a "row 1 drain programming soure" that may omprise a voltage level that permits pfet 615 to be plaed in a onduting state that allows programming the floating-gate. The "row 1 drain programming soure" may inorporate various voltage soures. One example voltage soure may generate pulses of varying width and/or varying amplitudes to ause hot-eletron injetion to our. Swith 162 as well as other similar swithes that are 2 assoiated with the drain rows other than drain row 1, are ativated to disonnet the rows from their respetive signal output lines. Swith 164 (and other swithes assoiated with the drain onnetions of other rows) is left undisturbed, thereby onneting all drain rows other than drain row 1 to a voltage soure Vy. The value of Vy is seleted to ause eah of the pfets (other than pfet 615) to remain in a non-onduting state. Swith 165 is then ativated to onnet the gate of pfet 615 (as well as gates of other pfets in olumn 1) to a "Col 1 gate programming soure," whih may omprise a lowvoltage DC soure. This low-voltage DC soure may be set to an optimal injetion voltage to program pfet 615. Other swithes, suh as swithes 166 & 167 are left undisturbed, thereby onneting all the gate olumns, exept gate olumn 35 1, to a suitable voltage soure Vz that plaes all pfets other than pfet 615 in a non-programmable state. When tunneling is to be performed for removing eletrons from the floating-gate of pfet 615, swith 168 is ativated to allow the floating-gate row assoiated with pfet 615 to 4 onnet into a "row 1 floating-gate programming soure," whih generate a suitable programming voltage level. Swith 165 as well as other swithes assoiated with other floating-gate rows, are set to onnet all gate rows to a voltage soure that permits tunneling to our. 45 Verifiation of aurate floating-gate programming may be arried out in several ways. One way would omprise monitoring the drain urrent of the pfet that was seleted for programming. For example the drain urrent of pfet 615 may be monitored in a monitoring iruit inorporated 5 into the "row 1 drain programming soure." Alternatively, the drain urrent of pfet 615 may be monitored be setting swith 161 to route the drain urrent out via the "row 1 signal out" onnetion. f the monitoring iruit indiates an improper level of floating-gate harge, the programming 55 proedure may be reursively repeated until the desired harge levels are ahieved. While the above-mentioned example explained the priniples of programming a single pfet, it will be apparent to persons of ordinary skill in the art, that in alternative 6 programming approahes, several pfets may be seleted for programming simultaneously. The seletion may be arried out by appropriate ontrol signals applied to an entire row, an entire olumn, multiple rows, or multiple olumns. For example, in one ase a seletion ontrol signal may be applied to row 3 together with a seond seletion signal that is applied simultaneously to olumn 8. n a seond ase a seletion ontrol signal may be applied to rows 2, 3, 4, and 6 simultaneously, with a seond seletion ontrol signal applied to olumn 3. This type of programming allows multiple devies of the array to be programmed 5 simultaneously, and is partiularly appliable when "global" programming of parameters, suh as a reset ondition, or a pre-set ondition is used to bring multiple devies of an array into idential operating onditions. An example of a 1 reset ondition may omprise tunneling of several pfets to remove floating-gate harges on the seleted devies. t should be emphasized that the above-desribed embodiments of the present invention are merely possible examples of implementations and are merely set forth for a lear understanding of the priniples of the invention. Many variations and modifiations may be made to the above- 15 desribed embodiment of the invention without departing substantially from the spirit and priniples of the invention. For example, while an FPAA has been used in this desription merely as a onvenient way to desribe the priniples of the invention, it will be appreiated by those skilled in that art that this invention may be implemented in iruitry outside suh an integrated iruit. This may involve assembling a floating-gate pfet and its assoiated iruitry if any, upon a printed iruit board. This floating-gate pfet may be assembled as a disrete devie rather than fabriated upon 25 the substrate of an integrated iruit. t may also be implemented in an integrated iruit that may not be referred to traditionally as a programmable devie-for example, it may be inorporated into an appliation speifi C (ASC), or a standard C that houses other 3 non-programmable iruitry. All suh modifiations and variations are intended to be inluded herein within the sope of the present invention and proteted by the following laims. We laim: 1. An image proessing iruit omprising: a signal generator onfigured to generate a time basis signal; an optial sensor element omprising a differential pair of transistors and an optial sensor diode, the optial sensor element onfigured to reeive the time basis signal and an input optial signal, and further onfigured to generate a differential output eletrial signal that is proportional to the produt of an amplitude of the time basis signal at a first instane in time and an amplitude of the input optial signal at the first instane in time; an analog omputing element omprising a floating-gate pfet onfigured to perform a mathematial transform operation upon the differential output eletrial signal from the optial sensor element at the first instane in time; and an interonnet iruit that is programmable to provide an interonnetion between the differential pair of transistors and the optial sensor diode, is programmable to provide an interonnetion between the differential pair of transistors and a gate terminal of the floating-gate pfet, and is further programmable to provide a floating harge in the floating-gate pfet of the analog omputing element. 2. The image proessing iruit of laim 1, wherein the analog omputing element omprises an array of floatinggate pfets, and wherein the floating-gate pfet is a part of the array of floating-gate pfets. 3. The image proessing iruit of laim 2, wherein the 65 floating-gate pfet is onfigured to operate as an analog memory element upon providing the floating harge into the floating-gate of the floating-gate pfet.

32 US 6,898,97 B The image proessing iruit of laim 2, wherein the the first floating-gate FET to at least one of a first terminal mathematial transform operation omprises multiplying the of the seond floating-gate FET, an input pin of the PAA, an output eletrial signal from the optial sensor element by a output pin of the PAA, a voltage supply, and a ground weight, and wherein the weight is proportional to the floating harge that is programmed into the floating-gate of the The PAA of laim 11, wherein the interonnet iruit onnetion. floating-gate peet. is further programmable to interonnet a gate terminal of 5. A epstral proessor, omprising: the first floating-gate FET to one of a fixed voltage soure a programmable bandpass filter onfigured to provide a and the ground onnetion for setting a floating gate harge programmable frequeny response to an input signal on the first floating-gate FET. that is oupled into the programmable bandpass filter; The PAA of laim 1, wherein the swithing matrix a programmable peak detetor that is programmed using mode omprises at least one of the first and seond floatinggate FETs operating as an analog swithing element of the a ontrol voltage to provide a user-seletable frequeny response; onfigurable analog matrix. a programmable analog memory omprising a floatinggate pfet, the floating-gate pfet onfigured to provide a programmable analog memory value, the programmable analog memory ommuniatively oupled to the programmable bandpass filter; and an interonnet iruit that is programmable to provide the ommuniative oupling between the programmable analog memory and the programmable bandpass filter, and is further programmable to provide a floating harge in the floating-gate pfet, the floating harge being the programmable analog memory value. 6. The epstral proessor of laim 5, wherein the programmable analog memory omprises an array of floatinggate pfets, and wherein the floating-gate pfet is a part of the array of floating-gate pfets. 7. The epstral proessor of laim 6, wherein the floatinggate pfet is onfigured to operate as an analog omputing element by programming a harge into the floating-gate of the floating-gate pfet. 8. The epstral proessor of laim 6, wherein the programmable bandpass filter is a apaitively oupled urrent 35 onveyor iruit. 9. A programmable analog array (PAA) omprising: a onfigurable analog matrix having a first floating-gate field effet transistor (FET) and a seond floating-gate FET, the onfigurable analog matrix being onfigurable 4 to operate in one of a plurality of matrix modes; and an interonnet iruit that is programmable to onfigure the onfigurable analog matrix to operate in the one of a plurality of matrix modes, and wherein the interonnet iruit is further programmable to provide a float- 45 ing harge in at least one of the first and seond floating-gate FETs. 1. The PAA of laim 9, wherein the plurality of matrix modes omprises one of a swithing matrix mode, a memory matrix mode, and a omputing matrix mode. 11. The PAA of laim 1, wherein the interonnet iruit The PAA of laim 1, wherein the memory matrix mode omprises at least one of the first and seond floatinggate FETs operating as an analog memory element of the onfigurable analog matrix. 15. The PAA of laim 1, wherein the omputing matrix mode omprises at least one of the first and seond floatinggate FETs operating as an analog omputing element of the onfigurable analog matrix. 16. The PAA of laim 15, wherein the analog omputing element provides an analog multipliation funtion ompris- 25 ing an input signal multiplied by a floating-gate harge programmed into the at least one of the first and seond floating-gate FETs. 17. The PAA of laim 9, wherein the interonnet iruit omprises at least one of an analog swith, a digital swith, 3 and a fusible link. 18. A method of onfiguring a programmable analog array (PAA), the method omprising: providing in the PAA, a onfigurable analog matrix having a first floating-gate field effet transistor (FET) and a seond floating-gate FET, the onfigurable analog matrix being onfigurable to operate in one of a plurality of matrix modes; programming an interonnetion between a first terminal of the first floating-gate field effet transistor (FET) and at least one of a first terminal of the seond floatinggate FET, an input pin of the PAA, an output pin of the PAA, a voltage supply, and a ground onnetion; and programming an interonnetion between a gate terminal of the first floating-gate FET and one of a fixed voltage soure and the ground onnetion for setting a floating gate harge on the first floating-gate FET. 19. The method of laim 18, the method further omprising: operating the PAA in a matrix mode omprising one of a swithing matrix mode, a memory matrix mode, and a 5 omputing matrix mode. is further programmable to interonnet a first terminal of * * * * *