TPIC3322L 3-CHANNEL COMMON-DRAIN LOGIC-LEVEL POWER DMOS ARRAY

Transcription

1 Low r DS(on)....6 Ω Typ High-Voltage Outputs...6 V Pulsed Current...5 A Per Channel Fast Commutation Speed Direct Logic-Level Interface description SOURCE GATE SOURCE SOURCE3 D PACKAGE (TOP VIEW) GATE GND DRAIN GATE3 The is a monolithic logic-level power DMOS transistor array that consists of three isolated N-channel enhancement-mode DMOS transistors configured with a common drain and open sources. The is offered in a standard 8-pin small-outline surface-mount (D) package and is characterized for operation over the case temperature range of 4 C to 5 C. schematic diagram DRAIN 6 Q Q Q3 8 Z Z 5 GATE GATE GATE3 Z3 D SOURCE 3 SOURCE 4 SOURCE3 7 GND absolute maximum ratings over operating case temperature range (unless otherwise noted) Drain-to-source voltage, V DS V Source-to-GND voltage V Drain-to-GND voltage V Gate-to-source voltage, V GS ± V Continuous drain current, each output, all outputs on, T C = 5 C A Continuous source-to-drain diode current, T C = 5 C A Pulsed drain current, each output, I max, T C = 5 C (see Note and Figure 5) A Single-pulse avalanche energy, E AS, T C = 5 C (see Figure 4) mj Continuous total power dissipation at (or below) T C = 5 C (see Figure 5) W Operating virtual junction temperature range, T J C to 5 C Operating case temperature range, T C C to 5 C Storage temperature range, T stg C to 5 C Lead temperature,6 mm (/6 inch) from case for seconds C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : Pulse duration = ms and duty cycle = %. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 995, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS 7565

2 electrical characteristics, T C = 5 C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V(BR)DSX Drain-to-source breakdown voltage ID = 5 µa, VGS = 6 V VGS(th) Gate-to-source threshold voltage ID = ma, VDS = VGS V V(BR) VDS(on) VF VF(SD) Reverse drain-to-gnd breakdown voltage (across D) Drain-to-source on-state voltage Forward on-state voltage, GND-to-drain Forward on-state voltage, source-to-drain Drain-to-GND current = 5 µa V ID =.75 A, See Notes and 3 ID =.75 A, See Notes and 3 VGS = 5 V, IS =.75 A, VGS =, See Notes and 3 and Figure V.8 V.85 V VDS = 48 V, TC = 5 C.5 IDSS Zero-gate-voltage drain current VGS = TC = 5 C.5 IGSSF Forward gate current, drain short circuited to source VGS = 6 V, VDS = na IGSSR Reverse gate current, drain short circuited to source VSG = 6 V, VDS = na Ilkg Leakage current, drain-to-gnd VDGND = 48 V TC = 5 C.5 TC = 5 C.5 VGS = 5 V, TC = 5 C.6.7 ID =.75 A, rds(on) Static drain-to-source on-state resistance D See Notes and 3 and Figures 6 and 7 T C = 5 C.94 gfs Forward transconductance VDS = V, ID =.5 A,.75.9 S See Notes and 3 and Figure 9 Ciss Short-circuit input capacitance, common source 5 45 Coss Short-circuit output capacitance, common source VDS = 5 V, VGS =, 6 75 Crss Short-circuit reverse transfer capacitance, f = MHz, See Figure common source 3 4 NOTES:. Technique should limit TJ TC to C maximum. 3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. source-to-drain and GND-to-drain diode characteristics, T C = 5 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT trr(sd) Reverse-recovery recovery time IS =.375 A, di/dt = A/µs, QRR Total diode charge See Figures and 4 VGS =, VDS =48V V, Z, Z, Z3 3 D 85 Z, Z, Z3.3 D.9 µa µa Ω pf ns µc POST OFFICE BOX DALLAS, TEXAS 7565

3 resistive-load switching characteristics, T C = 5 C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 8 6 td(off) Turn-off delay time VDD = 5 V, RL = 67 Ω,, tr = ns, 4 tr Rise time tf = ns, See Figure 4 8 tf Fall time 3 6 Qg Qgs(th) Qgd Total gate charge Threshold gate-to-source charge Gate-to-drain charge VDS = 48 V, ID =.375 A, VGS = 5 V, See Figure 3 LD Internal drain inductance 5 LS Internal source inductance ns.4.5 nc..4 Rg Internal gate resistance.5 Ω thermal resistance RθJA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Junction-to-ambient thermal resistance, See Note 4 All outputs with equal power RθJC Junction-to-case thermal resistance 44 NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink. 3 nh C/W PARAMETER MEASUREMENT INFORMATION.5 VDS = 48 V VGS = TJ = 5 C Z, Z, and Z3 Only Reverse di/dt = A/µs IS Source-to-Drain Diode Current A Shaded Area = QRR IRM 5% of IRM trr(sd) t Time ns IRM = maximum recovery current NOTE A. The above waveform represents D in shape only. Figure. Reverse-Recovery-Current Waveform of Source-to-Drain Diode POST OFFICE BOX DALLAS, TEXAS

4 PARAMETER MEASUREMENT INFORMATION VDD = 5 V RL VDS tr tf Pulse Generator Rgen 5 Ω VGS 5 Ω DUT CL = 3 pf (see Note A) VGS td(on) tf 5 V V td(off) tr VDD VDS VDS(on) TEST CIRCUIT NOTE A: CL includes probe and jig capacitance. VOLTAGE WAVEFORMS Figure. Resistive-Switching Test Circuit and Voltage Waveforms -V Battery. µf 5 kω Current Regulator.3 µf VDS Same Type as DUT VDD = 48 V 5 V VGS Qgs(th) Qg Qgd IG = µa DUT Gate Voltage Time IG Current- Sampling Resistor ID Current- Sampling Resistor TEST CIRCUIT VOLTAGE WAVEFORM Figure 3. Gate-Charge Test Circuit and Voltage Waveform 4 POST OFFICE BOX DALLAS, TEXAS 7565

5 PARAMETER MEASUREMENT INFORMATION VDD = 5 V 4. mh tw tav 5 V Pulse Generator (see Note A) 5 Ω VGS ID VDS DUT VGS ID V IAS (see Note B) Rgen V 5 Ω VDS V(BR)DSX = 6 V Min V TEST CIRCUIT Non-JEDEC symbol for avalanche time NOTES: A. The pulse generator has the following characteristics: tr ns, tf ns, ZO = 5 Ω. B. Input pulse duration (tw) is increased until peak current IAS =.5 A. VOLTAGE AND CURRENT WAVEFORMS Energy test level is defined as E AS I AS V (BR)DSX t av 9 mj, where t av avalanche time. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS Gate-to-Source Threshold Voltage V V GS (th) GATE-TO-SOURCE THRESHOLD VOLTAGE JUNCTION TEMPERATURE VDS = VGS ID = µa ID = ma TJ Junction Temperature C r DS(on) Static Drain-to-Source On-State Resistance Ω STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE JUNCTION TEMPERATURE.5 ID =.75 A VGS = 4.5 V VGS = 5 V TJ Junction Temperature C Figure 5 Figure 6 POST OFFICE BOX DALLAS, TEXAS

6 TYPICAL CHARACTERISTICS r DS(on) Static Drain-to-Source On-State Resistance Ω STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE DRAIN CURRENT.9 TJ = 5 C VGS = 4.5 V VGS = 5 V ID Drain Current A DRAIN CURRENT DRAIN-TO-SOURCE VOLTAGE VGS = 4 V VGS = 3.6 V VGS = 3 V.4.. ID Drain Current A.5 TJ = 5 C VGS =. V VDS Drain-to-Source Voltage V Figure 7 Figure 8 Percentage of Units % DISTRIBUTION OF FORWARD TRANSCONDUCTANCE Total Number of Units = 639 VDS = V ID =.5 A TJ = 5 C Drain Current A I D DRAIN CURRENT GATE-TO-SOURCE VOLTAGE VDS = 5 V TJ = 5 C TJ = 75 C TJ = 5 C TJ = 5 C TJ = 4 C VGS Gate-to-Source Voltage V gfs Forward Transconductance S Figure 9 Figure 6 POST OFFICE BOX DALLAS, TEXAS 7565

7 TYPICAL CHARACTERISTICS C Capacitance pf CAPACITANCE DRAIN-TO-SOURCE VOLTAGE Ciss Coss Crss VGS = f = MHz TJ = 5 C Ciss() = 58 pf Coss() = 4 pf Crss() = 78 pf Source-to-Drain Diode Current A I SD. SOURCE-TO-DRAIN DIODE CURRENT SOURCE-TO-DRAIN VOLTAGE VGS = TJ = 5 C TJ = 5 C TJ = 4 C TJ = 5 C TJ = 75 C VDS Drain-to-Source Voltage V.. VSD Source-to-Drain Voltage V Figure Figure VDS Drain-to-Source Voltage V DRAIN-TO-SOURCE AND GATE-TO-SOURCE VOLTAGE GATE CHARGE ID =.375 A TJ = 5 C See Figure 3 VDS = 3 V VDS = V VDS = V VDS = 48 V VGS Gate-to-Source Voltage V trr Reverse-Recovery Time ns REVERSE-RECOVERY TIME REVERSE di/dt Z, Z, and Z3 D VGS = VDS = 48 V IS =.375 A TJ = 5 C See Figure.5.5 Qg Gate Charge nc Reverse dl/dt A/µs Figure 3 Figure 4 POST OFFICE BOX DALLAS, TEXAS

8 THERMAL INFORMATION Maximum Drain Current A ID MAXIMUM DRAIN CURRENT DRAIN-TO-SOURCE VOLTAGE TC = 5 C DC Conditions ms ms 5 µs µs Maximum Peak Avalanche Current A 4 3 MAXIMUM PEAK AVALANCHE CURRENT TIME DURATION OF AVALANCHE See Figure 4 TC = 5 C TC = 5 C I AS.. VDS Drain-to-Source Voltage V Less than % duty cycle Figure 5.. tav Time Duration of Avalanche ms Figure 6 8 POST OFFICE BOX DALLAS, TEXAS 7565

9 THERMAL INFORMATION NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE PULSE DURATION Normalized Junction-to-Ambient Thermal Resistance Ω θja R... DC Conditions d =.5 d =. d =. d =.5 d =. d =. Single Pulse tw tc ID..... tw Pulse Duration s Device mounted on FR4 printed-circuit board with no heat sink. NOTE A: ZθA(t) = r(t) RθJA t w pulse duration t c cycle time d duty cycle t w t c Figure 7 POST OFFICE BOX DALLAS, TEXAS

10 POST OFFICE BOX DALLAS, TEXAS 7565

11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Instruments Incorporated