3.3 V 1:10 LVCMOS PLL Clock Generator

Transcription

1 Freescale Semiconductor Technical Data 3.3 V 1:10 LVCMOS PLL Clock Generator The is a 3.3 V compatible, 1:10 PLL based clock generator and zero-delay buffer targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking and computing applications. With output frequencies up to 250 and output skews less than 120 ps the device meets the needs of the most demanding clock applications. The is specified for the temperature range of 0 C to +70 C. Features 1:10 PLL based low-voltage clock generator Supports zero-delay operation 3.3 V power supply Generates clock signals up to 250 Maximum output skew of 120 ps Differential LVPECL reference clock input External PLL feedback Drives up to 20 clock lines 32-lead LQFP packaging 32-lead Pb-free Package Available Pin and function compatible to the MPC958 Functional Description Rev 5, 10/2004 LOW VOLTAGE 3.3 V LVCMOS 1:10 PLL CLOCK GENERATOR FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 The utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the requires the connection of the QFB output to the feedback input to close the PLL feedback path (external feedback). With the PLL locked, the output frequency is equal to the reference frequency of the device and VCO_SEL selects the operating frequency range of 50 to 125 or 100 to 250. The two available post-pll dividers selected by VCO_SEL (divide-by-2 or divide-by-4) and the reference clock frequency determine the VCO frequency. Both must be selected to match the VCO frequency range. The internal VCO of the is running at either 2x or 4x of the reference clock frequency. The has a differential LVPECL reference input along with an external feedback input. The is ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The is fully 3.3 V compatible and requires no external loop filter components. The inputs (except ) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the outputs can drive one or two traces giving the devices an effective fanout of 1:16. The device is packaged in a 7x7 mm 2 32-lead LQFP package. Freescale Semiconductor, Inc., All rights reserved.

2 Q k & Ref VCO Q1 Q2 Q3 PLL Q4 Q5 FB_IN 25 k FB Q6 Q7 PLL_EN VCO_SEL 3 25 k Q8 Q9 BYPASS MR/OE 25 k QFB Figure 1. Logic Diagram Q2 Q3 Q4 Q Q6 Q Q7 Q Q8 QFB Q9 VCO_SEL _PLL FB_IN BYPASS PLL_EN MR/OE Figure Lead Pinout (Top View) 2 Freescale Semiconductor

3 Table 1. Pin Configurations Number Name Type Description, Input LVPECL PECL reference clock signal FB_IN Input LVCMOS PLL feedback signal input, connect to QFB VCO_SEL Input LVCMOS Operating frequency range select BYPASS Input LVCMOS PLL and output divider bypass select PLL_EN Input LVCMOS PLL enable/disable MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset Q0 9 Output LVCMOS Clock outputs QFB Output LVCMOS Clock output for PLL feedback, connect to FB_IN Supply Ground Negative power supply () _PLL Supply PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin _PLL. Refer to APPLICATIONS INFORMATION for details. Supply Positive power supply for I/O and core. All pins must be connected to the positive power supply for correct operation. Table 2. Function Table Control Default 0 1 PLL_EN 1 Test mode with PLL bypassed. The reference clock () is substituted for the internal VCO output. is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. Selects the VCO output. (1) BYPASS 1 Test mode with PLL and output dividers bypassed. The reference clock () is directly routed to the outputs. is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. 1. PLL operation requires BYPASS = 1 and PLL_EN = 1. Selects the output dividers. VCO_SEL 1 VCO 1 (High frequency range). f REF = f Q0 9 = 2 f VCO VCO 2 (Low output range). f REF = f Q0 9 = 4 f VCO MR/OE 0 Outputs enabled (active) Outputs disabled (high-impedance state) and reset of the device. During reset the PLL feedback loop is open. The VCO is tied to its lowest frequency. The length of the reset pulse should be greater than one reference clock cycle (). Table 3. Absolute Maximum Ratings (1) Symbol Characteristics Min Max Unit Condition Supply Voltage V V IN DC Input Voltage V V OUT DC Output Voltage V I IN DC Input Current ±20 ma I OUT DC Output Current ±50 ma T S Storage Temperature C 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Freescale Semiconductor 3

4 Table 4. General Specifications Symbol Characteristics Min Typ Max Unit Condition V TT Output Termination Voltage 2 V MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 ma C PD Power Dissipation Capacitance 10 pf Per output C IN Input Capacitance 4.0 pf Inputs θ JA LQFP 32 Thermal resistance junction to ambient JESD 51-3, single layer test board JESD 51-6, 2S2P multilayer test board Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min θ JC LQFP 32 Thermal resistance junction to case MIL-SPEC 883E Method Table 5. DC Characteristics ( = 3.3 V ± 5%, T A = 0 C to 70 C) Symbol Characteristics Min Typ Max Unit Condition V IH Input High Voltage V LVCMOS V IL Input Low Voltage 0.8 V LVCMOS V PP Peak-to-Peak Input Voltage () 250 mv LVPECL (1) V CMR Common Mode Range () V LVPECL V OH Output High Voltage 2.4 V I OH = 24 ma (2) V OL Output Low Voltage (3) 1. V CMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V CMR range and the input swing lies within the V PP (DC) specification. 2. The is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of V TT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. 3. The output levels are compatible to the MPC958 output levels. 4. Inputs have pull-down resistors affecting the input current V V I OL = 24 ma I OL = 12 ma Z OUT Output Impedance Ω I IN Input Current (4) ±200 µa V IN = or I CC_PLL Maximum PLL Supply Current ma _PLL Pin I CCQ Maximum Quiescent Supply Current ma All Pins 4 Freescale Semiconductor

5 Table 6. AC Characteristics ( = 3.3 V ± 5%, T A = 0 C to 70 C) (1) Symbol Characteristics Min Typ Max Unit Condition f REF Input reference frequency 2 feedback (2) PLL mode, external feedback 4 feedback (3) Input reference frequency in PLL bypass mode (4) f VCO VCO lock frequency range (5) f MAX Output Frequency 2 feedback (3) feedback (4) AC characteristics apply for parallel output termination of 50 Ω to V TT PLL feedback (high frequency range) requires VCO_SEL = 0, PLL_EN = 1, BYPASS = 1 and MR/OE = PLL feedback (low frequency range) requires VCO_SEL = 1, PLL_EN = 1, BYPASS = 1 and MR/OE =0. 4. In bypass mode, the divides the input reference clock. 5. The input frequency f REF must match the VCO frequency range divided by the feedback divider ratio FB: f REF =f VCO FB. 6. V CMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V CMR range and the input swing lies within the V PP (AC) specification. Violation of V CMR or V PP impacts static phase offset t ( ). 7. Calculation of reference duty cycle limits: DC REF,MIN = t PW,MIN f REF 100% and DC REF,MAX = 100% DC REF,MIN. 8. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation in PLL zero-delay mode. 9. Output duty cycle is DC = (0.5 ± 400 ps f OUT ) Þ 100%. For example, the DC range at f OUT = 100 is 46% < DC < 54%. T = output period. 10. Refer to APPLICATIONS INFORMATION for a jitter calculation for other confidence factors than 1 σ and a characteristic for other VCO frequencies db point of PLL transfer characteristics PLL locked PLL locked PLL locked PLL locked V PP Peak-to-peak input voltage () mv LVPECL (6) V CMR Common Mode Range () V LVPECL t PW,MIN Input Reference Pulse Width (7) t ( ) Propagation Delay (static phase offset) to FB_IN f REF = 100 any frequency 2.0 ns t PD Propagation Delay (PLL and divider bypass) to Q ns t sk(o) Output-to-output Skew (8) 120 ps DC Output Duty Cycle (9) ps ps (T 2) 400 T 2 (T 2)+400 ps PLL locked t r, t f Output Rise/Fall Time ns 0.55 to 2.4 V t PLZ, HZ Output Disable Time 7.0 ns t PZL, LZ Output Enable Time 6.0 ns t JIT(CC) Cycle-to-cycle jitter 80 ps t JIT(PER) Period Jitter 80 ps t JIT( ) I/O Phase Jitter f VCO = 500 and 2 feedback, RMS (1σ) (10) f VCO = 500 and 4 feedback, RMS (1σ) BW PLL closed loop bandwidth (11) 2 feedback (3) 4 feedback (5) t LOCK Maximum PLL Lock Time 10 ms ps ps Freescale Semiconductor 5

6 APPLICATIONS INFORMATION Programming the The supports output clock frequencies from 50 to 250. Two different feedback divider configurations can be used to achieve the desired frequency operation range. The feedback divider (VCO_SEL) should be used to situate the VCO in the frequency lock range between 200 and 500 for stable and optimal operation. Two operating frequency ranges are supported: 50 to 125 and 100 to 250. Table 7. Configurations (QFB connected to FB_IN) illustrates the configurations supported by the. PLL zero-delay is supported if BYPASS =1, PLL_EN = 1, and the input frequency is within the specified PLL reference frequency range. Table 7. Configurations (QFB connected to FB_IN) Frequency BYPASS PLL_EN VCO_SEL Operation Ratio Output range (f Q0 9 ) VCO 0 X X Test mode: PLL and divider bypass f Q0 9 = f REF n/a Test mode: PLL bypass f Q0 9 = f REF n/a Test mode: PLL bypass f Q0 9 = f REF n/a PLL mode (high frequency range) f Q0 9 = f REF f VCO = f REF PLL mode (low frequency range) f Q0 9 = f REF f VCO = f REF 4 Power Supply Filtering The is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the A_PLL power supply impacts the device characteristics, for instance I/O jitter. The provides separate power supplies for the output buffers ( ) and the phase-locked loop (A_PLL ) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the _PLL pin for the. Figure 3 illustrates a typical power supply filter scheme. The frequency and phase stability is most susceptible to noise with spectral content in the 100 khz to 20 range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor R F. From the data sheet the I CC_PLL current (the current sourced through the _PLL pin) is typically 12 ma (20 ma maximum), assuming that a minimum of V must be maintained on the _PLL pin. R F = 5 15 Ω C F = 22 µf R F C F 10 nf nf _PLL Figure 3. _PLL Power Supply Filter The minimum values for R F and the filter capacitor C F are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 db for noise whose spectral content is above 100 khz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3 5 khz and the noise attenuation at 100 khz is better than 42 db. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Using the in Zero-Delay Applications Nested clock trees are typical applications for the. Designs using the as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. The external feedback option of the clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated). The maximum insertion delay of the device in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset, I/O jitter (phase or long-term jitter), feedback path delay and the output-to-output skew error relative to the feedback output. 6 Freescale Semiconductor

7 Calculation of Part-to-Part Skew The zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs of two or more are connected together, the maximum overall timing uncertainty from the common input to any output is: t SK(PP) = t ( ) + t SK(O) + t PD, LINE(FB) + t JIT( ) CF This maximum timing uncertainty consist of four components: static phase offset, output skew, feedback board trace delay, and I/O (phase) jitter: The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3σ) is assumed, resulting in a worst case timing uncertainty from input to any output of 214 ps to 224 ps relative to PCKL (f REF = 100, FB = ³4, t jit( ) = 8 ps RMS at f VCO = 400 ): t SK(PP) = [ 70ps...80ps] + [ 120ps...120ps] + [(8ps 3)...(8ps 3)] + t PD, LINE(FB) t SK(PP) = [ 214ps...224ps] + t PD, LINE(FB) Due to the frequency dependence of the I/O jitter, Figure 5 can be used for a more precise timing performance analysis. TCLK Common t(ý) t PD,LINE(FB) 20 I/O Phase Jitter versus Frequency Parameter: PLL Feedback Divider FB QFB Device 1 Any Q Device 1 t JIT( ) +t SK(O) t jit(f) [ps] RMS FB = ³ 2 FB = ³ 4 QFB Device2 +t ( ) t JIT( ) FCO Frequency [] Figure 5. Max. I/O Jitter versus Frequency Any Q Device 2 Figure 4. Max. Device-to-Device Skew Due to the statistical nature of I/O jitter a RMS value (1σ) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. Table 8. Confidence Factor CF CF Max. skew +t SK(O) t SK(PP) Probability of clock edge within the distribution ± 1σ ± 2σ ± 3σ ± 4σ ± 5σ ± 6σ Driving Transmission Lines The clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Freescale Semiconductor Application Note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to 2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the clock driver. However, for the series terminated case there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 6 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the clock driver is effectively doubled due to its capability to drive multiple lines. Freescale Semiconductor 7

8 In MPC958 Output Buffer 14 Ω MPC958 Output Buffe R S = 36 Ω R S = 36 Ω OutA OutB0 Voltage (V) OutA t D = In OutB t D = In 14 Ω R S = 36 Ω OutB Figure 6. Single versus Dual Transmission Lines The waveform plots in Figure 7 show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the. The output waveform in Figure 7 shows a step in the waveform. This step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: V L =V S (Z 0 (R S +R 0 +Z 0 )) Z 0 =50 Ω 50 Ω R S =36 Ω 36 Ω R 0 =14 Ω V L = 3.0 (25 ( ) =1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns) Time (ns) Figure 7. Single versus Dual Waveforms Since this step is well above the threshold region it will not cause any false clock triggering. However, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in Figure 8 should be used. In this case, the series terminating resistors are reduced such that, when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC958 Output Buffe 14 Ω R S = 22 Ω R S = 22 Ω 14 Ω + 22 Ω 22Ω = 50 Ω 50 Ω 25 Ω = 25 Ω Figure 8. Optimized Dual Line Termination Pulse Generator Z = 50 Ω DUT R T = 50 Ω R T = 50 Ω V TT Figure 9. AC Test Reference V TT 8 Freescale Semiconductor

9 t SK(O) 2 2 FB_IN V PP = 0.8V V CMR = 1.3V 2 The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 10. Output-to-Output Skew t SK(O) t (PD) Figure 11. Propagation Delay (t (PD), static phase offset) Test Reference t P 2 T 0 FB_IN DC = t P /T 0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 12. Output Duty Cycle (DC) Figure 13. I/O Jitter T JIT( ) = T 0 T 1 mean The deviation in t 0 for a controlled edge with respect to a T 0 mean in a random sample of cycles T N T JIT(CC) = T N T N+1 T N+1 T 0 T JIT(PER) = T N 1/f 0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 14. Cycle-to-Cycle Jitter The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 15. Period Jitter =3.3 V t F t R Figure 16. Output Transition Time Test Reference Freescale Semiconductor 9

10 PACKAGE DIMENSIONS PIN 1 INDEX D1/2 32 D X 0.20 H A-B D e/2 3 A, B, D E1/2 A 1 B F 6 E1 E 4 DETAIL G 8 17 E/2 DETAIL G F 4X C A-B D H SEATING PLANE C 28X e 9 D D/2 4 D DETAIL AD 32X 0.1 C PLATING BASE METAL b1 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. A A2 A1 (S) 8X (θ1 ) (L1) L DETAIL AD R R2 R R θ c GAUGE PLANE b SECTION F-F c M C A-B D 5 8 MILLIMETERS DIM MIN MAX A A A b b c c D D1 e E E BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC L L REF q q REF R R S 0.20 REF CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE 10 Freescale Semiconductor

11 NOTES Freescale Semiconductor 11

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