I AS Pulsed Avalanche Rating Figure 8 A dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5.0 V/ns
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1 N-Channel MOSFET Pb PTP6N65 PTA6N65 Lead Free Package and Finish Applications: Adaptor Charger SMPS Power Supply LCD Panel Power Features: RoHS Compliant Low ON Resistance Low Gate Charge Peak Current vs Pulse Width Curve Ordering Information PART NUMBER PACKAGE BRAND PTP6N65 TO-22 PTA6N65 TO-22F G D S V DSS R DS(ON) (Typ.) I D 65 V A TO-22 G D S Packages Not to Scale TO-22F G D S Absolute Maximum Ratings T C =25 o C unless otherwise specified Symbol Parameter PTP6N65 PTA6N65 Units V DSS Drain-to-Source Voltage (NOTE *1) 65 V I D Continuous Drain Current 6. 6.* I o C Continuous Drain Current Figure 3 A I DM Pulsed Drain V (NOTE *2) Figure 6 Power Dissipation W P D Derating Factor above 25 o C W/ o C Gate-to-Source Voltage ± 3 V E AS Single Pulse Avalanche Engergy L= mh 25 mj I AS Pulsed Avalanche Rating Figure 8 A dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5. V/ns T L T PKG T J and T STG Thermal Resistance Maximum Temperature for Soldering Leads at.63 in (1.6 mm) from Case for seconds Package Body for seconds Operating Junction and Storage Temperature Range 3 26 o C -55 to 15 * Drain Current Limited by Maximum Junction Temperature Caution: Stresses greater than those listed in the Absolute Maximum Ratings Table may cause permanent damage to the device. Symbol Parameter PTP6N65 PTA6N65 Units Test Conditions Drain lead soldered to water cooled heatsink, R JC Junction-to-Case PD adjusted for a peak junction temperature of +15 o C. o C/W R JA Junction-to-Ambient 62 1 cubic foot chamber, free air. Page 1 of 9 P P A PP P P P 1 A
2 OFF Characteristics TJ=25 o C unless otherwise specified BV DSS Drain-to-Source Breakdown Voltage V =V, I D =25μA BV DSS / T J BreakdownVoltage Temperature Coefficient, Figure V/ o C Reference to 25 o C, I D =25μA V DS =65V, =V I DSS Drain-to-Source Leakage Current μa V DS =52V, =V T J =125 o C Gate-to-Source Forward Leakage V I GS =+3V GSS na Gate-to-Source Reverse Leakage = -3V ON Characteristics TJ=25 o C unless otherwise specified R Static Drain-to-Source On-Resistance V DS(ON) GS =V, I D =2.5A Figure 9 and. (NOTE *4) (TH) Gate Threshold Voltage, Figure V V DS =, I D =25A gfs Forward Transconductance S V DS =3V, I D =6A (NOTE *4) Dynamic Characteristics Essentially independent of operating temperature C iss Input Capacitance =V C oss Output Capacitance V DS =25V pf f=1.mhz C rss Reverse Transfer Capacitance Figure 14 Q g Total Gate Charge VDD=325V Q gs Gate-to-Source Charge nc I D=6AVgs=V Q gd Gate-to-Drain ( Miller ) Charge Figure 15 Resistive Switching Characteristics Essentially independent of operating temperature t d(on) Turn-on Delay Time V DD =325V t rise Rise Time I D =6A ns t d(off) Turn-Off Delay Time =V t fall Fall Time R G =12 2
3 Source-Drain Diode Characteristics Tc=25 o C unless otherwise specified I S Continuous Source Current (Body Diode) A Integral pn-diode I SM Maximum Pulsed Current (Body Diode) A in MOSFET V SD Diode Forward Voltage V I S =6A, =V t rr Reverse Recovery Time ns =V Q rr Reverse Recovery Charge nc I F =6A, di/dt= A/μs Notes: *1. T J = +25 o C to +15 o C. *2. Repetitive rating; pulse width limited by maximum junction temperature. *3. I SD = 6 A, di/dt < A/μs, V DD < BV DSS, T J =+15 o C. *4. Pulse width < 38μs; duty cycle < 2%. 3
4 Z JC, Thermal Impedance (Normalized) E-6 Duty Factor 5% 2% % 5% 2% 1% single pulse Figure 2. Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case E-6 E-6 1E-3 E-3 E-3 1E+ Maximum Power Dissipation vs Case Temperature t p, Rectangular Pulse Duration (s) P DM t 1 t 2 NOTES: DUTY FACTOR: D=t1/t2 PEAK T J =P DM x Z JC x R JC +T C E+ Figure 3. Maximum Continuous Drain Current vs Case Temperature P D, Power Dissipation (W) TO-22F TO-22 I D, Drain Current (A) T T C, Case Temperature ( o C, Case Temperature ( o C) C) Figure 4. Typical Output Characteristics Figure 5. Typical Drain-to-Source ON Resistance vs Gate Voltage and Drain Current I D, Drain Current (A) PULSE DURATION = 25 μs DUTY FACTOR =.5% MAX, T C = 25 o C VGS =15V VGS = 6.5V VGS = 6.V VGS = 5.5V VGS = 5.V VGS = 4.5V RDS(ON), Drain-to-Source ON Resistance ( PULSE DURATION = μs DUTY FACTOR =.5% MAX T C = 25 o C I D = 18A I D = 12A I D = 6A I D = 2.5A V DS, Drain-to-Source Voltage (V) , Gate-to-Source Voltage (V) InPower Semiconductor Co., Ltd. Page 4 of 9 ITP6N65A/ITA6N65A Rev. A. Feb. 213
5 Figure 6. Maximum Peak Current Capability I DM, Peak Current (A) TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION FOR TEMPERATURES ABOVE 25 o C DERATE PEAK CURRENT AS FOLLOWS: I = 15 I TC 125 VGS = V 1 E-6 E-6 1E-3 E-3 E-3 1E+ E+ t p, Pulse Width (s) Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive Switching Capability I D, Drain-to-Source Current (A) PULSE DURATION = 38 μs DUTY CYCLE =.5% MAX VDS = 3 V o C +25 o C -55 o C I AS, Avalanche Current (A) STARTING T J = 25 o C STARTING T J = 15 o C 1 If R= : t AV = (L I AS )/(1.3BV DSS -V DD ) If R : t AV = (L/R) ln[i AS R)/(1.3BV DSS -V DD )+1] R equals total Series resistance of Drain circuit.1 1E-6 E-6 E-6 1E-3 E-3, Gate-to-Source Voltage (V) t AV, Time in Avalanche (s) R DS(ON), Drain-to-Source ON Resistance () Figure 9. Typical Drain-to-Source ON Figure. Resistance vs Drain Current PULSE DURATION = μs DUTY CYCLE =.5% MAX TC=25 C = V 12 R DS(ON), Drain-to-Source Resistance (Normalized) Typical Drain-to-Source ON Resistance vs Junction Temperature PULSE DURATION = μs.75 DUTY CYCLE =.5% MAX = V, I D = 2.5 A I D, Drain Current (A) T J, Junction Temperature ( o C) 5
6 BV DSS, Drain-to-Source Breakdown Voltage (Normalized) Figure 11. Typical Breakdown Voltage vs Figure 12. Junction Temperature.95 = V.7 I D = 25 μa (TH), Threshold Voltage (Normalized) = V DS I D = 25 μa Typical Threshold Voltage vs Junction Temperature T J, Junction Temperature ( o C) T J, Junction Temperature ( o C) Figure 13. Maximum Forward Bias Safe Figure 14. Operating Area Typical Capacitance vs Drain-to-Source Voltage I D, Drain Current (A). T J = MAX RATED T C = 25 o C Single Pulse. μs μ 1ms 1. C oss OPERATION IN THIS AREA = V, f = 1MHz MAY BE LIMITED BY R C DS(ON) iss = C gs + C gd C oss C ds + C T gd J = MAX RATED C rss = C gd.1 T C = 25 o C 1 C rss ms C, Capacitance (pf) C iss V DS, Drain-to-Source Voltage (V) V DS, Drain Voltage (V) Figure 15. Typical Gate Charge Figure 16. vs Gate-to-Source Voltage Typical Body Diode Transfer Characteristics, Gate-to-Source Voltage (V) V DS = 165V V DS = 325V V DS = 48V I D =6A I SD, Reverse Drain Current (A) +15 o C +25 o C -55 O C = V Q G, Total Gate Charge (nc) V SD, Source-to-Drain Voltage (V) InPower Semiconductor Co., Ltd. Page 6 of 9 ITP6N65A/ITA6N65A Rev. A. Feb. 213
7 TEST CIRCUITS AND WAVEFORMS D.U.T. + VDS L R G Driver V DD Same Type as D.U.T. * dv/dt controlled by R G * ISD controlled by pulse period * D.U.T.-Device Under Test Fig. 1.1 Peak Diode Recovery dv/dt Test Circuit (Driver) P.W. Period D= P. W. Period = V I FM, Body Diode Forward Current ISD (D.U.T.) di/dt I RM Body Diode Reverse Current Body Diode Recovery dv/dt VDS (D.U.T.) V DD Body Diode Forward Voltage Drop Fig. 1.2 Peak Diode Recovery dv/dt Waveforms 7
8 TEST CIRCUITS AND WAVEFORMS (Cont.) V DS R L V DS 9% V DD R G V D.U.T. % t D(ON ) Fig. 2.1 Switching Test Circuit t R t D(OFF) t F Fig. 2.2 Switching Waveforms Vdd C1 Rp C2 Same Type as D.U.T. V Q G V DS Q GS Q GD DUT 1mA V G Charge Fig Gate Charge Test Circuit Fig Gate Charge Waveform L V DS BV DSS R D V DD V D.U.T. t p IAS t p Time Fig. 4.1 Unclamped Inductive Switching Test Circuit Fig. 4.2 Unclamped Inductive Switching Waveforms InPower Semiconductor Co., Ltd. Page 8 of 9 ISD4N6A REV. B. Apr. 214
9 Disclaimers: Per Semiconductor Co., Ltd (IP) reserves the right to make changes without notice in order to improve reliability,function or design and to discontinue any product or service without notice. Customers should obtainthe latest relevantinformation before orders and should verify that such information is current and complete. All products are sold subject toip s terms and conditions supplied at the time of order acknowledgement. Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale,testing, reliability and quality control are used to the extent deems necessary to support this warrantee.except where agreed upon by contractual agreement, testing of all parameters of each product is not necessarily performed. Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs describedherein. Customers are responsible for their products and applications using IP s components. To minimize risk, customers must provide adequate design and operating safeguards. Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights,nor the rights of others. Reproduction of information in s data sheets or data books is permissible only if reproduction iswithout modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive businesspractice. Semiconductor Co., Ltd is not responsible or liable for such altered documentation. Resale of s products with statements different from or beyond the parameters stated by Semiconductor Co., Ltdfor that product or service voids all express or implied warrantees for the associated s product or service and is unfair anddeceptive business practice. Semiconductor Co., Ltd is not responsible or liable for any such statements. The device is electrostatic sensitive. Proper electrostatic discharge (ESD) protection shall be implemented to avoid damaging device. Life Support Policy: Semiconductor Co., Ltd s products are not authorized for use as critical components in life support devices or systems without the expressed written approval of Semiconductor Co., Ltd. As used herein: 1. Life support devices or systems are devices or systems which: a. are intended for surgical implant into the human body, b. support or sustain life, c. whose failure to perform when properly used in accordance with instructions for used provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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UNISONIC TECHNOLOGIES CO., LTD 11A, 9V N-CHANNEL POWER MOSFET DESCRIPTION The UTC 11N9 is a N-channel enhancement mode Power FET using UTC s advanced technology to provide customers with planar stripe
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FQPF7N60 FQPF7N60 600V N-Channel MOSFET April 2000 QFET TM General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe,
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UNISONIC TECHNOLOGIES CO., LTD 4A, 600V N-CHANNEL POWER MOSFET DESCRIPTION The UTC 4N60 is a high voltage power MOSFET and is designed to have better characteristics, such as fast switching time, low gate
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UNISONIC TECHNOLOGIES CO., LTD 15A, 600V N-CHANNEL POWER MOSFET DESCRIPTION The UTC 15N60 is an N-channel mode power MOSFET using UTC s advanced technology to provide costumers with planar stripe and DMOS
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UNISONIC TECHNOLOGIES CO., LTD 1.2A, 600V N-CHANNEL POWER MOSFET DESCRIPTION The UTC 1N60 is a high voltage MOSFET and is designed to have better characteristics, such as fast switching time, low gate
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UNISONIC TECHNOLOGIES CO., LTD 10N50 Preliminary Power MOSFET 10A, 500V N-CHANNEL POWER MOSFET DESCRIPTION 1 TO-220 The UTC 10N50 is an N-channel mode power MOSFET using UTC s advanced technology to provide
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UNISONIC TECHNOLOGIES CO., LTD 2.4A, 800V N-CHANNEL POWER MOSFET DESCRIPTION The UTC 2N80 is an N-channel mode power MOSFET using UTC s advanced technology to provide costumers planar stripe and DMOS technology.
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250V P-Channel MOSFET April 2000 QFET TM General Description These P-Channel enhancement mode power field effect transistors are produced using Fairchild s proprietary, planar stripe, DMOS technology.
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