Power Supply Noise Induced Jitter Estimation in High Speed Clock Tree for Full Chip Timing Analysis

Transcription

1 DesignCon 2013 Power Supply Noise Induced Jitter Estimation in High Speed Clock Tree for Full Chip Timing Analysis Wen Yin, IBM Zegui Pang, IBM Wei Liu, IBM Tonghao Ding, IBM Erik Breiland, IBM

2 Abstract As semiconductor technology advances, low supply voltage and high performance requirements make the clock jitter more critical to the integrated circuit (IC) design. In this paper, a 32nm test vehicle is built to characterize and analyze on-chip power supply noise. Clock jitter sensitivity to noise frequency and amplitude is investigated. By studying noise characteristics and jitter sensitivity to noise, a cell based jitter model generation method is introduced. This enables clock tree jitter calculation and flexible what if analysis with reduced run time, which is the key for STA early on in the design phase. The estimation result on a real design is studied and shows good correlation to conventional jitter analysis method. Author(s) Biography Wen Yin is technical leader of packaging engineering solutions and signal integrity analysis from ASIC design center at IBM China Corporation. His current focus includes 3DIC solutions, packaging engineering, and power integrity/signal integrity in ASICs used in high speed network systems. He received BS degree in electronics engineering from Huazhong Science and Technology University, and MS degree in Microelectronics from Shanghai Jiao Tong University. Ze Gui Pang is hardware engineer from IBM China ASIC design center. He focus on package design and power noise analysis, supporting high speed ASIC package solutions, design automation, on-chip power noise analysis and high speed SerDes interface modeling. He received BS and MS degree of microelectronics from Xi Dian University. Wei Liu is hardware engineer from IBM China. She focus on package design, power integrity/signal integrity in ASICs used in high speed network system, supporting design automation, on-chip power noise analysis. She received BS and MS degree of microelectronics from Fu Dan University. Tong Hao Ding is staff hardware engineer from IBM China ASIC design center. He focus on package design, power integrity/signal integrity in high speed circuit system design. He received the B.S. degree in electrical engineering from Xidian University, China, in 2007, and Ph.D degree in electrical engineering from Xidian University, China, in Erik Breiland has been an application engineer from IBM Burlington for the last 7 years of his 14 years with IBM. Prior work included noise tool development, HSS package design, and SSO model to hardware correlation. His current focus is on-chip power integrity, I/O noise analysis, and resonance analysis of customer ASIC Designs. He is also helping develop the noise tool automation and support of current tools and methodology. He received his BS in Electrical Engineering from the Rensselaer Polytechnic Institute in 1998, and an MS in Electrical Engineering in 2005 from the University of Vermont.

3 Introduction As semiconductor technology advances and IC frequency goes higher with lower voltage, clock period jitter acts more and more important role in chip design. Jitter directly reduces timing window between capture and launch sequential elements [1]. Conventional jitter analysis method to estimate clock tree jitter is shown in Figure 1. Figure 1. Conventional jitter analysis method The HSPICE netlist of the clock path is built with cell spice model and extracted interconnect parasitic RC model. The power supply with transient noise for each cell is extracted from whole chip power supply noise analysis tool. Piece Wise Linear (PWL) waveform from analysis tool for each cell is set to cell supply pin (Vdd 0, Vdd 1... Vdd n ) to enable HSPICE simulation. Jitter is measured at the output of the clock sink. This method deployment is limited by the simulation run time, which is up to weeks for a typical clock tree. Therefore this method can be used for a few of specific critical clock path analysis but not suitable to perform chip scale analysis, and it is not able to meet fast design turnaround time and quick what if analysis. In this paper, a fast jitter estimation method is proposed. This method can be run early in the chip s floorplan stage when clock buffers are placed. The estimation results can be back annotated to Static Timing Analysis (STA) tool, in order to assess full chip timing degradation due to clock jitter at early design phase. Corrective actions can be taken to mitigate clock jitter according to jitter analysis. It helps avoid no-timing-window issue in later design. In this method, the key is cell based jitter model generation for clock tree jitter calculation. It is based upon understanding of on-chip power supply noise characteristics, and clock buffer cell jitter sensitivity to noise frequency and amplitude. Runtime is significantly reduced by using the fast jitter estimation method and analysis results accuracy is acceptable because experimental run shows good correlation to conventional jitter analysis method.

4 Understanding On-Chip Power Supply Noise Figure 2 shows a typical power supply noise measured at the circuit point of a 32nm test chip, running continuous switching test pattern after certain delay from the beginning. Figure 2. At-circuit power supply characteristics In Figure 2, at-circuit power supply experiences abrupt drop, followed by voltage bounce due to off-chip recharge and finally settle down with periodic variation riding on a stable voltage. Step response occurs when chip power demand changes abruptly and the inductance of Power Distribution Network (PDN) limits current delivery from power supply. The minimum voltage of step response is determined by the characteristics of PDN and the time and magnitude of power change. The damped oscillation of step response indicates how PDN response to a power demand change which also reveals the characteristic of the PDN such as resonant frequency, which is typically tens to hundreds MHz level. Steady-State AC response is induced by high frequency switching of on chip circuits and primarily a function of chip quiet capacitance and the switch current drained by these circuits [2]. Static IR drop is the average voltage after power supply reaches steady state. It is a function of average power and resistance of PDN. Power supply noise can be thought of as the summation of multiple sinusoids with decaying amplitudes. When step response dies out, the resonant frequency dominates and the supply voltage distribution approaches that of a sinusoid [3]. For very large scale chip in 32nm technology or beyond, the internal circuit is switching at a much higher frequency than the resonance of the PDN. Power supply could not response quickly enough to mitigate the voltage drop, and the transient noise due to PDN resonance acts like DC supply for circuits switching at high frequency. The circuit delay varies to the supply voltage, which induces timing uncertainty. The growth of chip integration and complexity drives the increase of the die size. The clock tree spreads out, suffering more power supply noise from each noise aggressor in different areas. As shown in Figure 3, the power supply noise distribution across the chip has different power supply noise magnitude due to specific floorplan density and circuits current demand. This non uniform noise distribution causes more complexity in predicting the clock jitter [4-6].

5 Figure 3. Power supply noise distribution Jitter Sensitivity to Noise Frequency Based on the period jitter definition [7], the square of the root mean square (RMS) period jitter can be derived as J E R R (1) 2 RMS n n R is autocorrelation function of the phase where n is phase jitter of the nth period; noise n with time interval. The autocorrelation function represent with power spectral density S j as So the square of the RMS period jitter could be obtained as J R could also be 1 j RJ SJ e d 2 (2) J 0 J 2 R 0 R 4 S f sin ft df (3) 2 2 RMS 0 where f is power/ground noise frequency, T 0 is input signal period. It is easily found that the period jitter would be minimum value, when f = n / T 0, and the period jitter would be maximum value, when f =(n+1/2)/ T 0. The relation could be represent as 1 t max, Fnoise n Finput 2 (4) t min, F n F, n 0,1,2... noise where Fnoise is power/ground noise frequency, F input is input signal frequency. The cycle to cycle jitter could also be calculated as input

6 2 JC CRMS 6R 0 8R 2R 2 (5) 2 4 C CRMS 16 sin 0 J 0 (6) J S f ft df It is easily found that the equation (4) could also be applied to the cycle to cycle jitter. It is evidently found that the peak to peak jitter also satisfy equation (4). Figure 4 shows a test circuit including an inverted buffer with input data and power supply noise. This test circuit is built to analyze how noise frequency and signal frequency affect jitter. Vdd Figure 4. Test circuit for jitter and signal-noise frequency relation analysis The input data is modeled with a pulse source. The frequencies are 400MHz, 500MHz and 800MHz respectively, and signal rise time/fall time is 60ps.The power noise is modeled as a single-tone sinusoidal signal, and the noise frequency is a variable changing from 10MHz to 1GHz with 10MHz step. RMS and peak to peak jitter results are plotted in Figure 5. Figure 5. Jitter versus noise frequency plots at different signal frequencies When noise frequency is integral multiple of signal frequency, the smallest jitter values are obtained, when noise frequency is equal to (n+1/2) of signal frequency, the largest jitter values are obtained. It is found that the simulated results are consistent with the equation (4). Generally, one power supply is dominated by one single resonance in chip/package level, and the signal frequency can be known in initial design stage for a given design. Therefore, relation of noise and signal frequency effect on jitter is determined in this design.

7 Jitter Sensitivity to Noise Amplitude In Figure 6 [8], the signal amplitude with noise injection is V, which can be calculated in equation (7), where noise amplitude is V and ideal signal amplitude is V 0. V V V (7) 0 Slope Amplitude(V) k t V Time Figure 6. Relation of jitter and noise amplitude The jitter could be estimated based on the linear relation between noise and signal dv0 amplitude as shown in equation (8). With k, the jitter could be obtained as dt dv dt 0 t V / V / k It is evidently found that the jitter is increasing with the larger noise amplitude. So the jitter could be reduced by suppressing noise. In [9], there is detailed introduction of frequency domain jitter spectrum analysis. In this paper, time domain SPICE simulation experiments are performed to investigate single clock buffer jitter sensitivity to power supply noise. As shown in Figure 7, one stage clock tree HSPICE deck with the C load and supply source is built to analyze the effect of the capacitance and noise on jitter. The input data is modeled as a pulse source with 800MHz frequency and 60ps rise/fall time. The noise frequency is 100MHz and the noise magnitudes are changed from 0.02v to 0.1v with 20mv step. Vdd out (8) Figure 7. Simulation deck of one stage buffer with capacitance load In Figure 8, both RMS and peak to peak jitter results are plotted. It is found that the jitter results become larger with the increasing load capacitance and noise magnitude. Various types of clock buffers are investigated by HSPICE simulation experiments and good

8 linear correlation can be found between buffer output jitter and power supply noise amplitude. Load(pF) Load(pF) (a) (b) Figure 8. Jitter induced by power supply noise with different noise amplitude and load As shown in Figure 9, buffer chain with capacitance load is extracted from actual chip design. HSPICE netlist is built to analyze the effect of the stage number on jitter. The interconnect load is modeled as capacitance and the value is 0.02pF. The input data is modeled with a pulse source with 800MHz frequency and 60ps rise time/fall time. The noise frequency is 100MHz and magnitudes are swept from 0.02v to 0.1v. Vdd Vdd Vdd Vdd Vdd Figure 9. Multiple stages buffers with extracted C load In Figure 10, both RMS and peak to peak jitter results are given. It is found that the jitter is linearly rising with the increasing stages and noise magnitude. (a) (b) Figure 10. Jitter results induced by power supply noise with several stage cells

9 Jitter Calculation and Jitter Model Generation In [10], jitter is accumulated through circuits. For clock tree, jitter is propagated and accumulated from source pin to sink through each element in clock tree path. With predefined cell based jitter model, the jitter calculation is simplified. In Figure 11, given a clock tree, each stage of clock buffer can be traced and divided into segments. Total jitter is accumulated through the segments. Each segment is composed of clock buffer, and output interconnect RC load. Jitter generated from each segment with respect to power supply noise is obtained from pre-characterized cell based jitter model. In this model, the output signal jitter induced by power supply noise can be looked up, interpolated or extrapolated. Figure 11. Proposed jitter analysis methodology By studying the relation between jitter and power supply noise, there are 2 ways to generate the models: First one is from SPICE simulation. The SPICE netlist is based on buffer HSPICE model and interconnect RC load. Power supply noise can be simplified as sinusoid at resonant frequency, and input data is modeled as pulse source with a signal frequency. A look-up table format cell based jitter model can be established according to simulation results. Jitter value can be picked up, interpolated or extrapolated from the model with input noise amplitude, signal frequency and load information. This method is comprehensive and accurate because it honors jitter sensitivity to noise amplitude and frequency. The disadvantage is relative long runtime comparing to second jitter model generation method.

10 Second method uses timing.lib rules. Timing.lib rules include cell delay information with respect to its input signal slew, output load and supply voltage. Worst case peak to peak jitter can be derived by using.lib rules with DC approximation of supply noise. If the clock frequency is not multiple of the power supply resonant frequency, the clock edges will effectively sweep the power supply noise signature over an extended period of time and will probably experience voltage minima and maxima during the majority of the time. Thus, if oscillation period of power supply is much greater than clock path propagation delay (t pd ), the power supply approximately acts as DC during this propagation delay time interval, as it is shown in Figure 12. First Stage t pd Last Stage Figure 12. Power supply noise DC approximation Power supply resonant frequency is typically below 100MHz which is function of image/package inductance and capacitance, and current chip frequency is much higher than resonance. Therefore, using power supply noise DC approximation, worst-case jitter estimation can be simply done by calculating the desired path at the maximum and minimum observable power supply voltages, yielding the fastest and slowest achievable delays respectively. The difference between these two values gives the total estimated peak-to-peak jitter.

11 Correlation of Proposed Jitter Estimation and SPICE Simulation Jitter estimation of clock trees from real design is performed using proposed method, and comparison to conventional SPICE simulation is analyzed. In this experiment, signal frequency is 800MHz, and rise time/fall time is 60ps. Figure 13 shows thermal contour plot of different noise amplitudes. Two clock trees are selected to be analyzed. Both clock tree 1 and 2 have 6 stages of clock buffers. Clock tree1 Domain2 Domain3 Domain1 Clock tree2 Figure 13. Clock trees locations diagram As shown in Figure 14, clock 1 travels through the area with same color that represents one noise domain with the same noise amplitude 40mv. Domain1 Domain2 1 RC 2 RC 3 RC 4 RC 5 RC 6 RC Figure 14. Clock tree 1 in single noise domain In clock tree 1 analysis, the RMS and peak to peak jitter are 18.8ps and 68.4ps respectively while conventional jitter analysis results in 22.7ps and 67.5ps. It shows good correlation. As shown in Figure 15, clock 2 buffers locate in different noise domains. In clock tree 2 analysis, all simulation parameters are the same as previous analysis, except noise magnitudes. The noise amplitudes in domain 1, 2, 3 are 20mv, 40mv and 80mv respectively. Domain1 Domain2 Domain3 1 RC 2 RC 3 RC 4 RC 5 RC 6 RC Figure 15. Clock tree 2 in different noise domains

12 The RMS and peak to peak jitter are 21.0ps and 81.2ps respectively by proposed method comparing to conventional jitter analysis, which results in 24.3ps and 70.4ps. It also shows consistency. Conclusion This paper introduced a novel method for clock jitter estimation, which can be used for full chip timing analysis at early chip design stage. A cell based jitter model is introduced, which is a look-up table format for jitter estimation. Result from experiment on a real design shows good correlation to conventional SPICE simulation, which proves acceptable accuracy for jitter analysis by proposed method. With proposed methodology, flexible what if analysis with reduced run time is available for STA early on in the design phase. The estimation result can be used to guide a designer to optimize types and levels of clock buffer, refine wiring and decoupling strategy, etc. The improvements will ultimately benefit final chip timing closure. In the future, more investigations on cell based jitter model generation method using noise DC approximation and.lib rules are needed. This method enables fast jitter estimation but it does not consider jitter sensitivity to noise frequency. More theoretical analysis and test cases are required to enhance this method. Acknowledgement The authors would like to thank Carlos Dorta for his jitter analysis stuffs in his internship at IBM corporation. The authors would also like to thank Edward Sayre, Margaret Charlebois, Charles Chiu and Rui Zhang for many helpful insights, thank Mark Willette for hardware measurement support and also Neo Li for his management vision. References [1] J. Jang, O. Franza, and W. Burleson, Period Jitter Estimation in Global Clock Trees SPI [2]S.Sun, L.Smith, P.Boyle, On-Chip PDN Noise Characterization and Modeling, DesignCon [3] T. H. Ding and Y. S. Li, Efficient method for modeling of SSN using time-domain impedance function and noise suppression analysis, IEEE Transactions on Components, Packaging and Manufacturing Technology, 2012, 2(3): [4] I. Zamek, M. O. Wong, P. Boyle, N. Daud, L. N. Soh, H. L. Teng and C. S. Fong, A Study of Jitter Effects in nm-fpga based on Various Physical and Electrical Quantities, Asia pacific conference on applied electromagnetics proceedings. [5] D. A. Howe and T. N. Tasset, Clock Jitter Estimation based on PM Noise Measurements, Proceedings of the 2003 IEEE International Frequency Control Symposium and PDA Exhibition Jointly with the 17th European Frequency and Time Forum. [6] M.Saint-Laurent and M.Swaminathan, Impact of power-supply noise on timing in high-frequency microprocessors, IEEE Transactions on Advanced Packaging, Vol.27, Feb [7] I. Zamek, Jitter Spectral Theory, DesignCon [8] Mike Li Peng, Jitter, Noise, and Signal Integrity at High-Speed, Prentice Hall PTR, 2007.

13 [9] H.Lan, R.Schmitt, C.Yuan, Prediction and Measurement of Supply Noise induced Jitter in High-Speed I/O Interfaces, DesignCon [10] A.Hajimiri, S. Limotyrakis, and T. H. Lee Jitter and phase noise in ring oscillators, IEEE Journal of Solid-State Circuits, Vol.34, 1999