Comparative Analyses between Bare Cu Wire and Palladium Coated Cu Wire Performance in IC Packaging Assembly

Size: px
Start display at page:

Download "Comparative Analyses between Bare Cu Wire and Palladium Coated Cu Wire Performance in IC Packaging Assembly"

Transcription

1 Comparative Analyses between Bare Cu Wire and Palladium Coated Cu Wire Performance in IC Packaging Assembly Dr. Jerome Palaganas NANOTECH Solutions, Inc. ABSTRACT Cu wirebonding has been the interconnect technology of choice that has been rapidly replacing Au wirebonding in the semiconductor industry today. Primarily, the direction has been influenced and driven by lower cost and better reliability performance of Cu bonding wire vs. that of Au bonding wire. However, users or companies are faced with two options when converting to Cu wire solution - either to go to bare Cu wire or to adopt PCC, also widely known today as palladium coated copper wire. This paper provides up-to-date summary of comparisons between the Cu wires, namely bare Cu and PCC wire, starting at cost going through workmanship, then through reliability as well as providing other important information commonly overlook during Cu wirebonding production in IC semiconductor assembly. Explanation on interactions of Cu and PCC wire to key interfaces namely on the first bond and second bond are likewise discussed in the paper. Insight on industry trend has also been included, providing a macro view of for the Cu bonding wire history and rationale of migration. Lastly, author s recommendations are provided at the later part of the paper for those who consider converting from Au wire to Cu wire for the first time. In addition, the paper also touches on brief introduction of the alternative and latest interconnect technologies for wirebonding to provide users idea of what the future holds for wirebonding. INTRODUCTION In the middle of the decade of 2000, the push for wirebonding in the semiconductor industry to convert from Au bonding wire to Cu bonding wire was primary driven by finding an interconnect option as an answer to increasing price of gold in the market. However, due to the infancy phase of Cu bonding wire in the industry, and the lack of full support then from wirebond OEMs, the proliferation of Cu bonding wire has seen resistance and hesitation from different companies for the adoption of this interconnect technology. It was not until the late part of 2000s and early part of 2010s, when the price of Au was sky rocketing in the market, demand for Cu bonding wire adoption has become the key priority of many semiconductor companies. However, this move was not without some level of calculated risk involved to these Cu bonding wire industry adopters. Due to the recent introduction of Cu bonding wire, starting 2005, only a few number of players emerged in the market. Thus, selection option by the companies who embraced this new interconnect technology was limited to a few Cu bonding wire suppliers, who were then existing and known suppliers in the Au bonding wire market. The main thrust of early players had been more towards providing workable bonding wire that can be readily be used in manufacturing On the other hand, as the Cu bonding wire becomes more widely accepted in the semiconductor industry, with more and more

2 companies, IDMs and OSATs alike adopting, newer and better Cu bonding wire players have entered the bonding wire space. Some of these players have long and extensive experience and technology over Cu wire manufacturing which provided competitive advantage over Au bonding wire suppliers, who are now also migrating to Cu bonding wire supply and manufacturing. More so, armed with the technology these new players brought along the technology knowledge and patent for Cu bonding wire manufacturing. Thus, soon enough the emergence of insulated or plated Cu bonding wire has been introduced in the market. The introduction came as an innovation to improve the shelf life as well as the reliability of bonding of Cu wire to different device applications. True enough, the Pd plated Cu wire or PCC wire has become the interconnect of choice for those who have done extensive R&D and reliability study, as well as for those late adopters who have accessed to better and newer information on interconnect technology. This paper provides comparative analyses between the two existing Cu bonding wire the bare Cu wire and the PCC wire. The information contained herein provides the reader as well as the industry salient points needed to make a decision when migrating from Au wire to Cu bonding wire, and selecting the wire type between the two technology options. METHODOLOGY Using internal data generated during codevelopment works with customers combined with the literature review with respect to the advancement of Cu wirebonding, the author summarizes the: 1) material, 2) workmanship and 2) reliability performance for both bare Cu and PCC wire in this paper. In order to avoid variability in the results to be presented, most of the studies done had used same device, on both die and leadframe perspective, during the conduct of the evaluation studies completed. Thus, results presented, provide comparative analyses of all the data that shall be presented in succeeding pages of this paper. In this case, TAYA Cu bonding wire has been used in the evaluation studies particularly on the PCC wire. DISCUSSION Cu bonding wire has been seen and proven to provide better electrical performance and thermal conductance as compared with Au bonding wire. These properties of Cu has made it as a very attractive replacement for Au bonding wire as interconnect for wirebonding in the semiconductor industry. In addition, material cost savings derived from conversion from Au wire to Cu wire is relatively significant with larger wire diameter, and higher no. of I/O application in a package. In fact, an 85% estimate material savings can be achieved assuming 1Km length Au bonding wire is replaced by 1Km length Cu bonding wire. On the Cu wire processing side, the only difference between bare Cu and PCC wire is the addition of the Pd plating process. However, critical requirement to achieve a good Cu wire, regardless if bare Cu or PCC wire is the quality of raw materials used. The higher the quality or purity, the better would be quality of the Cu wires produced. For PCC wire, it is a factor that Pd plating over Cu wire must be uniformed and controlled. The quality of the Pd plating affects directly the hardness of the wire as well as the workmanship during wirebonding process. Controlled and uniform plated Pd Cu wires produced consistent

3 yield and quality performance during wirebonding and assembly. Also, it has been found out that overall wire hardness of the Bare Cu or PCC wire translates to the FAB hardness outcome and performance. Bare Cu or PCC wire with lower hardness measure produces softer FAB than those with higher wire hardness measure with wirebond parameters set at a constant. Looking at workmanship, using 20 um bonding wire diameter on device A with an Al bond pad structure from Customer A, 1 st and 2 nd bond performance of Au wire, Cu wire and PCC wire are presented in Figures 1, 2 and 3 respectively. All bonds from the three different wires show good 1 st and 2 nd bond appearance relative to the bonding pad and leadframe leadfinger structures. Specific to the 2 nd bond, there is not much tool or capillary mark indentation which can be seen for the stitch bond created using the PCC wire. This is apparent as PCC wire used in the wire evaluation used lower bond force and bond power comparable bare Cu wire used. However, this setting of second bond parameter does not translate to lower wire pull strength which later on can be seen on the subsequent page. Figure 2: Bare Cu wire 1 st and 2 nd bond Figure 3: PCC wire 1 st and 2 nd bond Likewise, crater test results for all the wires, as presented in Figures 4, 5 and 6 for Au wire, Cu wire and PCC wire, respectively. However, it can be noted that to test the true performance of the Cu wire and PCC wire, a circuit-under-pad or CUP device has been pre-selected. It has been an early notion before that PCC wire is hard, and difficulty to bond CUP bond pad structure was an earlier challenge. However, based on evidence presented below, using CUP device, PCC wire is able to pass crater test even with this kind of structure underneath the bonding pad. Figure 1: Au wire 1 st and 2 nd bond

4 shear strength, wire loop height, bonded ball height and bonded ball size. Cpk values for all five workmanship dimensions are used to compare the overall wire performance for each wire. For workmanship dimensions having Cpk >5, these are standardized or transformed to maximum of 5 Cpk value. Figure 4: Au wire crater test result Figure 5: Bare Cu wire crater test result Figure 6: PCC wire crater test result In Fig. 7, comparison for the three wires - Au wire, Cu wire, and PCC wire workmanship is presented. For Au wire and Cu wire, suppliers A and B were used. Whereas, PCC wire used in the comparative study is from TAYA. Apart from visual workmanship, the spider web chart presented in Figure 7, summarizes key mechanical workmanship performance of the three wire used namely, Au wire, Cu wire and PCC wire in terms of wire pull strength, ball Figure 7: Au vs. Cu vs. PCC Workmanship Matrix Cu wire performance, represented by brown color, shows better workmanship performance compared to Au wire for wire pull, ball size and ball height. And slightly better workmanship performance on loop height than Au wire. Whereas, PCC wire performance, on the other hand, represented by blue color, surpasses that of Cu wire on loop height and wire pull. And, on comparative performance with Cu wire for ball size and ball height. The good performance of PCC wire in this case is attributed to the softer wire property of TAYA bonding wire, thus, allowing consistent loop formation during wire bonding due to its highly workable wire property. This outcome has provided new evidence that PCC wire can no longer be considered as a hard wire, a belief earlier formed during the introductory phase of the PCC wire in the semiconductor market. Specific to 2 nd bond, the higher performance of wire pull values between the Cu and Ag interface on leadframe for PCC wire is attributed

5 to the low presence of oxygen in the said interface [1]. Overall, PCC wire workmanship performance is seen better than Cu and Au wires for all dimensions examined except for ball shear where in Au wire still has higher Cpk performance than PCC wire. This performance of Au wire on ball shear, with better performance than PCC and Cu wires, is attributed to the softer property of Au wire allowing it to produce better bonding adhesion with the bond pad after the 1 st bond formation at wirebond. In terms of reliability, recent studies show comparing bare Cu and PCC wire performance in reliability in terms of uhast and PCT, results so far from studies conducted favors that of PCC wire [2]. For uhast, using 135 o C/85%RH, Cu wire translated product life is 100 hr as compared to 1300 hr for PCC wire with both wires are used in combination of green molding compound [3]. In addition, under PCT 400hrs, Cu wire when combined to green molding compound shows cracking or separation at the Al-Cu IMC. Whereas, under the same condition, of PCT 400hrs, PCC wire combined with green molding compound does not exhibit any cracking at the IMC interface of the PCC wire and Al bonding pad [2]. Apart from workmanship and reliability performance, another factors needed to be considered in the Cu wirebonding are the assembly yield and process window when using bare Cu or PCC wires. Due to the presence of Pd plating, unlike the bare Cu wire, PCC wire extends the open air shelf life of the wire to a 15 day nominal period. However, there are cases which the open shelf life is set up to 30 day still achieving the same yield and quality performance. CONCLUSION / RECOMMENDATION In summary, it is presented that current level of bare Cu and PCC wire, with the introduction of innovation in both process and material in the Cu bonding wire manufacturing, are able to provide good visual and mechanical performance when doing wirebonding on IC device in lieu of Au bonding wire. However, comparing the two wires, PCC wire reliability performance has been found to be superior to that of bare Cu wire. In addition, working with PCC wire in production, based on our experience, using advanced PCC wire type like TAYA PCC bonding wire, is seen already to be almost comparable to that of Au bonding wire. However, just a caveat to engineers doing work on PCC bonding wire, not all PCC wires have the same level of Pd plating technology and overall wire hardness, thus, a careful selection is needed when adapting to the PCC bonding wire. With the correct wire selection, full benefits of adopting PCC wire can be achieved. In addition, there are new interconnect material options emerging in the market other than bare Cu and PCC wires. These are the Ag wire, Pd-doped wire, and Au+Pd plated Cu wire. With the experience gained in Cu wirebonding, the selection criteria on overall workmanship, quality, reliability and price can be applied during the selection process. However, the author believes that PCC would be the mainstay for Cu wirebonding for a while until any of identified next generation bonding wires would be able to provide similar extensive data with better quality and reliability performance results. Likewise, the wires have to prove itself capable to the different packaging applications in the semiconductor industry.

6 REFERENCES 1. Qin, I., Clauberg, H., Cathcart, R., Acoff, V., Cylak, B., and Huynh, C., Wirebonding of Cu and Pd Coated Cu wire: Bondability, Reliability, and IMC Formation, Electronics Components and Technology Conference (2011), pp Uno, T., Bond reliability under humid environment for coated copper wire and bare copper wire, Microelectronics Reliability, (2011) Vol. 51, pp ABOUT THE AUTHOR Dr. Jerome Palaganas is currently the Business Development and Operations Head of Nanotech Solutions, the materials and automations division under SA Technologies, Inc. Dr. Palaganas has more than 19 years of engineering and management experience in the semiconductor and electronics industry, including process, development, R&D, NPI and program management responsibility at Amkor Technology Philippines working at various sites and with different packaging technologies. He also played a key role as a start-up wirebond technical development and process engineer for Amkor s MQFP and TQFP packages as well as done pioneering and successful works in Cu wirebond development and qualification for CABGA in 2009 among others. Apart from the industry experience, Dr. Palaganas taught at the De La Salle Graduate School of Business for more than 8 years. He received his Doctor of Business Administration and Master of Business Administration degrees from De La Salle University finishing both With High Distinction Honors. And, he earned his Bachelor of Science in Electronics and Communications Engineering from Mapua Institute of Technology graduating at the Top Ten list of his class.

INCREASING PACKAGE ROBUSTNESS WITH PALLADIUM COATED COPPER WIRE

INCREASING PACKAGE ROBUSTNESS WITH PALLADIUM COATED COPPER WIRE INCREASING PACKAGE ROBUSTNESS WITH PALLADIUM COATED COPPER WIRE Rodan A. Melanio Regine B. Cervantes Sonny E. Dipasupil New Package Development ON Semiconductor Philippines Incorporated Golden Mile Business

More information

Interconnection Challenge in Wire Bonding Ag alloy wire. Jensen Tsai / 蔡瀛洲, SPIL, Taiwan

Interconnection Challenge in Wire Bonding Ag alloy wire. Jensen Tsai / 蔡瀛洲, SPIL, Taiwan 1 Interconnection Challenge in Wire Bonding Ag alloy wire Jensen Tsai / 蔡瀛洲, SPIL, Taiwan 2 Content Ag Alloy Wire Type Market Ag Alloy Wire Benefits Workability and Reliability Performance IMC behavior

More information

Wirebond challenges in QFN. Engineering Team - Wire bond section SPEL Semiconductor Limited

Wirebond challenges in QFN. Engineering Team - Wire bond section SPEL Semiconductor Limited Introduction: Wirebond challenges in QFN by Engineering Team - Wire bond section SPEL Semiconductor Limited The market for the portable & handheld consumer electronic goods is growing rapidly and technological

More information

The Future of Packaging and Cu Wire Bonding Advances. Ivy Qin

The Future of Packaging and Cu Wire Bonding Advances. Ivy Qin The Future of Packaging and Cu Wire Bonding Advances Ivy Qin Introduction Semiconductors have been around for over 70 years Packaging is playing a more and more important role, providing low cost high

More information

Challenges of Ultimate Ultra-Fine Pitch Process with Gold Wire & Copper Wire in QFN Packages

Challenges of Ultimate Ultra-Fine Pitch Process with Gold Wire & Copper Wire in QFN Packages Challenges of Ultimate Ultra-Fine Pitch Process with Gold Wire & Copper Wire in QFN Packages C.E.Tan, J.Y.Liong, Jeramie Dimatira, Jason Tan* & Lee Wee Kok** ON Semiconductor Lot 122, Senawang Industrial

More information

ENGINEERING PRACTICE STUDY FINAL REPORT STUDY PROJECT September 20, 2017

ENGINEERING PRACTICE STUDY FINAL REPORT STUDY PROJECT September 20, 2017 ENGINEERING PRACTICE STUDY TITLE: Copper (Cu) wire bond test methodology development for microcircuit, hybrid and semiconductor devices FINAL REPORT STUDY PROJECT 5962-2017-002 September 20, 2017 Study

More information

EFFECTS OF USG CURRENT AND BONDING LOAD ON BONDING FORMATION IN QFN STACKED DIE PACKAGE. A. Jalar, S.A. Radzi and M.A.A. Hamid

EFFECTS OF USG CURRENT AND BONDING LOAD ON BONDING FORMATION IN QFN STACKED DIE PACKAGE. A. Jalar, S.A. Radzi and M.A.A. Hamid Solid State Science and Technology, Vol. 16, No 2 (2008) 65-71 EFFECTS OF USG CURRENT AND BONDING LOAD ON BONDING FORMATION IN QFN STACKED DIE PACKAGE A. Jalar, S.A. Radzi and M.A.A. Hamid School of Applied

More information

Stitch Bond Enhancement for X-Wire Insulated Bonding Wire

Stitch Bond Enhancement for X-Wire Insulated Bonding Wire Stitch Bond Enhancement for X-Wire Insulated Bonding Wire A Technical Collaboration Published by: Small Precision Tools www.smallprecisiontools.com and Microbonds Inc. www.microbonds.com 2007 Microbonds

More information

Introduction to Wire-Bonding

Introduction to Wire-Bonding Introduction to Wire-Bonding Wire bonding is a kind of friction welding Material are connected via friction welding Advantage: Different materials can be connected to each other widely used, e.g. in automobile

More information

Tips for Increasing Yields when Wire Bonding Small MESA Chips TECH BRIEF

Tips for Increasing Yields when Wire Bonding Small MESA Chips TECH BRIEF Tips for Increasing Yields when Wire Bonding Small MESA Chips TECH BRIEF Abstract: lorem ipsum dolor sit amet Small MESA devices have posed a number of wire-bonding challenges, which have required advancements

More information

MEPTEC Luncheon Presentation. Introduction of Ag Alloy Bonding Wire William (Bud) Crockett Jr.

MEPTEC Luncheon Presentation. Introduction of Ag Alloy Bonding Wire William (Bud) Crockett Jr. MEPTEC Luncheon Presentation Introduction of Ag Alloy Bonding Wire William (Bud) Crockett Jr. w-crockett@ml.tanaka.co.jp April 10, 2013 2012 Semiconductor Market Tracking Forbes 2012 Monthly rolling forecast

More information

سمینار درس تئوری و تکنولوژی ساخت

سمینار درس تئوری و تکنولوژی ساخت نام خدا به 1 سمینار درس تئوری و تکنولوژی ساخت Wire Bonding استاد : جناب آقای محمدنژاد دکتر اردیبهشت 93 2 3 Content IC interconnection technologies Whats wirebonding Wire Bonding Processes Thermosonic Wirebond

More information

Pull Force and Tail Breaking Force Optimization of the Crescent Bonding Process with Insulated Au Wire. Experimental

Pull Force and Tail Breaking Force Optimization of the Crescent Bonding Process with Insulated Au Wire. Experimental Pull Force and Tail Breaking Force Optimization of the Crescent Bonding Process with Insulated Au 1 J. Lee, 1 M. Mayer, 1 Y. Zhou and 2 J. Persic 1 Microjoining Lab, Centre of Advanced Materials Joining,

More information

23 rd ASEMEP National Technical Symposium

23 rd ASEMEP National Technical Symposium V3V3D VSS GPIO0_SA GPIO1_SA AF E_ S CLK_SA AFE_ RST_SA VSS GPI O1 _A GPI O0 _AAF E_ FR _RDYAFE_ RST AFE_SCS AFE_SCLKAFE_SDA0A F E_ S D A1 V3V3D V3V3D VSS GPI O3 MS DA MS CL GPI O2 GPI O1 GPI O0 TSDA TSCL

More information

Abstract. Key words: Interconnections, wire bonding, Ball Grid Arrays, metallization

Abstract. Key words: Interconnections, wire bonding, Ball Grid Arrays, metallization Integrated Solutions to Bonding BGA Packages: Capillary, Wire, and Machine Considerations by Leroy Christie, Director Front Line Process Engineering AMKOR Electronics 1900 South Price Road, Chandler, Az

More information

Abstract. Key words: Insulated bonding wire, Advanced Packaging, Wire bonding

Abstract. Key words: Insulated bonding wire, Advanced Packaging, Wire bonding Robust Wirebonding of X-Wire Insulated Bonding Wire Technology Christopher Carr, Juan Munar, William Crockett, Robert Lyn Microbonds Inc. 151 Amber St. Unit 12 Markham, Ontario, Canada L3R 3B3 Tel: 905-305-0980,

More information

Stack Die CSP Interconnect Challenges Flynn Carson, Glenn Narvaez, HC Choi, and DW Son ChipPAC, Inc.

Stack Die CSP Interconnect Challenges Flynn Carson, Glenn Narvaez, HC Choi, and DW Son ChipPAC, Inc. Stack Die CSP Interconnect Challenges Flynn Carson, Glenn Narvaez, HC Choi, and DW Son ChipPAC, Inc. IEEE/CPMT Seminar Overview 4 Stacked die Chip Scale Packages (CSPs) enable more device functionality

More information

PRODUCT/PROCESS CHANGE NOTICE (PCN)

PRODUCT/PROCESS CHANGE NOTICE (PCN) PCN #: A1007-07 DATE: August 25, 2010 MEANS OF DISTINGUISHING CHANGED DEVICES: Product Affected: 82V2048 and 82V2058 Product Mark (built in 20 mm x 20 mm TQFP-144) Back Mark Date Code Date Effective: Contact:

More information

Chip-On-Lead Semiconductor Package with Copper Wirebonding

Chip-On-Lead Semiconductor Package with Copper Wirebonding Chip-On-Lead Semiconductor Package with Copper Wirebonding Antonio R. Sumagpang Jr., Frederick Ray I. Gomez New Product Introduction Department, Back-End Manufacturing & Technology, STMicroelectronics,

More information

Innovations Push Package-on-Package Into New Markets. Flynn Carson. STATS ChipPAC Inc Kato Rd Fremont, CA 94538

Innovations Push Package-on-Package Into New Markets. Flynn Carson. STATS ChipPAC Inc Kato Rd Fremont, CA 94538 Innovations Push Package-on-Package Into New Markets by Flynn Carson STATS ChipPAC Inc. 47400 Kato Rd Fremont, CA 94538 Copyright 2010. Reprinted from Semiconductor International, April 2010. By choosing

More information

MICROELECTRONICS ASSSEMBLY TECHNOLOGIES. The QFN Platform as a Chip Packaging Foundation

MICROELECTRONICS ASSSEMBLY TECHNOLOGIES. The QFN Platform as a Chip Packaging Foundation West Coast Luncheon January 15, 2014. PROMEX PROMEX INDUSTRIES INC. MICROELECTRONICS ASSSEMBLY TECHNOLOGIES The QFN Platform as a Chip Packaging Foundation 3075 Oakmead Village Drive Santa Clara CA Ɩ 95051

More information

2.5D Platform (Examples of products produced to date are shown here to demonstrate Amkor's production capabilities)

2.5D Platform (Examples of products produced to date are shown here to demonstrate Amkor's production capabilities) Wafer Finishing & Flip Chip Stacking interconnects have emerged to serve a wide range of 2.5D- & 3D- packaging applications and architectures that demand very high performance and functionality at the

More information

Advances in stacked-die packaging

Advances in stacked-die packaging pg.10-15-carson-art 16/6/03 4:12 pm Page 1 The stacking of die within IC packages, primarily Chip Scale Packages (CSP) Ball Grid Arrays (BGAs) has evolved rapidly over the last few years. The now standard

More information

B. Flip-Chip Technology

B. Flip-Chip Technology B. Flip-Chip Technology B1. Level 1. Introduction to Flip-Chip techniques B1.1 Why flip-chip? In the development of packaging of electronics the aim is to lower cost, increase the packaging density, improve

More information

Broadband Printing: The New SMT Challenge

Broadband Printing: The New SMT Challenge Broadband Printing: The New SMT Challenge Rita Mohanty & Vatsal Shah, Speedline Technologies, Franklin, MA Gary Nicholls, Ron Tripp, Cookson Electronic Assembly Materials Engineered Products, Johnson City,

More information

QUALIFICATION PLAN PCN #: IIRA-05BPMD768. Date: Dec 18, Qualification of 132L DQFN package at ANAC assembly site. A.

QUALIFICATION PLAN PCN #: IIRA-05BPMD768. Date: Dec 18, Qualification of 132L DQFN package at ANAC assembly site. A. QUALIFICATION PLAN PCN #: IIRA-05BPMD768 Date: Dec 18, 2013 Qualification of 132L DQFN package at ANAC assembly site. Distribution Surasit P. Rangsun K A. Navarro Irina K Wichai K. Fernando C Chaweng W.

More information

22 nd ASEMEP National Technical Symposium

22 nd ASEMEP National Technical Symposium QUAD FLAT NO-LEAD (QFN) FINE PITCH PACKAGING DESIGN AND MANUFACTURING CHALLENGES Michael B. Tabiera Ricky B. Calustre Jefferson S. Talledo Corporate Packaging & Automation STMicroelectronics, Inc., Calamba

More information

High efficient heat dissipation on printed circuit boards

High efficient heat dissipation on printed circuit boards High efficient heat dissipation on printed circuit boards Figure 1: Heat flux in a PCB Markus Wille Schoeller Electronics Systems GmbH www.schoeller-electronics.com Abstract This paper describes various

More information

Fan-Out Wafer Level Packaging Patent Landscape Analysis

Fan-Out Wafer Level Packaging Patent Landscape Analysis Fan-Out Wafer Level Packaging Patent Landscape Analysis Source: Infineon Source: TSMC Source: ASE November 2016 Source: Deca Technologies Source: STATS ChipPAC Source: Nepes KnowMade Patent & Technology

More information

SURFACE FINISH FOR ELECTRONIC PACKAGING WITH LEAD-FREE SOLDERS. Abstract

SURFACE FINISH FOR ELECTRONIC PACKAGING WITH LEAD-FREE SOLDERS. Abstract ~ ~ SURFACE FINISH FOR ELECTRONIC PACKAGING WITH LEAD-FREE SOLDERS PDF- I. V. Kadija J. A. Abys AT&T Bell Laboratories 600 Mountain Avenue Murray Hill, NJ 07974 Abstract Current trends in the preservation

More information

Available online at ScienceDirect. Procedia Engineering 75 (2014 ) MRS Singapore - ICMAT Symposia Proceedings

Available online at   ScienceDirect. Procedia Engineering 75 (2014 ) MRS Singapore - ICMAT Symposia Proceedings Available online at www.sciencedirect.com ScienceDirect Procedia Engineering 7 (14 ) 134 139 MRS Singapore - ICMAT Symposia Proceedings Synthesis, Processing and Characterization III Hardness Measurement

More information

Data Sheet _ R&D. Rev Date: 8/17

Data Sheet _ R&D. Rev Date: 8/17 Data Sheet _ R&D Rev Date: 8/17 Micro Bump In coming years the interconnect density for several applications such as micro display, imaging devices will approach the pitch 10um and below. Many research

More information

MIL-STD-883E METHOD BOND STRENGTH (DESTRUCTIVE BOND PULL TEST)

MIL-STD-883E METHOD BOND STRENGTH (DESTRUCTIVE BOND PULL TEST) BOND STRENGTH (DESTRUCTIVE BOND PULL TEST) 1. PURPOSE. The purpose of this test is to measure bond strengths, evaluate bond strength distributions, or determine compliance with specified bond strength

More information

AuthenTec AES1710 Secure Slide Fingerprint Sensor

AuthenTec AES1710 Secure Slide Fingerprint Sensor AuthenTec AES1710 Secure Slide Fingerprint Sensor Package Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology,

More information

Application Note AN-1011

Application Note AN-1011 AN-1011 Board Mounting Application Note for 0.800mm Pitch Devices For part numbers IRF6100, IRF6100PBF, IR130CSP, IR130CSPPBF, IR140CSP, IR140CSPPBF, IR1H40CSP, IR1H40CSPPBF By Hazel Schofield and Philip

More information

Min Tao, Ph. D, Ashok Prabhu, Akash Agrawal, Ilyas Mohammed, Ph. D, Bel Haba, Ph. D Oct , IWLPC

Min Tao, Ph. D, Ashok Prabhu, Akash Agrawal, Ilyas Mohammed, Ph. D, Bel Haba, Ph. D Oct , IWLPC PACKAGE-ON-PACKAGE INTERCONNECT FOR FAN-OUT WAFER LEVEL PACKAGES Min Tao, Ph. D, Ashok Prabhu, Akash Agrawal, Ilyas Mohammed, Ph. D, Bel Haba, Ph. D Oct 18-20 2016, IWLPC 1 Outline Laminate to Fan-Out

More information

HKPCA Journal No. 10. Wetting of Fresh and Aged Immersion Tin and Silver Surface Finishes by Sn/Ag/Cu Solder. Minna Arra Flextronics Tampere, Finland

HKPCA Journal No. 10. Wetting of Fresh and Aged Immersion Tin and Silver Surface Finishes by Sn/Ag/Cu Solder. Minna Arra Flextronics Tampere, Finland Wetting of Fresh and Aged Immersion Tin and Silver Surface Finishes by Sn/Ag/Cu Solder Minna Arra Flextronics Tampere, Finland Dongkai Shangguan & DongJi Xie Flextronics San Jose, California, USA Abstract

More information

Impact of Young Modulus of Epoxy Glue to Copper Wire Bonding

Impact of Young Modulus of Epoxy Glue to Copper Wire Bonding Impact of Young Modulus of Epoxy Glue to Copper Wire Bonding Tan KG 1, Chung EL 1, Wai CM 1, Ge Dandong 2 1 Infineon Technologies (Malaysia) Sdn Bhd, Malaysia 2 Infineon Technologies Asia Pacific Pte Ltd,

More information

TDDB Time Depending Dielectric Breakdown. NBTI Negative Bias Temperature Instability. Human Body Model / Machine Model

TDDB Time Depending Dielectric Breakdown. NBTI Negative Bias Temperature Instability. Human Body Model / Machine Model For integrated circuits or discrete semiconductors select Amkor-Kr to ASECL Assembly Transfer with Cu wire bonds ID Type of change No Yes AC TC SD Headings ANY A2 A3 A4 A5 A6 B1 B2 B3 C1 C2 C3 C4 C5 C6

More information

Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract)

Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract) Flexline - A Flexible Manufacturing Method for Wafer Level Packages (Extended Abstract) by Tom Strothmann, *Damien Pricolo, **Seung Wook Yoon, **Yaojian Lin STATS ChipPAC Inc.1711 W Greentree Drive Tempe,

More information

General Rules for Bonding and Packaging

General Rules for Bonding and Packaging General Rules for Bonding and Packaging at the Else Kooi Laboratory 3 CONTENT Rules for assembly at EKL 4 Introduction to assembly 5 Rules for Saw Lane 7 Rules for Chip Size 8 Rules for Bondpads 9 Rules

More information

ARCHIVE Brandon Prior Senior Consultant Prismark Partners ABSTRACT

ARCHIVE Brandon Prior Senior Consultant Prismark Partners ABSTRACT ARCHIVE 2010 LOW COST, SMALL FORM FACTOR PACKAGING by Brandon Prior Senior Consultant Prismark Partners W ABSTRACT hile size reduction and performance improvement are often the drivers of new package and

More information

SESUB - Its Leadership In Embedded Die Packaging Technology

SESUB - Its Leadership In Embedded Die Packaging Technology SESUB - Its Leadership In Embedded Die Packaging Technology Sip Conference China 2018 TDK Corporation ECBC, PAF, SESUB BU Kofu, Japan October 17, 2018 Contents SESUB Introduction SESUB Process SESUB Quality

More information

Electroless Bumping for 300mm Wafers

Electroless Bumping for 300mm Wafers Electroless Bumping for 300mm Wafers T. Oppert Internepcon 2006 Tokyo Big Sight, Japan Outline Short Company Profile Electroless Ni/Au Under Bump Metallization UBM for Copper Devices Solder Bumping: Stencil

More information

Brief Introduction of Sigurd IC package Assembly

Brief Introduction of Sigurd IC package Assembly Brief Introduction of Sigurd IC package Assembly Content Package Development Trend Product Brief Sawing type QFN Representative MEMS Product LGA Light Sensor Proximity Sensor High Yield Capability Low

More information

Diodes Incorporated. Discrete and Analog Semiconductors

Diodes Incorporated. Discrete and Analog Semiconductors www.diodes.com Diodes Incorporated for Discrete and Analog Semiconductors QPAK/PPAP 2130 Qualification Report Manufacturer No.: PCN-2130 Qualification of Alternative Copper Bond Wire, BOM Change, A/T Site

More information

BOARD DESIGN, SURFACE MOUNT ASSEMBLY AND BOARD LEVEL RELIABILITY ASPECTS OF FUSIONQUAD TM PACKAGES

BOARD DESIGN, SURFACE MOUNT ASSEMBLY AND BOARD LEVEL RELIABILITY ASPECTS OF FUSIONQUAD TM PACKAGES BOARD DESIGN, SURFACE MOUNT ASSEMBLY AND BOARD LEVEL RELIABILITY ASPECTS OF FUSIONQUAD TM PACKAGES Ahmer Syed 1, Sundar Sethuraman 2, WonJoon Kang 1, Gary Hamming 1, YeonHo Choi 1 1 Amkor Technology, Inc.

More information

PRODUCT/PROCESS CHANGE NOTICE (PCN)

PRODUCT/PROCESS CHANGE NOTICE (PCN) PCN #: A1205-01 Date: June 11, 2012 MEANS OF DISTINGUISHING CHANGED DEVICES: Product Affected: SSOP-28 Product Mark Lot # will have "MM" or "MS" prefix for Carsem (Green) Back Mark Malaysia and suffix

More information

Challenges of Ultra-thin LGA Package for Fingerprint Sensors

Challenges of Ultra-thin LGA Package for Fingerprint Sensors Challenges of Ultra-thin LGA Package for Fingerprint Sensors Jensen Tsai Deputy Director, SPIL Outline Background Package Features & Challenges Challenges & Solutions Mold Clearance Low Wire Loop Height

More information

Ball-Wedge Bonder G

Ball-Wedge Bonder G PRODUCT-BROCHURE Ball-Wedge Bonder G5 62000 F & K DELVOTEC The Ball-Wedge Bonder specialist delivers the perfect solution for any bonding challenge in the automotive, opto-electronics, sensors and HF/RF

More information

Ball Wedge Bonder. F & K Model G ADVANTAGES

Ball Wedge Bonder. F & K Model G ADVANTAGES Ball Wedge Bonder F & K Model G5 62000 F & K DELVOTEC The Ball Wedge Bonder specialist delivers the perfect solution for any bonding challenge in the automotive, optoelectronics, sensors and HF/RF technology.

More information

An Introduction to Electronics Systems Packaging. Prof. G. V. Mahesh. Department of Electronic Systems Engineering

An Introduction to Electronics Systems Packaging. Prof. G. V. Mahesh. Department of Electronic Systems Engineering An Introduction to Electronics Systems Packaging Prof. G. V. Mahesh Department of Electronic Systems Engineering India Institute of Science, Bangalore Module No. # 02 Lecture No. # 08 Wafer Packaging Packaging

More information

Wedge Bonding Chip on Board (COB) and Direct Chip Attach (DCA) Applications

Wedge Bonding Chip on Board (COB) and Direct Chip Attach (DCA) Applications Wedge Bonding Chip on Board (COB) and Direct Chip Attach (DCA) Applications Lee Levine, Consultant Process Solutions Consulting, Inc Distinguished Member of the Technical Staff Hesse & Knipps, Inc levilr@ptd.net

More information

What the Designer needs to know

What the Designer needs to know White Paper on soldering QFN packages to electronic assemblies. Brian J. Leach VP of Sales and Marketing AccuSpec Electronics, LLC Defect free QFN Assembly What the Designer needs to know QFN Description:

More information

The Future of Packaging ~ Advanced System Integration

The Future of Packaging ~ Advanced System Integration The Future of Packaging ~ Advanced System Integration Enabling a Microelectronic World R. Huemoeller SVP, Adv. Product / Platform Develop June 2013 Product Segments End Market % Share Summary 2 New Product

More information

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative

POSSUM TM Die Design as a Low Cost 3D Packaging Alternative POSSUM TM Die Design as a Low Cost 3D Packaging Alternative The trend toward 3D system integration in a small form factor has accelerated even more with the introduction of smartphones and tablets. Integration

More information

AN5046 Application note

AN5046 Application note Application note Printed circuit board assembly recommendations for STMicroelectronics PowerFLAT packages Introduction The PowerFLAT package (5x6) was created to allow a larger die to fit in a standard

More information

Wedge Bonder --- West Bond E

Wedge Bonder --- West Bond E Wedge Bonder --- West Bond 747677E Figure 1: West Bond Wedge Bonder Introduction The West Bond 747677E bonder is an ultrasonic wedge-wedge wire bonder designed to interconnect wire leads to various types

More information

Coto Technology 9814 Reed Relay

Coto Technology 9814 Reed Relay Coto Technology 9814 Reed Relay Coto Technology has recently released a new version of its flagship ATE grade 9800 series relay, the 9814 model. The 9814 is a logical successor to previous members of the

More information

Process Certification and Defect Recognition: Hybrids, Microcircuits and RF/MMIC Modules (3 DAYS)

Process Certification and Defect Recognition: Hybrids, Microcircuits and RF/MMIC Modules (3 DAYS) Process Certification and Defect Recognition: Hybrids, Microcircuits and RF/MMIC Modules (3 DAYS) Course Description: Most companies struggle to introduce new lines and waste countless manhours and resources

More information

Wire Bond Technology The Great Debate: Ball vs. Wedge

Wire Bond Technology The Great Debate: Ball vs. Wedge Wire Bond Technology The Great Debate: Ball vs. Wedge Donald J. Beck, Applications Manager Alberto C. Perez, Hardware and Applications Engineer Palomar Technologies, Inc. 2728 Loker Avenue West Carlsbad,

More information

UMS User guide for bare dies GaAs MMIC. storage, pick & place, die attach and wire bonding

UMS User guide for bare dies GaAs MMIC. storage, pick & place, die attach and wire bonding UMS User guide for bare dies GaAs MMIC storage, pick & place, die attach and wire bonding Ref. : AN00014097-07 Apr 14 1/10 Specifications subject to change without notice United Monolithic Semiconductors

More information

Chip Assembly on MID (Molded Interconnect Device) A Path to Chip Modules with increased Functionality

Chip Assembly on MID (Molded Interconnect Device) A Path to Chip Modules with increased Functionality T e c h n o l o g y Dr. Werner Hunziker Chip Assembly on MID (Molded Interconnect Device) A Path to Chip Modules with increased Functionality The MID (Molded Interconnect Device) technology enables the

More information

Silicon Interposers enable high performance capacitors

Silicon Interposers enable high performance capacitors Interposers between ICs and package substrates that contain thin film capacitors have been used previously in order to improve circuit performance. However, with the interconnect inductance due to wire

More information

Yole Developpement. Developpement-v2585/ Publisher Sample

Yole Developpement.  Developpement-v2585/ Publisher Sample Yole Developpement http://www.marketresearch.com/yole- Developpement-v2585/ Publisher Sample Phone: 800.298.5699 (US) or +1.240.747.3093 or +1.240.747.3093 (Int'l) Hours: Monday - Thursday: 5:30am - 6:30pm

More information

COFDC SUMMARY FOR ATP1 ASSEMBLY SITE QUALIFICATION FOR PLCC PACKAGE WITH CU WIRE EXTERNAL USE

COFDC SUMMARY FOR ATP1 ASSEMBLY SITE QUALIFICATION FOR PLCC PACKAGE WITH CU WIRE EXTERNAL USE COFDC SUMMARY FOR ATP1 ASSEMBLY SITE QUALIFICATION FOR PLCC PACKAGE WITH CU WIRE EXTERNAL USE MC68HC705C8A (M24Z) PLCC44 Item Name Supplier Response (CHD/KLM AU) Supplier Response (CHD/ATP CU) 1. User

More information

WB/WT/WXSC 250µm/WLSC100µm - Assembly by Wirebonding

WB/WT/WXSC 250µm/WLSC100µm - Assembly by Wirebonding General description This document describes the attachment techniques recommended by Murata* for their vertical capacitors on the customer substrates. This document is non-exhaustive. Customers with specific

More information

High Efficient Heat Dissipation on Printed Circuit Boards. Markus Wille, R&D Manager, Schoeller Electronics Systems GmbH

High Efficient Heat Dissipation on Printed Circuit Boards. Markus Wille, R&D Manager, Schoeller Electronics Systems GmbH High Efficient Heat Dissipation on Printed Circuit Boards Markus Wille, R&D Manager, Schoeller Electronics Systems GmbH m.wille@se-pcb.de Introduction 2 Heat Flux: Q x y Q z The substrate (insulation)

More information

International SEMATECH Wafer Probe Benchmarking Project WAFER PROBE ROADMAP. Guidance For Wafer Probe R&D Resources Edition

International SEMATECH Wafer Probe Benchmarking Project WAFER PROBE ROADMAP. Guidance For Wafer Probe R&D Resources Edition International SEMATECH Wafer Probe Benchmarking Project WAFER PROBE ROADMAP Guidance For Wafer Probe R&D Resources 2002 Edition Fred Taber, IBM Microelectronics Probe Project Chair Gavin Gibson, Infineon

More information

Some Key Researches on SiC Device Technologies and their Predicted Advantages

Some Key Researches on SiC Device Technologies and their Predicted Advantages 18 POWER SEMICONDUCTORS www.mitsubishichips.com Some Key Researches on SiC Device Technologies and their Predicted Advantages SiC has proven to be a good candidate as a material for next generation power

More information

Advanced High-Density Interconnection Technology

Advanced High-Density Interconnection Technology Advanced High-Density Interconnection Technology Osamu Nakao 1 This report introduces Fujikura s all-polyimide IVH (interstitial Via Hole)-multi-layer circuit boards and device-embedding technology. Employing

More information

Appeal decision. Appeal No USA VISHAY SILICONIX INC. Tokyo, Japan. Tokyo, Japan. Tokyo, Japan

Appeal decision. Appeal No USA VISHAY SILICONIX INC. Tokyo, Japan. Tokyo, Japan. Tokyo, Japan Appeal decision Appeal No. 2012-8250 USA Appellant VISHAY SILICONIX INC. Tokyo, Japan Patent Attorney ITO, Tadashige Tokyo, Japan Patent Attorney ITO, Tadahiko Tokyo, Japan Patent Attorney ONUKI, Shinsuke

More information

Image Sensor Advanced Package Solution. Prepared by : JL Huang & KingPak RD division

Image Sensor Advanced Package Solution. Prepared by : JL Huang & KingPak RD division Image Sensor Advanced Package Solution Prepared by : JL Huang & KingPak RD division Contents CMOS image sensor marketing overview Comparison between different type of CMOS image sensor package Overview

More information

By Christopher Henderson This article is a continuation of last month s article on leadframes.

By Christopher Henderson This article is a continuation of last month s article on leadframes. Leadframes Part II By Christopher Henderson This article is a continuation of last month s article on leadframes. Today, we mainly use plated leadframes. Plated leadframes can help improve adhesion of

More information

Automotive Devices: Quad No- Lead (QFN) Technology with Inspectable Solder Connections

Automotive Devices: Quad No- Lead (QFN) Technology with Inspectable Solder Connections Automotive Devices: Quad No- Lead (QFN) Technology with Inspectable Solder Connections FTF-SDS-F0026 Dwight Daniels Package Engineer A P R. 2 0 1 4 TM External Use Agenda Wettable Lead Ends / Definition

More information

Aries. QFP microstrip socket. prepared by. Gert Hohenwarter. DC Measurement Results

Aries. QFP microstrip socket. prepared by. Gert Hohenwarter. DC Measurement Results Aries QFP microstrip socket DC Measurement Results prepared by Gert Hohenwarter 2/5/2005 1 Table of Contents TABLE OF CONTENTS... 2 OBJECTIVE... 3 METHODOLOGY... 3 Test procedures... 4 Setup... 4 MEASUREMENTS...

More information

Cypress Semiconductor Package Qualification Report

Cypress Semiconductor Package Qualification Report ackage Qualification Report QT# 054206 VERSION 1.0 December 2005 72-LD QFN (Quad Flat No-Lead) (unch Version, 10x10mm) NidAu, MSL3, 260 C Reflow Amkor-Korea (L) CYRESS TECHNICAL CONTACT FOR QUALIFICATION

More information

Two capillary solutions for ultra-fine-pitch wire bonding and insulated wire bonding

Two capillary solutions for ultra-fine-pitch wire bonding and insulated wire bonding Microelectronic Engineering 84 (2007) 362 367 www.elsevier.com/locate/mee Two capillary solutions for ultra-fine-pitch wire bonding and insulated wire bonding K.S. Goh a, Z.W. Zhong b, * a SPT Asia Pte

More information

Design and Development of True-CSP

Design and Development of True-CSP Design and Development of True-CSP *Kolan Ravi Kanth, Francis K.S. Poh, B.K. Lim, Desmond Y.R. Chong, Anthony Sun, H.B. Tan United Test & Assembly Center Ltd (UTAC) 5 Serangoon North Ave 5, Singapore 554916

More information

Module 4 Design for Assembly IIT BOMBAY

Module 4 Design for Assembly IIT BOMBAY Module 4 Design for Assembly Lecture 8 Case Studies - IV Instructional objectives The objective of this lecture is to exhibit how real components are designed in industry following some of the principles

More information

Thermal Cycling and Fatigue

Thermal Cycling and Fatigue Thermal Cycling and Fatigue Gil Sharon Introduction The majority of electronic failures are thermo-mechanically related by thermally induced stresses and strains. The excessive difference in coefficients

More information

A Study on Package Stacking Process for Package-on-Package (PoP)

A Study on Package Stacking Process for Package-on-Package (PoP) A Study on Package Stacking Process for Package-on-Package (PoP) Akito Yoshida, Jun Taniguchi, *Katsumasa Murata, *Morihiro Kada, **Yusuke Yamamoto, ***Yoshinori Takagi, ***Takeru Notomi, ***Asako Fujita

More information

Two major features of this text

Two major features of this text Two major features of this text Since explanatory materials are systematically made based on subject examination questions, preparation

More information

Altera APEX EP20K600CB652C8ES Programmable Logic Device Structural Analysis

Altera APEX EP20K600CB652C8ES Programmable Logic Device Structural Analysis April 27, 2006 Altera APEX EP20K600CB652C8ES Programmable Logic Device Structural Analysis Table of Contents List of Figures...Page 1 Introduction...Page 4 Device Summary...Page 5 Device Identification

More information

SiP packaging technology of intelligent sensor module. Tony li

SiP packaging technology of intelligent sensor module. Tony li SiP packaging technology of intelligent sensor module Tony li 2016.9 Contents What we can do with sensors Sensor market trend Challenges of sensor packaging SiP technology to overcome challenges Overview

More information

Design, Characteristics and Performance of Diamond Pad Conditioners

Design, Characteristics and Performance of Diamond Pad Conditioners Reprinted from Mater. Res. Soc. Symp. Proc. Volume 1249 21 Materials Research Society 1249-E2-4 Design, Characteristics and Performance of Diamond Pad Conditioners Doug Pysher, Brian Goers, John Zabasajja

More information

LSI Logic LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Controller 0.18 µm CMOS Process

LSI Logic LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Controller 0.18 µm CMOS Process LSI Logic LSI53C13 PCI-X to Dual Channel Ultra32 SCSI Controller.18 µm CMOS Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs

More information

Introduction of IMS Technology for Advanced Solder Bumping on Wafers / Laminates

Introduction of IMS Technology for Advanced Solder Bumping on Wafers / Laminates Introduction of IMS Technology for Advanced Solder Bumping on Wafers / Laminates Science & Technology IBM Research Tokyo Yasumitsu Orii, PhD Senju Metal Industry Co.,TW Deputy General Manager Lewis Huang

More information

CHAPTER 11: Testing, Assembly, and Packaging

CHAPTER 11: Testing, Assembly, and Packaging Chapter 11 1 CHAPTER 11: Testing, Assembly, and Packaging The previous chapters focus on the fabrication of devices in silicon or the frontend technology. Hundreds of chips can be built on a single wafer,

More information

Aim. Unit abstract. Learning outcomes. QCF level: 6 Credit value: 15

Aim. Unit abstract. Learning outcomes. QCF level: 6 Credit value: 15 Unit T3: Microelectronics Unit code: A/503/7339 QCF level: 6 Credit value: 15 Aim The aim of this unit is to give learners an understanding of the manufacturing processes for and the purposes and limitations

More information

Chapter 11 Testing, Assembly, and Packaging

Chapter 11 Testing, Assembly, and Packaging Chapter 11 Testing, Assembly, and Packaging Professor Paul K. Chu Testing The finished wafer is put on a holder and aligned for testing under a microscope Each chip on the wafer is inspected by a multiple-point

More information

Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap

Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap Silicon Photonics Transceivers for Hyper Scale Datacenters: Deployment and Roadmap Peter De Dobbelaere Luxtera Inc. 09/19/2016 Luxtera Proprietary www.luxtera.com Luxtera Company Introduction $100B+ Shift

More information

Bob Willis Process Guides

Bob Willis Process Guides What is a Printed Circuit Board Pad? What is a printed circuit board pad, it may sound like a dumb question but do you stop to think what it really does and how its size is defined and why? A printed circuit

More information

size (the programmed size of the undeformed ball).

size (the programmed size of the undeformed ball). Very Fine Pitch Wire Bonding: Re-Examining Wire, Bonding Tool, and Wire Bonder Interrelationships for Optimum Process Capability Lee Levine, Principal Engineer K&S Packaging Materials 2101 Blair Mill Road,

More information

"Low Cost Electroless Bumping for Ultra Fine Pitch Applications in 8" and 12" Wafers"

Low Cost Electroless Bumping for Ultra Fine Pitch Applications in 8 and 12 Wafers 1 "Low Cost Electroless Bumping for Ultra Fine Pitch Applications in 8" and 12" Wafers" Elke Zakel, Thomas Oppert, Ghassem Azdasht, Thorsten Teutsch * Pac Tech Packaging Technologies GmbH Am Schlangenhorst

More information

Compression Molding. Solutions for 3D TSV and other advanced packages as well as cost savings for standard package applications

Compression Molding. Solutions for 3D TSV and other advanced packages as well as cost savings for standard package applications Compression Molding Solutions for 3D TSV and other advanced packages as well as cost savings for standard package applications 1. Company Introduction 2. Package Development Trend 3. Compression FFT Molding

More information

APPLICATION NOTE. BGA Package Overview. Prepared by: Phill Celaya, Packaging Manager Mark D. Barrera, Broadband Knowledge Engineer.

APPLICATION NOTE. BGA Package Overview. Prepared by: Phill Celaya, Packaging Manager Mark D. Barrera, Broadband Knowledge Engineer. Prepared by: Phill Celaya, Packaging Manager Mark D. arrera, roadband Knowledge Engineer PPLICTION NOTE PPLICTION NOTE USGE This application note provides an overview of some of the unique considerations

More information

MMIC 2-18GHz 90 Splitter / Combiner. Green Status. Refer to our website for a list of definitions for terminology presented in this table.

MMIC 2-18GHz 90 Splitter / Combiner. Green Status. Refer to our website for a list of definitions for terminology presented in this table. MMIC 2-18GHz 90 Splitter / Combiner MQS-0218 1 Device Overview 1.1 General Description The MQS-0218 is a MMIC 2GHz 18GHz 90 splitter/combiner. Wire bondable 50Ω terminations are available on-chip. Passive

More information

3D TSV Micro Cu Column Chip-to-Substrate/Chip Assmbly/Packaging Technology

3D TSV Micro Cu Column Chip-to-Substrate/Chip Assmbly/Packaging Technology 3D TSV Micro Cu Column Chip-to-Substrate/Chip Assmbly/Packaging Technology by Seung Wook Yoon, *K. T. Kang, W. K. Choi, * H. T. Lee, Andy C. B. Yong and Pandi C. Marimuthu STATS ChipPAC LTD, 5 Yishun Street

More information

Technical Note 1 Recommended Soldering Techniques

Technical Note 1 Recommended Soldering Techniques 1 Recommended Soldering Techniques Introduction The soldering process is the means by which electronic components are mechanically and electrically connected into the circuit assembly. Adhering to good

More information