The Big Picture on the Small World of MEMS

Transcription

1 The Big Picture on the Small World of MEMS 2009 IWLPC MEMS Plenary Session 29 th October 2009 Raj Gupta, PhD Volant Technologies, Inc.

2 Outline Background. Historical perspective. IC s vs. Sensors Challenges facing packaging and test of sensors: During development. In low-to-mid volumes. For high volumes. Options available for testing sensors in high volumes. Trends in current approaches to testing in high volume. Conclusions and strategies going forward. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 2

3 About Volant Technologies Served industry for more than a combined 60+ years. Broad and deep business & technical expertise in: Silicon sensors specifically pressure & acceleration. Sensor integration, and wireless electronics. Materials testing, and finite-element modeling. Focus areas: Product & Technology Strategy. Product Execution. Business Development. Foundry Partnering & Prototyping. Cost Reduction, Miniaturization, and Performance Improvement. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 3

4 Academic Industry Actuators Bell Laboratories W. G. Pfann, R. N. Thurston, C. S. Smith, Art Zias, W. P. Mason Kulite A. D. Kurtz Microsystem s J. Sanchez, W. Wright Honeywell K. Namura Art Zias The ChartCase-Western Reserve /6/2010 Copyright 2009, Volant Technologies, Inc. 4 DISCOVERY CalTech R. Feynman, Plenty of Room at the Bottom G.E. Art Zias Please send corrections & comments to: gupta@alum.mit.edu Art Zias Endevco B. Wilner COMMERCIALIZATION Art Zias Fairchild Don Lyman H. Keller National Semiconductor Bill Hare D. Dauenhauer & J. Bryzek J. Mallon J. Mallon Westinghouse H. Nathanson & R. Wickstrom Stanford University J. Angell & J. Meindl IBM San Jose, CA Keller H. Keller P. Barth K. Wise IC Transducers Lyman, Zias & Gene Burke Art Zias Carnegie Mellon John Gragg MOTOROLA U. C. Berkeley R. Muller, R. White J. Bryzek W. Ko Cognition F. Perrino COST REDUCTION & GM Delco APPLICATION EXPANSION M.I.T. S. Senturia University of Michigan K. D. Wise S. Terry J. H. Jerman S. Saadat Rosemount T. I. L. Hornbeck Motorola J. Gragg University of Wisconsin H. Guckel J. Knutti H. Allen Art Zias J. Knutti, H. Allen, K. Petersen K. Petersen Microsensor Technology S. Terry, J. H. Jerman, S. Saadat K. E. Petersen K. Petersen Foxboro ICT D. Lyman Ametek J. Bryzek J. Bryzek SenSym A. Zias R. Howe Transensory Devices D. Lyman IC Sensors Lyman & Bryzek Burr-Brown CapTorr Art Zias MICROMACHINING P. Barth NovaSensor Petersen, Barth, Bryzek, Mallon Bryzek

5 Where Do We Find MEMS Today? Apple iphone Knowles SMT Microphone More obvious examples: iphone and Nintendo Wii motion sensors. Silicon microphones in cell phones. TI s Digital Light Projection (DLP ) and pico-projectors. Others we don t see: Nintendo Wii TI DLP Inkjet print-heads. Automotive applications for fuel, tire, and attitude sensing. Medical applications for pressure, motion, and drug delivery. Microbolometers, silicon oscillators, micro-optics, microtips & probes, RF MEMS, micro fuel-cells 1/6/2010 Copyright 2009, Volant Technologies, Inc. HP Inkjet Printhead 5

6 Disposable Blood Pressure Evolution First volume MEMS sensor. Package (Cost) and volume driven design. Cost: $800 $28 $1.35 Volume: 1976 ~ 100K / yr 1979 ~ 100K / mo 1999 ~ 100K / day Weight reduction 1 ½ lbs < 2 oz. PRT Chip 1/6/2010 Copyright 2009, Volant Technologies, Inc. 6

7 ADI s Accelerometer Evolution Smaller Cheaper Header 1 Cerdip/Cerpak LLC QFN WSP 10 x 10 x 7 mm 3 10 x 10 x 5 mm 3 5 x 5 x 2 mm 3 4 x 4 x 1.45 mm 3 2 x 2 x 0.9 mm 3 Inertial market quickly becoming the largest volume MEMS market. Volume & ASP s: ASP: 1985 ~ $ ~ $ ~ $ ~ $0.60 CAGR 2003 ~ 2008: 21% for accelerometers $351M $893M 19% for gyroscopes $348M $833M 2 Courtesy of Analog Devices, Inc. 1 Rob O Reilly imems Test, What s Different?, Jan Yole Développement, /6/2010 Copyright 2009, Volant Technologies, Inc. 7

8 Key Enabling Technologies & Trends Technologies: Capping for mechanical protection Through Silicon Vias (VIA) Hermetric & Vacuum-level Wafer bonding for performance High-aspect ratio MEMS (HARMS). Trends: 8 CMOS toolset Fabless designs Hybrid MEMS-CMOS integration WLP 1/6/2010 Copyright 2009, Volant Technologies, Inc. 8

9 What Does WLP Mean for MEMS? Capping at the wafer-level: Provides robustness from dicing, and overall mechanical strength. Miniaturization. Reduces final assembly size and cost. Some performance advantages gains. Better hermeticity with gettering and anti-stiction, as needed. In combination with TSV s: Further size reduction. Cost reduction of assembly. Integration with CMOS and digital calibration and better performance. Some back-end testing moved closer to die-level. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 9

10 Why is it Package Test Trim? Cost Sensors sense everything. Senturia, Every MEMS sensor is also a 1 st -order strain sensor. Packaging, no trimming Singulated Sensor Die Trimming ideal Trimming & Auto-referencing What makes this different from IC s? Electronics (especially digital) can be easily separated from mechanical effects. Crystal silicon perfected for electronics over more than 75 years. Silicon is only one material among many used by MEMS sensors and actuators. Many different end-applications and packaging needs. Accuracy & Performance 1 1 Adapted from Carver & Looney, MEMS accelerometer calibration optimizes accuracy for industrial applications, October 27, /6/2010 Copyright 2009, Volant Technologies, Inc. 10

11 Pondering the Big Picture What can we learn from 50+ years of silicon sensor history? Can we break the paradigm of Package Test Trim? Is it possible? Show me the money Where should our resources be focused? How do choices we make during design, development, and prototyping affect our readiness for manufacturing? 1/6/2010 Copyright 2009, Volant Technologies, Inc. 11

12 Experiences & Observations Packaging, test, and performance intimately linked. Sufficient variability in process to require testing along the way. Many stages of testing and different types of tests called upon. Testing becomes progressively more involved and complex further into the process flow and product integration. Process flow often not vertically integrated and poor feedback of test data to previous stages. Testing affects throughput, and it is often a rate-limiting step. Inherent, intrinsic limitation due to mechanical time-constants. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 12

13 Costs 100% Packaging & Testing Testing Only Sensor chip cost Percentage of Total Cost Development Low-to-Mid Volume High Volume Log (Volume) 1/6/2010 Copyright 2009, Volant Technologies, Inc. 13

14 Types of Tests Process: Dopant levels Materials & geometry Electrical: Continuity / ESD Burn-in Transduction Performance: Sensitivity Calibration Mechanical Integrity Physically broken sensor chip Hermiticity / encapsulant Drift / offset / TC s Shock Intra-process-level Wafer-level Die-level Packaged-level Trimming Assembly Process Flow 1/6/2010 Copyright 2009, Volant Technologies, Inc. 14

15 Ultimate Vision Because final test is and will be the minimum requirement to guarantee quality of the materials produced The goal is to eliminate as many tests as possible to reduce the wafer start to customer delivery cycle-time. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 15

16 Development: Process Sensitivity Difficult to test for overall performance at wafer & die level. Only inferences can be made based on material properties, geometry, and electrical characteristics. Industry standard test structures & procedures lacking, because: 1. processes / run-cards are intensively variable and constitute trade secrets, 2. there are a range of materials and transducer types, and 3. material properties are highly process sensitive. This will remain true in low-to-mid volume applications. Standardization possible in high-volume and with fabless approaches. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 16

17 Low-to-Mid Volume: Customization Example: piezoresistive pressure sensors Die Package Examples Applications DIP T0-8 INP various others Meteorology Farming Military Medical Automotive HVAC many, many more Variants may include open or closed bridge, absolute vs. gauge vs. differential Typically 5 pressure ranges, with modest process changes required for each. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 17

18 High Volume: Throughput Good news: Fewer die variants good yield at die level limited # of packages $14 $12 $10 $8 Cost w /o Test before trimming Cost w / Test before trimming Challenges: well-defined operating conditions. 1 st : Improving throughput: Final assembly, test & trim IS the bottleneck. 2 nd : Reducing fall-out & handling issues / improving assembly yield. Examples of tests affecting throughput: Testing over mechanical frequency mechanical placement, settling time, hysteresis Testing over pressure pressure source stabilization, eliminating leaks, hysteresis Testing over temperature thermal lags, hysteresis Testing over time for reliability, burn-in. Laser trimming for analog calibration & Package / die / sensor(s) tracking. $6 $4 Package + Assembly: $3 Test (in high volume): $1 $2 Die: $1 % Die $0 Yield 30% 40% 50% 60% 70% 80% 90% 100% 1/6/2010 Copyright 2009, Volant Technologies, Inc. 18

19 High-throughput Test Equipment Much still custom, e.g. Measurement Specialties, GE Sensing, Motorola/Freescale, Honeywell, Merit Medical, MEMSIC, etc. Tests are often application specific, e.g. inkjet print heads, micromirrors Limited by lack of package standardization. Solution providers emerging: MultiTest Electronic Systems Mensor Unholtz-Dickie Teradyne Blue M (Lunaire) National Instruments Consumer electronics volume for accelerometers, gyros, and IMU s is creating a market for test equipment suppliers. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 19

20 Off-the-Shelf Volume Test Equipment Best systems handle 8,000 units per hour; gravity draw. Test is still slow. Some package standardization around DIL & SO. Multi-unit test parallelization, to obviate sensor mechanical timeconstants. Trends: Leadless packages such as LGA, QFN, MFL attractive for CE miniaturization. Smaller packages allow faster parallel testing. Reduced thermal lag. Reduced mass on shaker. Smaller package electrical pads pose problem with reliable connectivity during test. Multiple sensors in one package. MultiTest InStrip test jig 1/6/2010 Copyright 2009, Volant Technologies, Inc. 20

21 Approaches for the Future Goal: To reduce the burden of testing at final assembly. A mixture of approaches: Moving back-end testing to the die-level, e.g. Wafer-Level Packaging (WLP) and testing. Built-in Self-Test (BIST). Higher performance sensor die. Better assembly solutions. Designing for Test (DFT). Virtualization of Test? 1/6/2010 Copyright 2009, Volant Technologies, Inc. 21

22 Solutions at the Die Level Stress-immunity: Allows more slop in assembly, keeping costs low, or Introduces package-level performance repeatability, reducing # of calibration test points. Possibilities: Cheaper assembly possible for low-performance applications. Tighter tolerances on material & geometry specifications allows greater flexibility to trim. Challenges: Obviating test & trim at final assembly for ideal performance still unclear. Alternatively: Remove off-chip analog trim by an All-digital calibration approach. e.g. tall constraints 1/6/2010 Copyright 2009, Volant Technologies, Inc. 23

23 Built-In Self Test (BIST) Ideally suited for devices that can be electrostatically actuated. Process characterization: In-situ pull-in and resonance test structures (M-TEST) for mechanical property extraction & geometry characterization. Device characterization: Use electrical signals to simulate mechanical stimuli. Analog Devices pioneered this concept with their ADXL-50 in 1990 s. Approaches to apply this to pressure are in venture phase. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 24

24 Designing for Test (DFT) Adding testability features at the die-level that allow assessment of the manufacturing process. In-situ test structures. Structures that help monitor extraneous - environmental parameters that affect sensor performance. Requires parameterization of variables affecting performance all the way through assembly. DFT establishes a communication framework for designers, fabs, assemblers, and final testers. + V c co ntact 2µm POLYSILICON SILICON 2µm frees pac e gap 0.5µm NITRIDE 1/6/2010 Copyright 2009, Volant Technologies, Inc. 25

25 Areas in Continual Improvement Tighter control of assembly. Designs immune to packaging. Better feedback into design. Designing for test. Better automation for test. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 26

26 Conclusions Understanding of end application needs necessary: Cannot plan on product pieces in isolation. Program management highly critical. Cycle-time and cost suggests pushing as much backend testing up to wafer-level, so as to: Reduce cost for testing & customization at package level. Increase throughput. Test early and test often. WLP and Wafer-Level Test (WLT) is critical to this evolution. 1/6/2010 Copyright 2009, Volant Technologies, Inc. 27

27 Contact Information Raj Gupta, PhD Owner, Volant Technologies San Francisco, CA DSK: WEB: gupta at terahz.org 1/6/2010 Copyright 2009, Volant Technologies, Inc. 28