LED Cost and Technology Trends: How to enable massive adoption in general lighting

Transcription

1 LED Cost and Technology Trends: How to enable massive adoption in general lighting SEMICON West 2011 Moscone Center, San Francisco June 13 th 2011 Lumileds Lumileds OSRAM Aixtron CREE OSRAM OKI OSRAM 45 rue Sainte Geneviève, F Lyon, France Tel: Fax: Web:

2 Content Rationale: why are cost reductions necessary? LED die singulation. Packaging substrates Conclusion

3 Packaged LED: Revenue by Application (Base Scenario) Sources: Yole Développement? General Lighting to take off only if cost/performance can beat incumbent technologies

4 Upfront Cost: Sticker Shock: All sources: ~ 800 lumens Warm White Tier 1 brand <$1 $3-5 $40 Need to reduce $/lumen!

5 Cumulated Cost of Light = Upfront Cost + Energy Cost + Maintenance Cost

6 Cumulated Cost: Examples Standard A19 Warm white Bulb 800 lumen No maintenance cost (residential use) Sources: Yole Développement $40 LED Bulb: LED cumulated cost remains higher than Fluorescent light sources

7 Cumulated Cost: Examples Sources: Yole Développement $10 LED Bulb: LED becomes significantly cheaper than other light source + upfront cost more acceptable trigger for massive market adoption

8 The Path to Cost Reduction Cost = $/Lumen Manufacturing Efficiency: Higher equipment throughput Higher yields Economy of scale LED performance: Higher Efficiency (lumen/w) More light per chip

9 20 Key Technologies & Research Areas Relative Impact on LED cost of ownership Manufacturing Cost Alternative substrates #2: Si Large Diameters Substrates: 4, 6, 8 Lithography: Dedicated tools, Higher Throughput Testing and Binning: Wafer Level, Higher throughputs Die Singulation Increased throughputs and yields Contacts/Electrodes: Transparent contacts/electrode materials and patterns Encapsulation Materials and Optics: Ageing and optical properties Contacts & Electrodes: p to n layer VIAS Epitaxy: Cluster tools - New Epi Technologies Substrate Separation: Laser Lift Off, other separation techniques Wafer Level Packaging: Silicon TSV, Wafer Level Optics Phosphors: Conversion efficiency, Color Rendering IP free phosphors Mirrors: Resonant Cavities Mirrors: Improve reflectivity/electrical properties Surface Texturation: Patterned substrates / Roughening Epitaxy MOCVD: Higher yields and Throughputs - Improved Material quality Phosphors: Quantum dots Phosphors Alternative substrates #1: GaN, ZnO, Si, Engineered substrates Thermal Management: New materials for packaging Surface Texturation: Photonic and Quasi Photonic Crystals Current Droop / Green Gap / LED Structures Sources: Yole Développement LED Performance

10 Typical Process Flow: Carrier wafer Carrier wafer Epitaxial substrate Epiwafer Die Lens Each step represents an opportunity for cost improvement

11 Typical Process Flow: Die

12 LED Singulation: 4 different processes can be used for LED die singulation: Dicing Process 1) Blade Dicing 2) Laser Dicing LED Epiwafer 3) Diamond Scribing Breaking Scribe & Break 4) Laser Scribing Scribed Epiwafer LED dice

13 Critical Parameters: Dicing and LED Cost Reducing street width increase die/wafers count. Cutting speed increase equipment throughput Cutting yields good die per wafers Performance some processes reduce brightness: lower die value Street Width Scribing Depth Kerf Loss Picture: JPSA Picture: JPSA Picture: A.L.S.I

14 Improving Throughput: Main Factors influencing Dicing Speed: Materials: GaN Sapphire GaAs SiC Si, Ge Cu, CuW, Mo Scribing depth: Indexing speed: Vertical LED chip bonded on metal substrate Scribe depth versus scribe speed for a 266nm laser using 1W average power at 30kHz (source: Oxford Lasers) Recasting effect on metal after laser scribing Trade off between speed and depth Indexing / alignment times are critical to throughput

15 Increasing Speed (1): Serial Multibeam Laser Dicing Increasing laser dicing speed requires higher laser energy: damages the components. Solution: Serial Multibeams Expander Diffractive Optical Element Laser Beams Multibeam vs. high energy single beam (right) beam splitting technique (ALSI) Wafer 1 st pulse n th pulse Side view of a 650 um thick GaAs wafer scribed with a mutibeam laser (ALSI) Illustration of Multibeam laser dicing process (source: ALSI)

16 Increasing Speed (2): Parallel cuts Comparison of wafer throughput vs. scribing speed: Hypothesis: 2 wafer, 350 um die, 20 um x6street width. 7 Results: a 6x speed increase would lead to a 2x improvement in wafer throughput: Speed (mm/s) Wafer/ hour x Increase factor Speed increase Wafer Throughput increase Source: Yole Scribing Speed (mm/s) Due to high alignment and indexing time, increasing the scribing speed has a comparatively limited impact on system throughput: For small die sizes, significant throughput improvements are possible with parallel cuts systems. Mechanical: Dual Spindle (available) Laser: Multibeam (coming soon) Concept for a parallel multibeam scribing system

17 Reducing Street Width: Stealth dicing Short-pulse, high-power laser beam weakens the material under the surface wafer is diced from the inside Wafer Process overview (Hamamatsu photonics) Benefits: Much reduced kerf loss small street width No debris on wafer or contamination on the optics Clean edges: little/no loss in brightness Drawbacks: Sapphire breaking after stealth dicing (Disco) Higher capital cost. Despite the name dicing, a breaking step is still required for LED due to the small die size. Not available for all materials. Si and Sapphire OK

18 Alternative Die Singulation Method: Etching Startup Verticle developed hexagonal shaped LED chips: Improved current spreading Almost circular beam profile Increased die count Die separation is achieved by chemical etching after removal of the initial sapphire substrate Allows the processing of multiple wafers simultaneously. Honeycomb chips before separation ( Top) and SEM Image of separated chip (Bottom). Singulated chips

19 Singulation: Conclusions Tremendous growth of laser based dicing since 2005: high capital cost but high throughput. Laser solutions keep improving are not (yet?) suitable for all structures/materials. Choice is application/material dependent and made on a case by case basis. Singulation techniques improving constantly to respond to new challenges and reduce LED manufacturing cost down

20 Performance: Package Substrate Die

21 LED Thermal Management: Why? LED: up to 40% of the of the energy turned into heat! Electric Loss Quantum Loss Light Extraction Loss Source: Osram LED DON T like heat, performance decrease: Brightness, Efficiency Lifetime Color stability

22 Thermal Management Stay cool!

23 Thermal Management Main design options for high power LEDs ( 1 W) LED Die Substrate Only Heat slug Ceramic Silicon (Wafer Level Packaging) Organic / Heat slug Si Submount Substrate Ceramic Chip on Board Optek Lednium Lumileds Luxeon Rebel Viscera Technology Lumileds Luxeon Cree-X-lamp PCB / MCPCB MCPCB

24 High-Power LED Packages Examples Single Large Die (1 die, typical dimension: 0.5 to 1.5 mm) Multiple Large Dice (3 to 25 dice, typical dimension: 0.5 to 1.5 mm each) Small/medium dice Array (20 to 100 dice, typical dimension: 250 to 500 um each) Single or Multi Jumbo Die 1 to 6 dice, typical dimension 2 to 5 mm each) Lumileds Cree Luminus Device Lumileds Luminus Device Osram Osram Cree Osram Edison Opto Luminus Device

25 Wafer Level Packaging (WLP): Packaging of an LED at wafer level, rather than assembling the package of each individual unit after wafer dicing. Packaging wafer LED wafer Note: in this example, the LED chips are singulated before being positioned onto the package wafer (= Chip to Wafer packaging) LED die Phosphor Wafer Level Optic Mirror coating Solder Bump Solder / Metallization 1) Wafer level preparation of the package substrate 2) Chip to wafer 3) Wafer level interconnect, phosphor deposition, encapsulation, optic. 4) LED package separation. Overview of Chip to Wafer LED WLP process Wafer Semicon Level West Packaging 2011

26 Wafer Level Packaging Hymite (technology acquired by Touch Microsystem Technology in 2010) Courtesy of Hymite

27 Wafer Level Packaging Silicon Base Development Inc VisEra Technology Pictures: Company Pictures: Company, System Plus consulting

28 WLP operations for high power LEDs Many LED packaging operations could be carried out at the wafer level: Wafer level Optics 3D Silicon substrates Embedded Zener diodes Wafer level Phosphor coating WLP operations for High Power LEDs Wafer level coating of reflective layer Bumping at the wafer level Wafer to wafer bonding (LED on package substrate)

29 Silicon Substrates and WLP Benefits: Silicon: thermal conductivity, further improved by the use of copper-filled Through Silicon Vias (TSV) Reliability: monolithic assembly, reduced wire interconnect, good CTE match with GaN Wafer level testing Cost: Wafer Level Manufacturing: cost effective. but: Copper-filled TSVs for 3D electrical redistribution and heat dissipation are still expensive. So far only for high performance LEDs Other options: WLP on ceramic substrates. EMC3D TSV Cost of ownership roadmap (courtesy: EVG / EMC3D)

30 High Power LED Substrate Market Penetration Forecast by substrate type Yole Développement Note: technology adoption rates for High Power (>1W) LED package only

31 Conclusion: The Path to Cost Reduction Lack of standards: Technology choices application and manufacturer dependent. 10x cost reduction in packaged LEDs cost? Not easy but achievable through a combination of: Technology improvements: efficiency + more lumens per chip. Manufacturing improvements: dedicated LED tools, automation, inline testing. Economies of scale Higher integration Standardization LED industry maturing and reaching critical mass to enable development of dedicated tools. Semiconductor veteran companies bring additional expertise and best practices