Scientific (super)computing in the electronics industry

Transcription

1 Scientific (super)computing in the electronics industry Wil Schilders Centre for Analysis, Scientific Computing and Applications & Platform Wiskunde Nederland SARA Superdag, December 1, 2010

2 Centre for Analysis, Scientific Computing and Applications Combines all activities related to analysis at the Department of Mathematics and Computer Science of Eindhoven University of Technology (TU/e). Major research objective is to develop new and improve existing mathematical (both analytical and numerical) methods for a wide range of applications in science and engineering. Extensive collaboration with researchers in the technical sciences as well as cooperation with industrial partners is vital. Located at CWI (Science Park 123) National organisation founded by Koninklijk Wiskundig Genootschap and Nederlandse Vereniging van Wiskundeleraren Improved advocacy of mathematics Policy determined by Committees on Education, Research, Publicity, Publications and Innovation bureau@platformwiskunde.nl Website (operational soon):

3 Warning No success stories regarding use of high performance computing! Merely opportunities Electronics industry can benefit much from supercomputing Better understanding Faster time to market Not seen in electronics industry

4 Contents High performance mixed signal (Semi-)automatic design Multi-core analog simulation Conclusions

5 High Performance Mixed Signal December 6,

6 High Performance Functional Performance Speed, bandwidth, bit-rate Accuracy, resolution Gain Linearity, dynamic range Efficiency Power Cost Autonomy Robustness & versatility Reliability Withstand harsh environments Flexibility Adaptability Mixed Signal is the optimized mix of analog and digital Radio Interface Sensor Actuator Mixed Signal Digital Digital Processing / Storage Power Philips Research <Title> - <Author>,< MMMM dd, yyyy> 6 6

7 High Performance Mixed Signal Requires innovative process technology, circuit design expertise and architectural insight Mixed-signal businesses have attractive margins and show healthy growth in the following areas: Energy Health Mobility Security Philips Research <Title> - <Author>,< MMMM dd, yyyy> 7

8 The Chief Technology Officer s Headache... How to cope with the ever-increasing complexity of System-on-Chip (SoC), System-in-Package (SiP) and Software to continue bringing ever-greater Sensory Experiences to consumers? extern int a[]; extern int b[]; void rateconv(int n) { int i; for (i = 0; i<n/2; i++) { a[i] = b[2*i+1] + b[2*i]; } } int main(int argc, char *argv[]) { rateconv(atoi(argv[1])); } Plenary Talk/VLSI 2007/Rene Penning de Vries 8 <Title> - <Author>,< MMMM dd, yyyy> Janu ary

9 ...and Why He/She Doesn t Sleep at Night IP and Software Heaven Design Design and Implementation are linked... System Design... but pull in opposite directions Implementation Deep Sub-Micron Hell Plenary Talk/VLSI 2007/Rene Penning de Vries 9 <Title> - <Author>,< MMMM dd, yyyy> Janu ary

10 Log Scale Plen ary Complexity Crisis! Design & Software Crisis Gates/cm 2 Moore s Law (59% CAGR) Design Productivity (20-25% CAGR) Widening Gaps Will Trigger Paradigm Shift! Software Productivity (8-10% CAGR) 0.35µ 0.25µ 0.18µ 0.15µ 0.12µ 0.1µ 0.045µ January 10,

11 Coping With Complexity Key Trends More (Sub)systems on one SoC More Complexity More SW Content More (programmable) cores in single SoC Less Power Less Cost Better TTM First Time Right January 10, 2007 Solution Efficient system integration. Re-configuration Move to higher abstraction levels Separate concerns (Functions vs Architecture) SW/HW co-design. Component Technology Multi-core debugging and programming System power analysis and power-aware design Architecture exploration. DfM Design & verification productivity Maximise automation & ReUse Hardware & Software quality Verification & validation quality Designers are coping with limitations of software, but maybe the solution is in the hardware! 11 Plen ary

12 Law of (Gordon) Moore The engine behind the chips industry is Moore s law: every 2 years the speed and density of transistors is doubled <Title> - <Author>,< MMMM dd, yyyy> 12

13 Moore s law also holds for computational techniques! These effects strengthen each other! Success of analog circuit simulators 13

14 Plen ary (Semi-)automatic design January 10,

15 New challenge: semi-automatic design Develop and deploy a semi-automatic RF-AMS IP design methodology based on fully parameterized ROD cells and efficient automatic place, route, extraction and optimization <Title> - <Author>,< MMMM dd, yyyy> 15

16 New challenge: semi-automatic design Develop and deploy a semi-automatic RF-AMS IP design methodology based on fully parameterized ROD cells and efficient automatic place, route, extraction and optimization <Title> - <Author>,< MMMM dd, yyyy> 16

17 New challenge: semi-automatic design Develop and deploy a semi-automatic RF-AMS IP design methodology based on fully parameterized ROD cells and efficient automatic place, route, extraction and optimization <Title> - <Author>,< MMMM dd, yyyy> 17

18 A PCircuit is a parameterized layout of: Electronic component with more features than offered by the standard technology library Electronic circuit that consists of parameterized layouts of the previous one We can build a complete chip with parameterized blocks All sub blocks can be parameterized according to the needs of the system Derivatives and technology ports easy with Pcircuits <Title> - <Author>,< MMMM dd, yyyy> 18 CI&T Integ

19 Using PCircuits in optimization loop reduces labor intensive extraction and modification on layouts including parasitics during verification Designers can focus on more technically challenging problems performance simulator Design assistant modify design parameters ~10 minutes <Title> - <Author>,< MMMM dd, yyyy> 19 CI&T Integ

20 Key aspects of (semi-)automatic design Methodology addresses issues by 1. Design using parameterized layout cells 20 increase reuse enable fast design derivatives fast design space exploration including parasitics simplify technology port of designs 2. Layout optimization to include parasitics and interconnect semi-automatic layout optimization for performance tuning Key difference layout cells are now programmed instead of manual drawing design becomes piece of software code <Title> - <Author>,< MMMM dd, yyyy>

21 (semi-)automatic design: implementation Two aspects: 1. Parameterized cells and circuits: schematic, symbol, and layout Using programming languages Skill with Relative Object Design (ROD) ( Python) PCell is a new concept; we have extended it to Pcircuits (higher level) 2. Semi-automatic optimization of Pschematics and Playouts Using languages Skill and Ocean Solutions being developed inhouse in electronics companies <Title> - <Author>,< MMMM dd, yyyy> 21

22 Required: understand interactions! In RF power products, high frequencies, high currents, and large dimensions (compared to wavelength) come together Obtain high product performance by understanding coupling mechanisms in overall product Gain insight / understand / clarify mechanisms Close loop between simulation and measurement Verify using dedicated test structures 22 <Title> - <Author>,< MMMM dd, yyyy>

23 Account for interactions in complete product die pre-match capacitor 23 Interaction PCB, package / leadframe and die Current distribution over transistor width Die-to-die and intra-die Current crowding, eddy currents Return path <Title> - <Author>,< MMMM dd, yyyy>

24 Core simulation task: coupled device, circuit, EM (in optimization loop with many iterations) Behaviour of interconnect structure via solution of Maxwell equations Behaviour of transistors summarized in so-called compact models up to 50 parameters constructed by physicists/mathematics Semiconducting substrate, behaviour via extraction software complex R or RC networks L A R G E c o m b i n e d c i r c u i t 24

25 Required: high-speed analog circuit simulation Layout effects appear as large extracted networks that are added to the original (much smaller, but nevertheless huge) circuits Simulator must be able to cope with such extremely large circuits Problem: Most simulators cannot handle millions of equations..and if they can, it takes hours per optimization step, and several weeks for a full optimization! <Title> - <Author>,< MMMM dd, yyyy>

26 Plen ary Multi-core analog simulation January 10,

27 Analog Simulation Benchmark Many simulators are available for electronic (analog) circuit simulation nowadays In-house simulators like Pstar (NXP) and Titan (Infineon) Commercial products like Spectre, Spice, BDA Trend in electronics industry to use commercial tools Natural questions: which one is best? Does it outperform the in-house code? Are there multithread capabilities, and do they enhance simulations? Performance for huge extracted circuits ( optimization loop!) <Title> - <Author>,< MMMM dd, yyyy>

28 Many analog simulators.. In-house Pstar (NXP) Titan (Infineon) Commercial XA BDA Spectre Spectre Turbo Virtuose APS Gsim FineSim Eldo Multithreading in preparation Top performance only using multithreading <Title> - <Author>,< MMMM dd, yyyy>

29 Results for 12 bit ADC (extracted netlist)

30 Observation with regard to multithreading It appears from our experiments that multi-threading in an engineering environment has limited added value beyond 4 cores. In some cases even no improvement beyond 2 cores was observed. So unless specific hardware is made available for running such tools for instance using a separate queue for high performance jobs it is not realistic to expect a performance improvement using any additional cores. Most high performance simulators are transient only. Most of them have no support for RF analyses nor small-signal frequency domain (AC) nor harmonic balance. This means that one will always require a basic simulator to execute these analyses there will never be a complete replacement if such analyses are not covered. <Title> - <Author>,< MMMM dd, yyyy>

31 By the way

32 Filterbank example from Analog simulation benchmark report 32

33 Philips Research <Title> - <Author>,< MMMM dd, yyyy> 33

34 Philips Research <Title> - <Author>,< MMMM dd, yyyy> 34

35 Result of new Pstar simulation capability on filterbank problem (V6.0.1) Many hours for input 1 hour for DC analysis Success due to state-of-the-art linear algebra (AMD ordering and BBD implementation) 35

36 Plen ary Conclusions January 10,

37 Conclusions No success stories using supercomputing in the electronics industry Current analog simulators are moving into multi-threading, but the performance is far from optimal So far, performance improvements only from algorithms It is vital to understand all interactions in order to cope with increasing complexity My opinion: much more effort should be devoted to the use of high performance computing! It will lead to better understanding and less work-arounds It will aid the new design paradigm based on parameterized cells and circuits It will dramatically improve time-to-market, and hence give a competitive edge <Title> - <Author>,< MMMM dd, yyyy>