Super J-MOS Low Power Loss Superjunction MOSFETs

Transcription

1 Low Power Loss Superjuctio MOSFETs Takahiro Tamura Mutsumi Sawada Takayuki Shimato ABSTRACT Fuji Electric has developed superjuctio MOSFETs with a optimized surface desig that delivers lower switchig. I these chips, gate legth ad chael desity were adjusted to optimize the gate-to-drai capacitace ad threshold voltage, thus achievig lower tur-off. For devices rated at 6 V/2 A/.19, a extremely low tur-off of 16 μj at the tur-off dv/dt of kv/μs was realized. Power effi ciecy is over 94.%, eablig compliace with the 8 PLUS certificatio. 1. Itroductio Recetly, i respose to heighteed iterest i global evirometal protectio through coservig eergy ad reducig CO 2 emissios, lower levels of power are sought i so-called IT equipmet, such as PCs ad servers. I order to reduce the power i IT equipmet, the power coversio devices used i IT equipmet must be made more efficiet, ad the techology that eables this higher efficiecy is power semicoductors. The power semicoductors istalled i power coversio equipmet operate as switchig devices, ad their power cosists of coductio while the device is i its o-state, ad switchig whe the device chages from its o- to off-state or from its offto o-state. To achieve higher efficiecy ad lower i power coversio equipmet, both types of must be reduced. This paper reports o Fuji Electric s successful developmet of a (Superjuctio MOSFET) that achieves low switchig as a result of optimizatio of the SJ-MOSFET surface structures from a theoretical perspective ad a improved tradeoff relatioship betwee tur-off E off, geerated whe the device chages from its o- to off-state, ad the value of tur-off d V /d t, which idicates the timechage of drai-to-source voltage at the time of turoff. 2. Characteristics of the a covetioal power MOSFET, the SJ-MOSFET features a sigificatly improved trade-off relatioship betwee the device breakdow voltage BV DSS ad the specific o-resistace R o A, ad because the coductio ca be reduced dramatically, SJ-MOSFETs are beig used more ad more i power coversio equipmet. Figure 1 shows schematic cross-sectioal views of a SJ-MOSFET ad a covetioal MOSFET. The SJ-MOSFET has a structure i which p-pillars ad - pillars are arraged alterately i the drift regio. By arrowig the width of each pillar, the impurity cocetratio i the drift regio ca be icreased without decreasig the breakdow voltage, ad therefore the o-resistace ca be reduced. (1)~(4) Furthermore, because a SJ-MOSFET has sigifi- p-base Source + + p+ + Drai Gate (a) Covetioal MOSFET p-base Source p L g + + p+ + Drai p Gate (b) SJ-MOSFET issue: Power Semicoductor cotributig i eergy ad eviromet regio The use of a SJ-MOSFET is oe way to reduce both coductio ad switchig. Compared to Fuji Electric Co., Ltd. Fig.1 Schematic cross-sectioal views of power MOSFETs *1: Miller period: See supplemetal explaatio 2 o page

2 catly smaller R o A tha a covetioal MOSFET, its gate-to-drai capacitace C GD is also sigificatly smaller. As a result, there is a problem of the C GD becomig too small, causig the gate cotrollability to decrease ad the tur-off d V /d t to icrease. Additioally, if the gate resistace R g is icreased i order to reduce the tur-off d V /d t, the Miller period* 1 will legthe ad the will icrease. As a result, the tradeoff relatioship betwee E off ad tur-off d V /d t deteriorates. Accordigly, if the tradeoff relatioship betwee E off ad tur-off d V /d t ca be improved, ad the tur-off decreased, a low power device that realizes both low coductio ad low switchig ca be realized. I fact, the is a realizatio of such a device. 3. Optimizatio of Surface Structures 3.1 Desig cocept I order to improve the tradeoff relatioship betwee E off ad tur-off d V /d t i a SJ-MOSFET, it is ecessary to reduce tur-off d V /d t uder coditios of costat R g. Focusig o the reductio of tur-off d V /d t, characteristics of the tradeoff betwee E off ad tur-off d V /d t were improved i accordace with the followig equatio. Assumig that the gate-source capacitace durig tur-off is costat withi the Miller period, tur-off d V /d t ca be expressed as i Eq.(1). dv dt ID + Vth gfs = C $ V $ R GD DS g I D : Drai curret g fs : Trascoductace V DS : Drai-to-source voltage (1) From Eq.(1), it ca be uderstood that whe R g, I D ad V DS are costat, icreasig C GD ad decreasig the threshold voltage V th are effective for reducig tur-off d V /d t. C GD is determied by the distace betwee the p-bases, i.e., the gate legth L g, ad therefore L g should be legtheed i order to icrease C GD. Moreover, because V th is determied accordig to the impurity cocetratio of the p-base regio, V th ca be decreased by reducig the impurity cocetratio of the p-bases. 3.2 Gate legth depedece of tur-off Simulatios based o the desig cocept were performed to estimate the L g depedece of E off. Figure 2 shows the L g depedece of E off ad tur-off d V /d t. E off values are show for the case that tur-off d V /d t is kv/ μ s, ad tur-off d V /d t values are show for the case that R g is 91 Ω. Additioally, the values of L g are relative to the value of L g prior to optimizatio of the structure. As show i Fig. 2, tur-off d V /d t ca be reduced by legtheig L g, ad the resultig decrease i the value of E off was cofirmed. Whe L g icreases above 1.4, the E off value shows early o improvemet ad remais early uchaged. This is thought to be caused by the legtheig of the Miller period ad icreased that occurs whe C GD is icreased, causig the tur-off time to become loger ad the feedback capacitace to icrease. 3.3 Threshold voltage depedece of tur-off Next, the V th depedece of E off ad tur-off d V /d t was calculated. The results are show i Fig. 3. As i the calculatio of the L g depedece, the values of V th are relative to the value of V th prior to optimizatio of the structure. Additioally, a estimatio of the V th depedece was calculated based o the simulatio described i Sectio 3.2 ad usig a optimal L g desig value of 1.4. As show i Fig. 3, tur-off d V /d t decreases as V th becomes smaller, ad accordigly, a decrease i the value of E off was cofirmed. If V th becomes too small, however, a problem may occur i which the device turs-o uitetioally due to oise. I optimizig the desig for V th, it is ecessary to be careful so as ot to reduce V th too much i order to prevet malfuctio of the device. Based o the above results ad usig L g =1.4 ad V th =.75 as optimal structure values, the tradeoff rela- 1, 1, Tur-off Eoff (μj) Tur-off dv/dt= kv/μs R g=91 Tur-off dv/dt (kv/μs) Tur-off Eoff (μj) Tur-off dv/dt= kv/μs R g=91 Tur-off dv/dt (kv/μs) Gate legth L g (a.u.) Threshold voltage V th (a.u.) Fig.2 L g depedece of E off ad tur-off dv/dt Fig.3 V th depedece of E off ad tur-off dv/dt 8 Vol. 58 No. 2 FUJI ELECTRIC REVIEW

3 Tur-off dv/dt= kv/μs Specific o-resistace Ro A (a.u.) Competitor A s Fig.4 Compariso ad evaluatio of R o A tioship betwee E off ad tur-off d V /d t was improved. 4. Performace 4.1 Evaluatio of o-resistace For SJ-MOSFETs rated at 6 V/2 A/.19 Ω, the specific o-resistaces R o A at rated voltages of the ad competitors s were compared ad evaluated. Figure 4 shows the evaluatio results. The values of R o A are relative to the value of the. With the, R o A values equal to or better tha those of competitors SJ- MOSFETs were cofirmed. 4.2 Evaluatio of switchig Next, E off was evaluated. With the, the E off value is 16 μ J whe tur-off d V /d t is kv/ μ s, ad this extremely small E off was realized through structural optimizatio. E off values whe tur-off d V /d t is kv/ μ s were compared ad evaluated for the ad competitors s, ad the results are show i Fig. 5. As i the case of Fig. 4, E off values are relative to the value of the Super J-MOS. As show i Fig. 5, the is affected by the structural optimizatio ad the results showed a E off value sigificatly lower tha those of competitors s. 5. Ivestigatio i Electrical Equipmet Competitor B s As described above, by optimizig the surface structures, the was cofirmed to exhibit excellet levels of R o A ad E off. Next, to verify the power efficiecy whe usig a, a Super J-MOS was istalled i the power factor correctio (PFC) circuit of a 4 W-ATX power supply as show i Fig. 6, ad the power efficiecy was evaluated. The same evaluatio was also performed for compay A s SJ-MOSFET, which exhibited lowest tur-off Tur-off Eoff (a.u.) Fig.5 Compariso ad evaluatio of E off PFC circuit Fig.6 Cofiguratio of PFC circuit Competitor A s Forward coverter Competitor B s amog the competitors s. The values of power supply ad power supply efficiecy that were obtaied were compared ad evaluated (see Fig. 7). All the devices that were evaluated were rated at 6 V/.19 Ω. As show i Fig. 7(a), i compariso to compay A s, the exhibits lower especially durig tur-off, ad this cotributes greatly to a reductio i total power supply. Moreover, as show i Fig. 7(b), highly efficiet power supply operatio is realized with the Super J-MOS, ad whe the power supply has a 5% load factor, the power efficiecy is at the high level of 96%. Furthermore, i the load factor rage from 2% to %, the power efficiecy was at least 94% or higher. This result coforms to the 8 PLUS (6) * 2 stadard, ad idicates that the possess characteristics that ca cotribute to improvemet of the power *2: 8 PLUS : A stadard promotig higher efficiecy i power supplies ad is defied by a idepedet private orgaizatio ( I the power supplies used i PC ad servers, 8 PLUS certificatio idicates that the power coversio efficiecy is 8% or greater at load factors of 2%, 5% ad %. 8 PLUS is a trademark or registered trademark of USbased Ecos Cosultig Ic. issue: Power Semicoductor cotributig i eergy ad eviromet regio Low Power Loss Superjuctio MOSFETs 81

4 Power (a.u.) Power efficiecy (%) Fig.7 Results of ivestigatio i electric equipmet efficiecy of a power coverter. 6. Postscript Iput voltage: AC115 V Output voltage: 39 V Tur-off Tur-o Coductio Competitor A s (a) Compariso of power i power supply (at output power of 4 W) Competitor A s Load factor (%) (b) Compariso of power efficiecy By optimizig the surface structures of the SJ- MOSFET, the, which features a improved tradeoff relatioship betwee tur-off ad tur-off d V /d t ad low switchig, was developed. Icreasig the gate-to-drai capacitace ad lowerig the threshold voltage was cofirmed to result i a lower tur-off d V /d t ad a improved tradeoff relatioship betwee tur-off ad tur-off d V /d t. By optimizig the surface structures of the device, the tur-off was foud to be 16 μ J whe tur-off d V /d t is kv/ μ s, ad this is a excellet level for a SJ-MOSFET. Additioally, as a result of istallig a i the PFC circuit of a 4 W-ATX power supply ad the coductig a evaluatio, power supply operatio exhibitig much higher efficiecy tha that of competitors SJ-MOSFETs was foud to be possible. Targetig applicatios i the commuicatio ad PC server power supply market, Fuji Electric is curretly movig forward with efforts to reduce ad icrease the efficiecy of the 6 V-rated Super J-MOS. Fuji Electric iteds to cotiue to improve device performace i the future through device miiaturizatio ad the like. Refereces (1) Fujihira, T. Theory of Semicoductor Superjuctio Devices, Jp. J. Appl. Phys., 1997, vol.36, p (2) Deboy, G. et al. A New Geeratio of High Voltage MOSFETs Breaks the Limit Lie of Silico, Proc. IEDM, 1998, p (3) Oishi, Y. et al. 24 mωcm 2 68 V Silico Superjuctio MOSFET, Proc. ISPSD 2, 22, p (4) Saito, W. et al. A 15.5 mωcm 2-68 V Superjuctio MOSFET Reduced O-Resistace by Lateral Pitch Narrowig, Proc. ISPSD 6, 26, p (5) Baliga, B. J. Moder Power Devices, Joh Wiley & Sos, Ic., 1987, p (6) ECOS Cosultig. (Refer to Jul. 29, 211) 82 Vol. 58 No. 2 FUJI ELECTRIC REVIEW

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