SW simulation and Performance Analysis

Transcription

1 SW simulation and Performance Analysis In Multi-Processing Embedded Systems Eugenio Villar University of Cantabria

2 Context HW/SW Embedded Systems Design Flow HW/SW Simulation Performance Analysis Design Verification At the different abstraction levels Requirements Functional design Executable Specification Co- Design UML/MARTE MDA SystemC Embedded SW Compilation C VHDL Verilog IP Reuse HW Platform Behavioral Synthesis RTL Synthesis HW/SW Implementation SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 2

3 Agenda Motivation: Why SW simulation Technologies: How SW simulation SCoPE: SW simulation for DSE SW performance analysis Improvements for Scalopes Conclusions SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 3

4 Motivation

5 Motivation The MPSoC Multi-processing platform ASIC FPGA Commercial multi-processing platform SW-centric design methodology Most of the functionality implemented as Embedded SW With some application-specific HW SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 5

6 Motivation Software Reliability WASHINGTON (COMPUTERWORLD) - Software bugs are costing the U.S. economy an estimated $59.5 billion each year, with more than half of the cost borne by end users and the remainder by developers and vendors, according to In Embedded SW both a new federal study. Functionality and Performance are Improvements in testing could reduce relevant this cost by about a third, or $22.5 billion, but it won't eliminate all software errors, the study said. Of the total $59.5 billion cost, users incurred 64% of the cost and developers 36% SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 6

7 Motivation Embedded SW simulation As an integral part of the MPSoC simulation Essential for MPSoC verification At any abstraction level Essential for DSE During architectural design Essential for performance analysis At any abstraction level SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 7

8 SW simulation In Multi-Processing Embedded Systems Eugenio Villar University of Cantabria

9 Embedded SW simulation technologies Embedded SW simulation Requirements Functional Simulation Functional design UML/MARTE MDA Native code simulation Fast Computation&Communication estimations Native co-simulation Accurate Computation&Communication estimations Virtual Functional Models ISS Discrete-Time Models HDL Discrete-Event Models Embedded SW Compilation Executable Specification Co- Design SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 9 C VHDL Verilog IP Reuse HW/SW Implementation SystemC HW Platform Behavioral Synthesis RTL Synthesis

10 Embedded SW simulation technologies HDL simulation Embedded System Architecture Node i Application Code HDL Model Task 1... Task n VHDL Verilog Other Nodes Node i CPU1 model CPUp model Cache models Cache models Bus model DMA NoC if. ASHW memory Compilation OS OS CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 10

11 Embedded SW simulation technologies HDL simulation Very detailed model High modeling cost Late design steps Highest accuracy Discrete delays Highest simulation times SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 11

12 Embedded SW simulation technologies ISS simulation Embedded System Architecture Node i ISS Model Application Code Task 1... Task n ISSs Node i CPU1 CPUp Instruction Instruction Set Set model model Cache models Cache models Bus (TLM/RTL) model DMA NoC if. ASHW memory Compilation OS OS CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 12

13 Embedded SW simulation technologies ISS simulation Detailed model High modeling cost Late design steps Cycle accuracy High simulation times SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 13

14 Embedded SW simulation technologies Virtualization Embedded System Architecture Node i Virtual Model Application Code Task 1... Task n Node i Binary Binary OS OS CPU1 virtual model CPUp virtual model TLM Bus model DMA NoC if. ASHW memory Compilation CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 14

15 Embedded SW simulation technologies Virtualization (QEMU) Detailed model High modeling cost Late design steps High simulation times Faster than ISS PowerPC (200 MHz) # r1 = r1-16 addi r1,r1,-16 Intel Core i5 (2.40 GHz) # movl_t0_r1 # ebx = env->regs[1] mov 0x4(%ebp),%ebx # addl_t0_im -16 # ebx = ebx - 16 add $0xfffffff0,%ebx # movl_r1_t0 # env->regs[1] = ebx mov %ebx,0x4(%ebp) SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 15

16 Embedded SW simulation technologies Virtualization (QEMU) Functional emulation Rough timed simulation i.e. 1 cycle per instruction Large effort needed for more accurate modeling Execution times Power consumption Caches Requires a specific Virtual Model for each processor SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 16

17 Embedded SW simulation technologies Native simulation Embedded code directly executed by the host Good accuracy by back-annotation Fast execution time SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 17

18 Embedded SW simulation technologies Native simulation based on HAL API Virtual Model Embedded System Architecture Node i Application Code Annotation Node i Application Code Task 1... Task n Task 1... Task n OS OS OS OS Other Nodes HAL CPU1 model DMA HAL CPUp model TLM Bus model NoC if. ASHW memory Parsing CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 18

19 Embedded SW simulation technologies Native simulation based on Virtual Model Embedded System Architecture Node i Application Code Annotation Node i Application Code Task 1... Task n Task 1... Task n Other Nodes DMA OS & CPU OS & CPU TLM Bus model NoC if. ASHW memory Parsing OS OS CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 19

20 Embedded SW simulation technologies Code annotation in native simulation Overflow = 0; s = 1L; for (i = 0; i < L_subfr; i++) { Carry = 0; s = L_macNs(s, xn[i], y1[i]); if (Overflow!= 0) { break; }} if (Overflow == 0) { exp_xy = norm_l(s); if (exp_xy<=0) xy = round(l_shr (s, -exp_xy)); else xy = round(l_shl (s, exp_xy)); } mq_send(queue1, &xy, p, t); Global variable int Sim_Time = 0; Sim_Time += 20; Sim_Time += 25; Sim_Time += 15; Sim_Time += 10; Sim_Time += 10; Sim_Time += 10; wait included SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 20

21 Embedded SW simulation technologies Functional simulation based on code Virtual Model Node i Embedded System Architecture Node i Application Code Task 1... Task n Task 1... Task n Modeling API Modeling API Other Nodes OS & DMA OS & TLM Bus model NoC if. ASHW memory OS OS CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 21

22 Embedded SW simulation technologies Functional simulation based on abstract tasks Virtual Model Embedded System Architecture Node i Node i Task 1 WCET period... Task n WCET period Task 1 WCET period Application Code... Task n WCET period Modeling API Modeling API Other Nodes OS & DMA OS & TLM Bus model NoC if. ASHW memory OS OS CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 22

23 Embedded SW simulation technologies Power estimation based on traces Accurate but slow ISS Model ISSs Node i Binary Binary CPU1 model CPUp model Cache models Cache models Bus (TLM/RTL) model DMA NoC if. ASHW memory Activity Power (& Thermal) Estimation Thermal & Power metrics NoC model SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 23

24 Embedded SW simulation technologies Power estimation based on back-annotation Virtual Model Node i Same technology as with execution times Other Nodes Task 1 DMA Application Code OS & CPU TLM Bus model NoC if. ASHW memory NoC model... Task n OS & CPU Power metrics Global variable int Sim_Energy = 0; Best ratio accuracy/speed SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 24

25 Embedded SW simulation technologies Cache modeling Node i Application Code Task 1... Task n Other Nodes OS & CPU DMA OS & CPU TLM Bus model NoC if. ASHW memory Misses Cache model Time & Power metrics NoC model SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 25

26 Embedded SW simulation technologies Performance/Error comparison Functional Native Virtualization ISS (cycle-accurate) HDL Technology Time Estimation Time & Power Estimation Performance 5,000 N.A. Error N.A. N.A. Performance 1, Error Performance 200 T.B.M. Error 1.5 T.B.M. Performance 10 1 Error 1.1 (DT) 1.1 Performance Error 1 (DE) 1 Rough approximate figures SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 26

27 SCoPE: SW Performance Modeling

28 SCoPE: SW Performance Estimation Key features OS modeling Instruction cache modeling Novel features Physical memory accesses Separate memory spaces Design-space exploration SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 28

29 SCoPE: SW Performance Estimation OS modeling POSIX threads modeled as SC_THREADs Scheduler model Time modeling RTOS services (POSIX & μcs) interrupt T1 Priority = 1 T1 40 μs 30 μs T2 Priority = 2 T2 25 μs 50 μs 45 μs 45 μs 25 μs Tick-Timer Period = 30 μs SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 29

30 SCoPE: SW Performance Modeling Instruction cache modeling Similar to time modeling Overflow = 0; s = 1L; for (i = 0; i < L_subfr; i++) { Carry = 0; s = L_macNs(s, xn[i], y1[i]); if (Overflow!= 0) { break; }} if (Overflow == 0) { exp_xy = norm_l(s); if (exp_xy<=0) xy = round(l_shr (s, -exp_xy)); else xy = round(l_shl (s, exp_xy)); } struct icache_line { char num_set; char hit; } static icache_line line_124 = {0,0}; static icache_line line_125 = {0,0}; static icache_line line_126 = {0,0}; If (line_124.hit == 0) insert_line(&line_124); If (line_125.hit == 0) insert_line(&line_125); If (line_126.hit == 0) insert_line(&line_126); SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 30

31 SCoPE: SW Performance Modeling Physical memory accesses Memory (re)map for passive accesses pa=mmap(addr, len, prot, flags, fildes, off); Access to peripherals Application SW *addr=value; Native Simulation Exception handler Peripheral SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 31

32 SCoPE: SW Performance Modeling Separate memory spaces Use of dynamic libraries Task T int global = 0; void func() { { int main() { } Peripheral P int regs[4]; void read_reg() { { int write_reg() { } Node 1 Application Code Node n Application Code Task 1... Task n Task 1... Task n OS & CPU OS & CPU TLM Bus model DMA NoC if. ASHW memory OS & CPU OS & CPU TLM Bus model DMA NoC if. ASHW memory NoC model SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 32

33 SCoPE: SW Performance Modeling Design-Space Exploration Configurable model Node Node i Node i i Application Code Application Code Application Code Task Task Task 1 Task 1... Task n Task n n model model of OS OS & of OS CPU & CPU CPU model model of OS OS & of OS CPU & CPU CPU TLM TLM Bus TLM Bus model Bus model Other model Other Nodes Other Nodes DMA Nodes DMA NoC DMA NoC if. NoC if. ASHW if. ASHW memory ASHW memory memory Design parameters Metrics Design-Space Exploration Tool Pareto points NoC NoC model NoC model model SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 33

34 SCoPE: Improvements for Scalopes

35 SCoPE: Improvements for Scalopes Dynamic Voltage-Frequency Scaling Node i Application Code Annotation T 0 (F 0,V 0 ) E 0 (F 0,V 0 ) Node i Application Code Task 1... Task n Task 1... Task n Other Nodes DMA F,V OS & CPU F,V OS & CPU TLM Bus model NoC if. ASHW memory Parsing F T = T. 0 0 F E = E 0 P = E/T V. V OS OS CPU1 caches CPUp caches Bus memory NoC if. ASHW DMA Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 35

36 SCoPE: Improvements for Scalopes Thermal modeling Node i Application Code Task 1... Task n Other Nodes DMA OS & CPU OS & CPU TLM Bus model NoC if. ASHW memory Power metrics Thermal Model (PoTest) Thermal metrics NoC model SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 36

37 SCoPE: Improvements for Scalopes System composition from IP-XACT components Other Nodes Task 1 DMA OS & CPU Node i Application Code... Task n OS & CPU TLM Bus model NoC if. ASHW memory Model Generator CPU1 caches Node i Bus memory NoC if. ASHW CPUp caches DMA Application SW IP-XACT Library Other Nodes NoC model NoC SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 37

38 SCoPE: Improvements for Scalopes WIN32 API Node i Other Nodes DMA Windows Application Code Task 1 OS & CPU... Task n OS & CPU TLM Bus model NoC if. ASHW memory Plug-in kernel32 Plug-in translation Windows DLL Plug-in POSIX Wine native DLLs Kernel32 DLL NTDLL Wine server Wine executable DLLs & shared libraries NoC model SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 38

39 SCoPE: Improvements for Scalopes Data cache model L2 model In both cases, physical addresses model needed SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 39

40 SCoPE: Improvements for Scalopes SCoPE as a system component Execution Platform Task 1 OS & CPU Application Code... Task n OS & CPU type and number of processors SCoPE Component Generator cache architecture Application SW SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 40

41 SCoPE: Improvements for Scalopes SCoPE as a system component Execution Platform Application Code Task 1... Task n OS & CPU OS & CPU Bus memory HW component Peripheral SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 41

42 SCoPE: Improvements for Scalopes Spear modeling Power-Line Communication (PLC) modeling SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 42

43 Conclusions

44 Conclusions SW simulation Essential Design Technology HW/SW Embedded Systems At different design steps Different modeling and simulation technologies Various performance*accuracy products SCoPE SystemC Native Co-Simulation Technology Specially tuned to performance analysis Design-Space Exploration SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 44

45 Thank you for your attention Slides available at: SCoPE available at: SW Simulation and Performance Analysis In Multi-Processing Embedded Systems - 45

46 Thank you for your attention We value your opinion and questions