High Performance Cognitive Radio Platform with Integrated Physical & Network Layer Capabilities

Transcription

1 High Performance Cognitive Radio Platform with Integrated Physical & Network Layer Capabilities Bryan Ackland, Ivan Seskar WINLAB, Rutgers University 1

2 Dynamic Spectrum Allocation Large, increasing demand for wireless services Static frequency bands allocated to single service Inefficient use of spectrum Slow, expensive political process Locally optimized incompatible solutions FCC exploring alternatives ISM & U-NII bands Power and BW limitations to allow co-existence Successful but quickly getting congested Intelligent or Cognitive radios that adapt to local wireless environment Improve spectrum efficiency and fairness 2

3 Cognitive Radio Programmable radio systems that adapt to: Changing radio interference Availability of nearby collaborative nodes Changing protocols & standards Application requirements by modifying Frequency, power, bandwidth Modulation, coding, MAC Network protocols and coordinating with other cognitive systems to maximize spectral efficiency and fairness 3

4 Cognitive Radio Implementation Tradeoff between flexibility, performance & power flexibility speed, power, cost 1 10 Silicon area efficiency Microprocessor DSP FPGA ASIC Moore s Law improvements in CMOS VLSI Implement some functions in SW Ultimate goal: software radio?? A/D µp Reality: some combination of HW, SW and reconfigurable logic 4

5 Programmable Wireless Networks Research Goals: Investigate Cognitive Radio Strategies & Spectrum Sharing Algorithms Explore flexible, power efficient wireless architectures Develop board level platform for system prototyping & subsequent distribution to research community 5

6 Project Team WINLAB, Rutgers University Bryan Ackland Ivan Seskar D. Raychaudhuri Chris Rose GEDC, Georgia Institute of Technology Joy Laskar Stephane Pinel Wireless Res. Lab., Lucent Bell Laboratories Tod Sizer Dragan Samardzija 6

7 Platform Goals Design & build cognitive radio platform that is High performance HW & SW Programmable Physical, baseband & network layer adaptable Support wide range of spectrum sharing scenarios Leverage today s high performance off-the-shelf components to build experimental platform with maximum utility & flexibility Demonstrate architectures and components that will enable low cost, low power, flexible integrated circuit implementations in near future. 7

8 Spectrum Management: Problem Scope Spectrum Coordination Server (dynamic) BTS Etiquette policy Short-range ad-hoc net INTERNET Dynamic frequency provisioning Spectrum Allocation Rules (static) Auction Server (dynamic) Spectrum Coordination protocols Spectrum Coordination protocols Wide-area infrastructure mode network (e.g ) AP Short-range infrastructure mode network (e.g. WLAN) Ad-hoc sensor cluster (low-power, high density) Dense deployment of wireless devices, both widearea and short-range Proliferation of multiple radio technologies, e.g a,b,g, UWB, , 4G, etc. How should spectrum allocation rules evolve to achieve high efficiency? Available options include: Agile radios (interference avoidance) Dynamic centralized allocation methods Distributed spectrum coordination (etiquette) Collaborative ad-hoc networks 8

9 Cognitive Radio: Design Space Protocol Complexity (degree of coordination) Unlicensed band + simple coord protocols Internet Internet Server-based Server-based Spectrum Spectrum Etiquette Etiquette Unlicensed Unlicensed Band Band with DCA with DCA (e.g x) (e.g x) Ad-hoc, Ad-hoc, Multi-hop Multi-hop Collaboration Collaboration Radio-level Radio-level Spectrum Spectrum Etiquette Etiquette Protocol Protocol Cognitive Radio schemes Internet Internet Spectrum Spectrum Leasing Leasing Static Static Assignment Assignment Reactive Reactive Rate/Power Rate/Power Control Control UWB, UWB, Spread Spread Spectrum Spectrum Agile Agile Wideband Wideband Radios Radios Open Access + smart radios Hardware Complexity 9

10 Cognitive Radio: Capabilities Spectrum scanning & frequency agility Fast physical layer adaptation & power control to respond to changing local conditions Flexible baseband & MAC switchable on a packet-by-packet basis (SDR) to provide interoperability with multiple radio technologies Capable of higher layer spectrum etiquette or negotiation protocols Simultaneous heterogeneous radio links Protocol translation & routing to support heterogeneous and/or ad-hoc networks 10

11 Cognitive Radio Platform Flexible Antenna Flexible RF Flexible RF Flexible RF Flexible Baseband (SDR) Network Processor (MAC+) CR Strategy (host) local drop Separate sub-systems to simplify functional implementation & modification by students in experimental environment 11

12 Platform Partitioning Flexible Antenna Flexible RF Flexible RF Flexible RF A/D/A A/D/A A/D/A Flexible Baseband (SDR) Network Processor (MAC+) CR Strategy (host) Antenna & RF Board (Georgia Tech.) A/D/A Board (Rutgers) Baseband & Network Processor Board (Rutgers & Lucent) 12

13 Agile Tri-band RF Front-end Tri-band operation: MHz GHz ISM band GHz ISM and UN-II bands 2 Transmit + 2 Receive channels for data + spectrum monitoring receiver 20 MHz bandwidth on each channel tunable over band Narrow band selection performed at baseband 100mW transmit power (variable) per channel Sensitivity & linearity to meet a 13

14 Tri-band Agile Receiver ~ 800 MHz 2.4 GHz 5.2 GHz Channel 1 To baseband A/D s I Q 20 MHz BW IF filter ~ Low-IF ~150 MHz I Q tri-band RX ~ 800 MHz 2.4 GHz 5.2 GHz SW M A T R I x AgileTriband LNA + Agile High Q matching network tri-band antenna Channel 2 I Q 20 MHz BW IF filter I Q tri-band RX SOC SOP Power detection Standard identification 20 MHz BW IF filter ~ I Q tri-band RX tri-band VGA tri-band antenna Tri-band Sensing /Monitoring Unit 14

15 Reconfigurable RFIC s for Compact Intelligent RF Front-end Switched-L Frequency Agile VCO Oscillation Frequency (in GHz) Band-I Band-II Vtune (in V) 15

16 Tri-band Antennas Triple-Broadband Antenna for handheld terminals - planar antenna structure -multi-band 5 - broadband 4 VSWR Frequency (GHz) PCB Frequency Range (MHz): VSWR: 1.5 Pattern (azimuth plane) : Omni-directional Non-omni Peak Gain (azimuth plane) : 0 dbi 3 dbi Polarization: Mixed Antenna dimensions: 50 mm 50 mm 0.2 mm 16

17 GaTech System-on-Package RF-MEMS Switch Reconfigurable CMOS RFIC RF Tx / Rx Flexible baseband Multiband/wideband antenna. FR-4 Organic high density multi-layer RF-MEMS Switch & Multi-band Antenna VSWR Frequency (GHz) Reconfigurable CMOS RFIC L(active) G N D C 3 C 1 C 2 G N D V b R R 1 V D D GN D Q 1 L 1 V D D Q 2 R 2 G N D Vg ain R C 4 V D D G N D R 3 Q 3 C 5 O u t 17

18 Baseband & Network Processor Interface to multiple radio channels Real time spectral analysis Support comparison of HW & SW baseband solution MAC, protocol conversion, SAR, routing Data rates (total) up to 100 Mb/s Support novel reconfigurable architectures in baseband and network layers Clean partitions between Baseband, NP and CR Simple programming environment (not DSP) Fast reconfiguration time (~µs) 18

19 Bell Labs Programmable Radio Platform Megarray Connector- 244 Configurable I/O pins XC2V6000 FPGA TMS320C6701 Ethernet MPC8260 6M gates programmable logic 2.5 Megabits DPRAM in FPGA 144 dedicated multipliers 1 GFLOPS TMS320C MIPS MPC configurable I/O pins 19

20 WINLAB Baseband Platform GV300 2 Virtex -II FPGAs (XC2V3000) each with 256K x 18 ZBT SRAMs 1 Spartan -II FPGA for External Interface 1 Spartan -II FPGA for Configuration Control USB interface Four 100 MHz 12-bit A/D and four 100 MHz 12-bit D/A channels On-board 100 MHz programmable clock oscillator 32 Bit LVDS interface 2M x 8 configuration FLASH 20

21 Baseband & Network Processor Data, control & sensing to/from RF front-end Baseband FPGA Virtex-4 94K logic cells 160 DSP slices PowerPC (RTOS) Network FPGA Virtex-4 94K logic cells Soft RISC cores 64 SDRAM (128MB) EEPROM (config) SRAM (4MB) PowerPC PowerQuick III 600 MHz (LINUX) DRAM (64MB) Gig-E USB-II 21

22 Network Processor based on Multiple RISC Cores to/from baseband to/from CR host Packet Scheduler (RISC) Packet Buffer (DRAM) Header Buffer Packet Processor (RISC/reconfig) Packet Processor (RISC/reconfig) Local I&D Local I&D Packet Processor (RISC/reconfig) Local I&D External DRAM 22

23 SW Development Environment Need efficient multi-user, multi-proc. compile & debug Short learning curve for student SW developers Linux OS with Gnu tool chain Open source Modular: I/O drivers can be installed without kernel modification or reboot User friendly development environment Simulink models compiled to VHDL and/or C 23

24 Milestones & Timeline RF Front-end Baseband & Network Proc. System Y1 Q1 Y1 Q2 Detailed performance & interface specs (12/04) Result of HW (FPGA) and SW implementation studies Y1 Q3 Detailed Architecture Specification Y1 Q4 Initial prototype off the shelf components limited flexibility 1. Component selection & schematics. 2. Software Specification Proof of concept system prototype based on: 1. Existing WINLAB board 2. Gatech prototype Y2 Q1 Y2 Q2 Agile prototype mainly off the shelf some custom components full functionality Y2 Q3 Prototype Software Dev. Env. Y2 Q4 Prototype boards available System Prototype based on: 1. Lucent BB&NP 2. Gatech Agile Radio Y3 Q1 Y3 Q2 1. Board spin 2. Baseline SW release Y3 Q3 Y3 Q4 Integrated SIP/SOC agile tri-band radio 2-3 Cognitive Radio Scenario Demos* *Note: Further release of Cognitive Radio Boards to community contingent on separate funding 24