Hardware Architecture of Software Defined Radio (SDR)

Transcription

1 Hardware Architecture of Software Defined Radio (SDR) Tassadaq Hussain Assistant Professor: Riphah International University Research Collaborations: Microsoft Barcelona Supercomputing Center University of Valenciennes, France (CNRS UMR) UCERD Pvt Ltd Pakistan

2 Digital System

3 What is Software Defined Radio (SDR) SDR is a general term referring to any radio design that uses a computer and some controlling software to define that radio s operation. A true SDR has very little hardware and virtually every aspect of its operation is performed by the controlling software.

4 Software Defined Radio (SDR) Performs the majority of signal processing in the digital domain using programmable multicore RISC, GPU, DSPs and hardware accelerator support. Some signal processing is still done in the analog domain, such as in the RF and IF circuits.

5 Ideal SDR

6 The history of SDR SPEAKeasy phase I A government program with the following goals: to develop a radio that could function anywhere between 2 Mhz and 2 Ghz: To able to communicate with the radios used by ground forces as well as air force and naval radios in addition to satellites To develop a new signal format within 2 weeks with no prior preparation To use parts and software from multiple contractors at once

7 SDR: Programming The ultimate device, where the antenna is connected directly to an A-D/D-A converter and all signal processing is done digitally using fully programmable high speed processor/s. All functions, modes, applications, etc. can be reconfigured/programmed by the software.

8 WHY an SDR? The biggest reason to have an SDR is the flexibility it offers the user. Filtering can easily be changed, depending on the needs Modes of operation can be changed to accommodate new communications technologies All of these functions are controlled in Software, rather than Hardware, making changes simpler (no new filters/hardware demodulators required- the code takes care of it)

9 Benefits of SDR Best utilizes the frequency band spectrum Flexible Reduced Obsolescence Enhances Experimentation Brings Analog and Digital World Together Improve Intelligence Quicker time to market

10 New Breed of Radio Re-programmable / Reconfigurable Multi-core CPU/GPU/DSP and FPGA Accelerators Multiband/Multimode Networkable Simultaneous voice, data, and video Full convergence of digital networks and radio science.

11 Block Diagram Software Defined Radio Antenna RF IF Bandpass Filter Variable Local Frequency Oscillator Oscillator Baseband ADC/DAC Multi-core System

12 Block Diagram Software Defined Radio Antenna RF Local Oscillator (fixed) IF Baseband ADC/DAC Multi-core System

13 Block Diagram Software Radio Antenna RF ADC/DAC IF Baseband Multi-core System

14 Designing an SDR Antenna RF ADC/DAC Multi-core Processor

15 High Performance SDR

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19 MHz Receive RF Amp Synthesizer to MHz 5 khz Steps 10 MHz Ext. Ref. (Optional) Synthesizer MHz U1,U2 R ANT or XVRTR TR SW (D2) J211 J212 T 2-Pole LC Filter 150 MHz 32 db Transmit RF Amp MHz R T 4-Pole LC Filter U4,U5 First Mixer R Receiver Second IF khz TR SW (U11A,U11C) (U15) T U109B, Q5,Q khz Audio Power Amp Audio Filters o 90 TR SW (U11B) DAC R ADC o 90 SSB and CW Detector +/- AGC R LMS Denoise Sinewave BFO khz J102 FFT Spectrum Analyzer PTT CW Key Low-Pass Filter IF Driver 50 db Microphone Second Mixer 40 db Q1, U10A T 4-Pole Crystal Filter (U3) IF Amp TR SW (U12A,U12B) 28 khz TR SW (D1) J213 Low-Pass Filter MHz J103 Arc Tangent FM Detector Analog Devices EZ-Kit Lite SW FM Squelch 1024 Points J201 Serial Data to PC U14 J204 Speaker

20 Conclusions Integrates heterogeneous multi-processor cores having RISC, DSP and FPGA architecture that utilize communication system resources efficiently under varying conditions. Take advantage of unutilized spectrum. If one application is not using its spectrum, the hardware can borrow the spectrum until the application starts using it again. Uses wide-band RF transceiver and multi input multi output (MIMO) antennas that adapts to use in a different environment and for multiple applications. A high performance front-end interface having high speed ADC and DAC which manages high data rate signals. Provides C/C++ based programming toolkit to program multi-cores or reprogram hardware accelerators to support the latest communications standards without affecting SDR structure. Help to perform future research and development by providing an implementation of many different waveforms for real-time performance analysis.

21 Looking Ahead Smart Radios that configure themselves to perform the communications task requested (using different frequency bands, modes, etc.) Cognitive Radios that learn about their environment (e.g., other users nearby, interference, location, elevation) to optimally configure themselves to maximize efficiency and reduce interference.

22 Technical Challenges Reconfigurable RF Hardware ADC/DAC Speed Sensor Wall AI Algorithms