MSL RAD Front-End-Electronics RADE PCB layout

Transcription

1 MSL RAD Front-End-Electronics RADE PCB layout Stephan I. Böttcher v04: December 12, 2006 The RADE board supports the readout of the neutron channel scintillator of the RAD instrument. The board will be mounted below the neutron channel, with the backside facing the scintillator. The board shape is circular with a diameter of 46 mm, with six cutouts to accommodate the inner preload spring assembly. The board shall be staked to the upper spring plate, with a thin insulating layer of polyimide glass between the board and the plate. Three neutron channel detectors will be connected with small flex strips, which are glued and wire-bonded to the detector. The other end of the strips will be staked to the RADE board and connected with short solder wires. The power supply of the RADE electronics is routed via Teflon insulated wires (17-strand, AWG 32) from the RADF board through the anticoincidence scintillator to solder pads on the perimeter of the RADE board. A further set of solder pads supports the power supply wires to the RADD boards. The electronics on the RADE board include three Charge Sensitive Amplifiers (CSA) and three Fast Shapers (FSH). 1

2 1 Fabrication The board shall be made according to IPC 6012 class 3 standards. 1.1 Material The base material is polyimide glass, Total board thickness 1 mm ± 10 %, with 35 µm copper thickness, surface finish HAL PbSn, with solder mask on the front side only, no silk screens. 1.2 Design Rules The minimum trace width is 0.2 mm (8 mil), clearance 0.2 mm (8 mil), the clearance on top surfaces to copper carrying 70 V shall be 0.3 mm (12 mil). The minimum via hole diameter is 0.4 mm (16 mil), with annular rings of at least 0.25 mm (10 mil) width. The edge clearance of copper traces and pads is 0.5 mm (20 mil) minimum. 1.3 Layers The board has four copper layers, with SMD components on one side. The backside is filled with a ground plane. The inner layers are a ground plane and a power routing layer. The layer order is front, ground, power, back. The ground plane has cutouts under the inverting input nodes of the current feedback amplifiers (AD 8005). Layer order Gerber file 1 front layer copper v04.group0.gbr 2 ground layer copper v04.group3.gbr 3 power layer copper v04.group4.gbr 4 back layer copper v04.group1.gbr board shape front solder mask drill file back solder mask front solder paste back solder paste front silk screen back silk screen fab, please ignore v04.group2.gbr v04.frontmask.gbr v04.plated-drill.cnc (v04.backmask.gbr) (v04.frontpaste.gbr) (v04.backpaste.gbr) (v04.frontsilk.gbr) (v04.backsilk.gbr) (v04.fab.gbr) 2

3 The files in parenthesis are PCB tool output not relevant to this board s fabrication. 2 Design 2.1 Tools The design is done with GNU EDA tools. ( The layout tool is PCB version GAF version is Schematics The schematics for the CSA and FSH were derived from master schematics (Fig. 2 and 3) by a script which prefixes net names and reference designators with an instance prefix, L1, L2, and L3 for the CSAs, and S1, S2, and S3 for the shapers. The RADE schematics (Fig. 1) defines connections between the amplifier instances, and to the solder pads. 2.3 Layout Fig. 4 to 7 show the copper layer layouts, Fig. 8 shows the silk layer (not to be printed on the board). Each layer is shown at scale 1:1 and expanded to text width. 3

4 $Id: RADE.sch,v /11/07 12:20:04 bottcher Exp $ R4 L1_out S1_in 1.62k R5 L2_out S2_in 330 R6 L3_out S3_in 220 S1_out S2_out S3_out 47 R2 47 R3 47 E1 E2 E3 refdes=conn footprint=rade net=vcc:1 net=vss:2 net=vfet:3 net=gnd:4 net=vbias:5 net=vfet:6 net=vss:7 net=gnd:8 net=e3:9 net=gnd:10 net=vcc:11 net=vbias:12 net=vcc:13 net=vss:14 net=vfet:15 net=gnd:16 net=vbias:17 net=vfet:18 net=vss:19 net=gnd:20 net=e2:21 net=gnd:22 net=vcc:23 net=vbias:24 net=vcc:25 net=vss:26 net=vfet:27 net=gnd:28 net=vbias:29 net=vfet:30 net=vss:31 net=gnd:32 net=e1:33 net=gnd:34 net=vcc:35 net=vbias:36 net=gnd:37 net=gnd:38 net=gnd:39 MSL RAD FEE: RADE board interconnects TITLE $Id: RADE.sch,v /11/07 12:20:04 bottcher Exp $ $RCSfile: RADE.sch,v $ $Revision: 1.6 $ FILE: REVISION: 1 1 Stephan I Böttcher PAGE OF DRAWN BY: R1 Figure 1: RADE master schematics: RADE.sch 4

5 C1 10n c1206 Vfet C3 fet_drain BF862 SOT23 2 D opdc R4 10k Vcc Vss R2 33/33/100 Meg c0805 C2 8.2/3.3/1 p fet_gate G J1 3 1 S R3 15k R1 470 vcc_filtered C6 C4 C7 R5 15Meg c0805 R6 15Meg c0805 vbias_filtered C5 10n c1206 detector Vbias 75 R61 AD8005 U1 R VCC + 1/2.2/5.1 k 1 CFA out 4 - VSS SOT23_5 opinv 2 vss_filtered 75 R71 R C31 MSL RAD FEE Charge Sensitive Amplifier (CSA) TITLE $Id: CSA-1.sch,v /12/04 10:07:12 bottcher Exp $ $RCSfile: CSA-1.sch,v $ $Revision: 1.22 $ FILE: REVISION: 1 1 Stephan I Böttcher PAGE OF DRAWN BY: css C11 33p Figure 2: Charge sensitive amplifier schematics: CSA-1.sch 5

6 vi 4k...10k R3 220pF...560pF C5 Vss Vcc out C4 C3 R5 75 R4 75 in 0Ohm R2 R1*C1 = 100us/270us R2*C1 = 2.2us R3*C3 = 2.2us pz 10k...200k R1 C1 1.4nF...10nF R7 2.2k vii AD8005 U1 5 3 VCC + CFA 4 - VSS 2 vcc_filtered 1 SOT23_5 vss_filtered MSL RAD FEE Fast SHaper (FSH) TITLE $Id: FSH-1.sch,v /10/23 16:59:29 bottcher Exp $ $RCSfile: FSH-1.sch,v $ $Revision: 1.12 $ FILE: REVISION: 1 1 Stephan I Böttcher PAGE OF DRAWN BY: Figure 3: Fast shaper schematics: FSH-1.sch 6

7 Figure 4: Front layer copper 7

8 Figure 5: Ground layer copper 8

9 Figure 6: Power layer copper 9

10 Figure 7: Back layer copper 10

11 Figure 8: Assembly 11