EDA365. DesignCon 2008

Transcription

1 DesignCon 2008 The Impact of Common Mode Currents and Interconnect Inductance on the Signal Quality of Differential Signals in Multi-Board PCB Systems Samuel Connor, IBM Dr. Bhyrav Mutnury, IBM Mosin Mondal, University of Washington

2 Pravin Patel, IBM Joseph C. (Jay) Diepenbrock, IBM Moises Cases, IBM Dr. Bruce Archambeault, IBM

3 Abstract The high-speed differential signals in today's multi-board systems often carry significant amounts of common mode current also. When the common mode currents flow through the inter-board connectors, the inductance of the common mode current return path in the connectors creates a noise voltage between the connected boards. The effect of this common mode noise on received differential signals is demonstrated in this paper using measurement and modeling results. Effective and accurate methods for quantifying the amount of common mode current, the amount of inductance in the common mode current return path, and the impact of the common mode noise on the differential signal are proposed to ensure better design practices. Author(s) Biography Sam Connor is a senior engineer responsible for the development of EMC and SI analysis tools/applications. Mr. Connor's current work activities and research interests also include electromagnetic modeling and simulation in support of power distribution and link path design for printed circuit boards. He has co-authored more than 20 papers in computational electromagnetics, mostly applied to decoupling and high-speed signaling issues in PCB designs. He is a Senior Member of the IEEE and is currently the webmaster for the TC-9 subcommittee of the IEEE EMC Society. Dr. Bhyrav Mutnury is an electrical interconnect and package design engineer at IBM in Austin, TX. He received his M.S. and Ph.D degrees from the Georgia Institute of Technology in 2002 and 2005, respectively. Dr. Mutnury joined System x server group in IBM, Austin, in 2005 as electrical design engineer for Intel and AMD based high speed server packages and boards. Dr. Mutnury has authored or co-authored more than 25 journal and conference papers and filed more than 12 patents. Mosin Mondal is a Ph.D. student in the Department of Electrical Engineering at University of Washington, Seattle, WA. He received his M.S. degree in ECE from Rice University, Houston, TX and the B.E. degree in Electronics and Telecommunication Engineering from Jadavpur University, India. He worked with IBM Corporation, RTP, NC, as an Engineering Co-op in He also worked with Cadence Design Systems India Pvt. Ltd. ( ) as a Member of the Technical Staff on signal integrity of digital ICs. His research interests include combined circuit-em simulations, interconnect modeling, timing analysis and signal integrity. Mr. Mondal is a recipient of the Best Paper Award in IEEE EPEP, Pravin Patel is a Senior Engineer and Technical Leader working for IBM xseries Server Development. He is involved in defining product architecture, creating product strategies, and time and frequency domain SI analysis/simulation of Intel base server products. His current activities include the design and analysis of Serdes interfaces for BladeCenter product. He

4 performs modeling, simulation and measurements of the high speed serial link Channels. The other areas of his responsibilities include design and development of models for line cards, backplanes, traces, via and performing simulations for system level voltage and timing budgets and jitter characterization. He is an active member of T11.2 and IEEE802.3 channel model standard committee from IBM. He has authored or co-authored number of papers in IEEE EPEP, IEEE ECTC and Designcon Conferences. He received a B.S. degree in electrical engineering from the New Jersey Institute of Technology in Joseph C. (Jay) Diepenbrock received the Sc. B. and M. S. degrees in electrical engineering from Brown University, Providence, RI, and Syracuse University, Syracuse, NY, respectively. Mr. Diepenbrock has worked in a number of areas in IBM including bipolar and CMOS IC design, analog and digital circuit design, backplane design and simulation, and network hardware and server product development. He is currently a Senior Technical Staff Member in the Interconnect Qualification Engineering department in IBM s Integrated Supply Chain, working on the electrical testing and modeling of connectors and cables. Moises Cases has thirty-eight years of progressive experience in very-large scale integration chip and package designs, in system level electrical and package designs, and in complex project and people management. Presently, he is a Distinguished Engineer at IBM System and Technology Group and the team leader for system electrical design and integration of modular and blade servers. Responsible for signal and power distribution integrity, and system level timing for complex multiple board system designs. He obtained Master of Science in Computer Engineering from Syracuse University, NY in 1979, Master of Science in Electronic Engineering from New York University, NY in 1973, and a Bachelor of Science in Electrical Engineering from City College of New York, NY in He is a senior member of IEEE and a member of Tau Beta Pi and Eta Kappa Nu honor societies. Mr. Cases has received the Hispanic in Technology Corporate Award from the Society of Hispanic Professional Engineers in 2006, the Corporate Business/ Community Representative of the Year Award from Austin Independent School District in 2007, and the Albert V. Baez Award from HENAAC in Mr. Cases has received 43 U.S. Patents and has published 88 refereed technical papers on numerous proceedings, journals and transactions. Dr. Bruce Archambeault is an IBM Distinguished Engineer at IBM in Research Triangle Park, NC. He received his B.S.E.E degree from the University of New Hampshire in 1977 and his M.S.E.E degree from Northeastern University in He received his Ph. D. from the University of New Hampshire in His doctoral research was in the area of computational electromagnetics applied to real-world EMC problems. He is the author of the book PCB Design for Real-World EMI Control and the lead author of the book titled EMI/EMC Computational Modeling Handbook.

5 Introduction The high-speed link paths in today s computer systems frequently span across multiple circuit boards. These signal paths on multiple boards are connected through connectors and cables, which often introduce impedance discontinuities. The challenges presented by multi-board signaling have been addressed in most high-speed interfaces by using differential signaling, which is less severely impacted by connector discontinuities. However, one pitfall of differential signaling is that there is a tendency to ignore the accompanying common mode signal and mode conversion effects. When signal integrity simulations only include the differential-to-differential parameters (S DD11 and S DD21 ) and ignore the mode conversion S-parameters or when they assume that the reference plane in each circuit board is tied perfectly to a common ground or when they do not include an accurate amount of common mode current from the driver, the results fail to capture the common mode effects on the differential eye diagram. The true scenario, however, is that at high frequencies the reference planes in multi-board systems are independent and, thus, significant noise voltages can develop between reference planes due to common mode currents flowing through the connectors. This noise voltage is a function of the common mode current and the loop inductance of the connector as seen by the signal line and its ground-reference pins. In this paper, the impact of the non-ideal ground-to-ground noise on the electrical behavior of multi-board differential signaling is studied. In particular, the amount of common mode signal present in a realistic design, the amount of inductance experienced by a signal line due to interboard connectors, the amount of noise between reference planes in two adjoining boards, the overall impact on the high speed differential signals (i.e. a reduction in the eye diagram opening), and the electromagnetic compatibility impact are described. The common mode noise that appears between the ground planes in different boards will depend on the common mode current and the impedance of the loop inductance seen by the signal lines inside the connector. Therefore, accurate analysis and successful design of printed circuit boards (PCBs) with board-to-board connections need to factor in the loop inductance contributed by the connectors, which depends on the actual current return paths. Since the common mode current flowing through the signal pin returns through the ground pins, the separation of the signal pin from the ground pins and their relative positioning plays an important role in determining the loop inductance. Finding the pin configuration that minimizes inductance is very important for signal integrity in PCBs. In this paper, the Partial Element Equivalent Circuit (PEEC) method and the magnetic energy conservation method are employed for analyzing the inductance efficiently. In previous work, we have shown that significant common mode currents can be generated on a differential pair by driver rise- and fall-time mismatch or even small amounts of signal skew. Additionally, there can be differential-to-common mode conversion in the PCB structures and in the connectors. The common mode current waveform can be calculated, if these signal characteristics are known, or can be determined through measurement, as we demonstrate in this paper.

6 1. Simulated Eye Diagrams for Differential Signals in Multi- Board Systems Are Too Optimistic To determine whether our signal integrity simulations are accurately predicting the eye diagram for differential link paths in multi-board systems, we simulated a link path with HSPICE, using an s-parameter block from a vector network analyzer (VNA) measurement, and compared the results with a direct time domain measurement of the same link path. Figure 1 shows an eye diagram obtained from a parallel bit error rate tester (parbert) measurement when a 800 mv peak-peak differential signal is transmitted through the device under test (DUT) at 2.125Gbps using a PRBS7 bit pattern. The DUT includes a driver test card connected to a back plane through an AirMax VS 1 connector onto which a receiver test card is connected through a GbX 2 connector. The total path length is approximately 18 inches in the 3 PCBs plus the length of the 2 connectors. SMA cables from the parbert generator are connected to the driver test card SMA connectors. The SMA connectors on the receiver test card feed into a sampling scope for capturing the eye waveform. It can be seen from Figure 1 that the eye height is approximately 440mV. Figure 2 shows the eye diagram obtained from an HSPICE simulation of the link path, and the eye is more open, with an eye height of 510 mv. 440mV Figure 1: Eye diagram measured with parbert equipment. 1 AirMax VS is a registered trademark of FCI SA. 2 GbX is a registered trademark of Amphenol Corp.

7 510mV Figure 2: Eye diagram simulated with SPICE, using an ideal differential source. This difference of 15% is too high if designers are relying on the HSPICE simulation to determine link path performance and to make design decisions. In our investigation, we discover that the difference in eye diagram height can be almost eliminated by including the common mode signals in the analysis. Section 2 discusses the sources of common mode signals in differential link paths and introduces a couple ways to quantify the common mode levels in a design. 2. Common Mode Currents in Differential Signaling The differential links in today s computer systems are typically not driven with true differential drivers. The two mated lines are driven complementary to each other, but there is a certain amount of imbalance that creates common mode currents on the differential pair. The receivers in most integrated circuits have excellent common mode rejection, and this leads to a temptation to ignore the common mode currents on the link path. But this is a risky practice, since the common mode currents can cause signal integrity and electromagnetic interference (EMI) problems. In this section, we will describe several sources of common mode current in multiboard link paths and ways to quantify them. Skew and Rise/Fall Time Mismatch The input/output (I/O) drivers themselves generate some of the common mode currents. Even well-matched complementary drivers will have a certain amount of mismatch in the rise and fall times due to differences in NMOS and PMOS transistor performance and will have a certain amount of skew due to mismatch in path lengths in the integrated circuit (IC) and IC package. In previous work [1], it has been shown how small amounts of driver rise/fall time mismatch, driver skew, and driver amplitude mismatch can create a common mode signal with amplitude on the same order as the intentional signal. Further skew can be introduced by the printed circuit board (PCB) due to trace length mismatch and due to inconsistency in the dielectric material which causes the two differential mates to experience slight differences in permittivity and therefore propagation velocity [6]. If the total rise/fall time mismatch and skew can be estimated from the

8 IC and PCB designs, the amount of common mode signal can be calculated by adding together the time domain waveforms of the differential mates. For cases where the design skew is not known, the common mode voltage can also be measured with an oscilloscope by measuring each leg of the differential pair individually and by adding the two measured waveforms. We performed these measurements at two places in our sample link path, at the output of the coaxial cables from the parbert and at the inter-board connector near the driver. The common mode voltage measurement for the parbert output is shown in Figure 3. The measurement shows a significant amount of common mode signal (about 160 mv) that is being injected into our link path during the eye diagram measurement. The parbert s outputs are better matched than this, so the likely cause of this high amount of common mode signal is mismatch in the coaxial cables. For this reason, care should be taken to ensure that matched cables are used when making eye diagram and bit error rate measurements with the parbert. Figure 3. Common mode voltage measurement at the output of the coaxial cables attached parbert. to the The single-ended voltage waveforms of the differential pair at the driver-side inter-board connector are plotted in Figure 4, and the common mode waveform is shown in Figure 5 (the sum of the two waveforms in Figure 4). If the driver s common mode output is not known or is difficult to measure, this measurement could be used instead to determine what value to use for simulation purposes.

9 Voltage (mv) Figure 4. Single-ended voltage waveforms at driver-side inter-board connector. Time (ns) Figure 5. Common mode voltage at driver-side inter-board connector.

10 Mode Conversion Another source of common mode currents is mode conversion in the PCB discontinuities (e.g. vias) and/or inter-board connectors. The s-parameters plotted in Figure 6 below are measured data on an actual AirMax connector. The SCD21 term indicates how much of the differential signal is converted to common mode signal when a pair passes through the connector. The value is close to -20 db across the frequencies of interest, which means that 1/10 of the driven differential voltage is converted to common mode signal by the time the differential pair exits the connector. Mode conversion works the other way as well, from common mode to differential mode, and this conversion provides another way for common mode noise to impact the differential signal and its eye diagram. The SDC21 term (the term with a box around it) indicates how much of the common mode signal is converted to differential mode signal. The value is close to -20 db across the frequencies of interest, so approximately 1/10 of the common mode voltage is converted to differential mode signal on the other side of the connector. The SDC21 term is also a measure of the differential pair s susceptibility to interference from other signals, radiated fields, and electrostatic discharge (ESD) events, which are all common mode sources. These mode conversion levels can be considered small, but depending on the margin in the eye diagram, they could make the difference between a robust design and intermittent failures. Certainly, if a simulator does not account for these mode conversion terms, it is potentially yielding incorrect results.

11 Figure 6. Four-port, mixed-mode s-parameters for our sample link path. 3. Inter-board Ground-to-Ground Noise Caused by Common Mode Currents The common mode noise that appears between the ground planes in different boards will depend on the common mode current and the common mode loop inductance seen by the signal lines due to the connector. Therefore, accurate analysis and successful design of PCBs with multiple boards connected to a main board need to factor in the loop inductance contributed by the connectors, which depends on the actual current return paths [2]. Since the common mode current flowing through the signal pin returns through the ground pins, the separation of the signal pin from the ground pins and their relative positioning plays an important role in determining the loop inductance. Finding the pin configuration that minimizes inductance is very important for signal integrity in PCBs. In this paper, the Partial Element Equivalent Circuit (PEEC) method [3], and magnetic energy conservation method [4] are employed for analyzing the inductance efficiently. PEEC Method The model of Figure 7 is implemented in IBM s PEEC solver PowerPEEC. Small lengths of microstrip lines with characteristic impedance of 50 Ω are used to obtain the inductance as

12 Figure 7. CAD model of an example inter-board connector. seen by the microstrip lines. The actual dimensions of the AirMax connector s pins are used for modeling the DUT. Different possible configurations of the ground pins are considered for estimating the inductance seen by the microstrip line. Depending on the number of grounded pins and their locations, different inductance values are obtained. Figure 8 shows four possible configurations and the corresponding inductance values as determined by PowerPEEC. The horizontal spacing of the pins is 2 mm while the vertical spacing is 1.4 mm in Figure 8. Note that the white pins are considered as floating for the purpose of inductance computation. The values of inductance show strong dependence on the ground pin configuration, ranging between 16nH-37nH for all the experiments performed on this connector nh nh (a) (b) nh nh (c) (d) Signal Pin Related Ground Pins Figure 8. Illustration of a few possible placements of Ground pins around the signal pin along with the corresponding inductance.

13 Figure 9 illustrates another important point that the loop inductance seen by the two pins of a differential pair may be different depending on their locations. For the AirMax connector used in the measurements, the loop inductance for pin 1 is 26.6nH whereas pin 2 experiences 23.6nH. Similarly, pins 3 and 4 have loop inductances of 31.8nH and 28.8nH, respectively. This will cause propagation delay mismatch between the two leads of a differential pair creating more skew in the connector. Ground pins Differential pair Figure 9. Location of a couple differential pairs in the AirMax connector. Although the results obtained by PEEC simulation will be highly accurate, depending on the number of pins, the model size and corresponding simulation time could be large. For example, for the AirMax connector, the number of pins could be as high as 120 and the PEEC simulation could take tens of minutes for a single configuration of the ground pins making the search for the optimal configuration time consuming. Therefore, a faster method which gives reasonable accuracy to explore different connectors and different ground configurations is used. Magnetic Energy Conservation Method For measuring the loop inductance due to the connector, the method described by Krauter and Mehrotra in [3] is found to be appropriate and convenient. The method determines the equivalent loop inductance based upon the conservation of magnetic energy stored in the conductor system. For the AirMax connector, each pin has two segments of unequal length one horizontal and one vertical. For the purpose of inductance computation, a unit current source is applied between the horizontal terminal of the signal pin and the terminal shorting all horizontal terminals of the ground pins. The terminals of the vertical parts of all pins will be considered shorted assuming quasi-static mode. For applying the energy-equivalence method [3] to a system consisting of a signal line and N ground lines, let the signal line be represented by the subscript s and the ground lines using gi where i is the index of the ground line. The quantities corresponding to the horizontal (vertical) conductors will be denoted by superscript H (V). Let I be the vector of currents flowing through each pin with directions signified by the sign of the current value for unit current through the signal pin. The partial inductance matrices for the horizontal conductors, M H, and the vertical conductors, M V, will be given by the following matrix considering the respective parts only:

14 L M s sg1... M sgn M g1s Lg1 M g1g 2... M P =... M g 2 g1... H M gns LgN In the matrix above, the L terms represent the partial self inductances and the M terms the partial mutual inductances, which are computed using the formulae presented in [4]. The equivalent loop inductance L loop, which is the total magnetic energy stored for each signal pin current, can then be calculated as: H M 0 I H V T L loop = [ I I ] = I( M + M ) I V 0 M I This formulation produces a huge speedup in inductance computation more than four orders of magnitude with inductance values within 5% of the values obtained from PowerPEEC, as shown in Table I. Therefore, this formulation can be utilized for determining the optimal ground pin configuration, quick inductance computation for signal integrity analysis and many other applications. TABLE I: PEEC VS. FAST METHOD PowerPEEC (nh) Fast Method (nh) Percentage Error Impact of Inter-board Noise on Electromagnetic Compatibility The voltage created between ground planes in a multi-board system is directly related to the inductance calculated in the previous sections and the rate of change of the common mode current (which increases with shorter rise and fall times). When driven by this voltage source, the ground planes can act as an efficient antenna and cause electromagnetic compatibility (EMC) problems for systems. Using a Method of Moments (MoM)-based full wave solver, we analyzed the field strength at a distance of 3 meters for a couple of ground pin configurations which correspond to different inductances. As expected, the trends in Figure 10 (calculated by a moving average of the data to smooth out resonance effects which are very dependent on the specific geometry) show that the inter-board connection with higher inductance causes higher radiation levels. Therefore, minimizing the loop inductance of the inter-board connectors is beneficial for EMC as well as signal integrity, and this fact needs to be considered when designing the pinout of inter-board connectors.

15 Figure 10. Comparison of radiated electric field strength for different interboard connection inductance. 4. Improved Eye Diagram Simulation with Common Mode Signal Included Once the inductance of the inter-board connectors and the profile of the common mode current are known, a more accurate HSPICE simulation can be run. In our example, we are using a measured s-parameter block, which includes the mode conversion effects of the inter-board connectors, so we only need to add the common mode signal (the amount of common mode signal produced by the parbert and the coaxial cables) to the drivers to get an improved answer. When we do this, the new eye diagram results are shown in Figure 11. The 450 mv eye height almost matches the measured value of 440 mv. The error is now 2%, significantly better than the 15% error achieved when the common mode signal is not included in the source.

16 450mV Figure 11: Eye diagram predicted by SPICE simulation of the entire channel when the board-to-board noise is included in the model. Conclusions In this paper, the effect of non-uniform, common mode current return path on common mode noise in high speed differential signals is demonstrated in multi-board systems using both measured and simulated data. Two main points have been made. First, real-world, differential link path designs have some amount of common mode signal on them due to the driver rise/fall time mismatch, driver skew, driver amplitude mismatch, trace length skew, PCB fiber weave effects, and mode conversion in the connector. Even carefully designed IC packages will have 5-7 ps of skew, which is enough to create common mode signal amplitudes on the same order as the intentional signal. This common mode signal must be included in signal integrity simulations, because the effect is not negligible as shown by the reduction in eye height error from 15% to 2% for the example link path. The effect will become more significant as data rates increase, because the skew becomes a larger portion of the bit width. The second point is that the loop inductance of the inter-board connectors can be quantified and used to predict the ground-to-ground noise voltage between boards or to calculate the common mode signal level from measurements of the ground-to-ground noise. This paper also shows that minimizing the loop inductance of the inter-board connectors will reduce the ground-to-ground noise, which will in turn have a positive impact on the signal integrity and EMC performance of the link path. References [1] B. Archambeault, S. Connor, J. Diepenbrock, EMI Emissions from Mismatches in High- Speed Differential Signal Traces and Cables, in DesignCon Conference, [2] M. Beattie and L. Pileggi, Inductance 101: Modeling and Extraction, in Proc. Design Automation Conference, pp , 2001.

17 [3] A. E. Ruehli, Equivalent Circuit Models for Three Dimensional Multiconductor Systems, IEEE Transactions on MTT, vol. 22, pp , Mar [4] B. Krauter and S. Mehrotra, Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis, in Proc. Design Automation Conference, pp , [5] A. E. Ruehli, Inductance Calculations in a Complex Integrated Circuit Environment, IBM Journal of Research and Development, vol. 16, no, 5, pp , [6] J. Loyer, R. Kunze, X. Ye, Fiber-Weave Effect: Practical Impact Analysis and Mitigation Strategies, in DesignCon Conference, 2007.