Dual, 8-Bit, 100Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs

Transcription

1 9-4; Rev 0; 4/0 Dual, 8-Bit, 00Msps, 3.3, Low-Power ADC General Description The is a 3.3, dual, 8-bit analog-to-digital converter (ADC) featuring fully differential wideband trackand-hold (T/H) inputs, driving two ADCs. The is optimized for low power, small size, and high-dynamic performance for applications in imaging, instrumentation, and digital communications. This ADC operates from a single.7 to 3.6 supply, consuming only 64mW, while delivering a typical signal-to-noise and distortion (SINAD) of 48.dB at an input frequency of 50MHz and a sampling rate of 00Msps. The T/H-driven input stages incorporate 400MHz (-3dB) input amplifiers. The converters may also be operated with singleended inputs. In addition to low operating power, the features a 3.mA sleep mode, as well as a 0.5µA power-down mode to conserve power during idle periods. An internal.048 precision bandgap reference sets the full-scale range of the ADC. A flexible reference structure allows the use of this internal or an externally applied reference, if desired, for applications requiring increased accuracy or a different input voltage range. The features parallel, CMOS-compatible threestate outputs. The digital output format can be set to two s complement or straight offset binary through a single control pin. The device provides for a separate output power supply of.7 to 3.6 for flexible interfacing with various logic families. The is available in a 7mm x 7mm, 48-pin TQFP package, and is specified for the extended industrial (-40 C to +85 C) temperature range. Pin-compatible lower speed versions of the are also available. Refer to the MAX95 data sheet for 40Msps and the MAX97 data sheet for 60Msps. In addition to these speed grades, this family includes a multiplexed output version (MAX96, 40Msps), for which digital data is presented time interleaved and on a single, parallel 8-bit output port. For a 0-bit, pin-compatible upgrade, refer to the MAX80 data sheet. With the N.C. pins of the internally pulled down to ground, this ADC becomes a drop-in replacement for the MAX80. Applications Baseband I/Q Sampling Multichannel IF Sampling Ultrasound and Medical Imaging Battery-Powered Instrumentation WLAN, WWAN, WLL, MMDS Modems Set-Top Boxes SAT Terminals Features Single.7 to 3.6 Operation Excellent Dynamic Performance 48.dB/47.6dB SINAD at f IN = 50MHz/00MHz 66dBc/6.5dBc SFDR at f IN = 50MHz/00MHz -7dB Interchannel Crosstalk at f IN = 50MHz Low Power 64mW (Normal Operation) 0.6mW (Sleep Mode) 0.5µW (Shutdown Mode) 0.05dB Gain and ±0. Phase Matching Wide ± P-P Differential Analog Input oltage Range 400MHz -3dB Input Bandwidth On-Chip.048 Precision Bandgap Reference User-Selectable Output Format Two s Complement or Offset Binary Pin-Compatible 8-Bit and 0-Bit Upgrades Available DD GND INA+ INA- DD GND INB- INB+ GND DD CLK REFN REFP REFIN REFOUT D7A D6A D5A D4A D3A DA DA D0A GND DD Ordering Information PART TEMP RANGE PIN-PACKAGE ECM -40 C to +85 C 48 TQFP-EP* *EP = Exposed paddle Functional Diagram and Pin Compatible Upgrades table appear at end of data sheet. Pin Configuration DD GND T/B SLEEP PD OE D7B D6B D5B D4B TQFP-EP N.C. N.C. OGND O DD O DD OGND N.C. N.C. D0B DB DB D3B Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS DD, O DD to GND to +3.6 OGND to GND to +0.3 INA+, INA-, INB+, INB- to GND to DD REFIN, REFOUT, REFP, REFN,, CLK to GND to ( DD + 0.3) OE, PD, SLEEP, T/B, D7A D0A, D7B D0B to OGND to (O DD + 0.3) Continuous Power Dissipation (T A = +70 C) 48-Pin TQFP (derate.5mw/ C above +70 C)...000mW Operating Temperature Range C to +85 C Junction Temperature C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( DD = 3.3, O DD =.5, and.µf capacitors from REFP, REFN, and to GND; REFOUT connected to REFIN through a 0kΩ resistor, IN = P-P (differential with respect to ), C L = 0pF at digital outputs, f CLK = 00MHz, T A = T MIN to T MAX, unless otherwise noted. +5 C guaranteed by production test, <+5 C guaranteed by design and characterization. Typical values are at T A = +5 C.) DC ACCURACY PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS Resolution 8 Bits Integral Nonlinearity INL f IN = 7.5MHz (Note ) ±0.3 ± LSB Differential Nonlinearity DNL f IN = 7.5MHz, no missing codes guaranteed (Note ) ±0. ± LSB Offset Error ±4 %FS Gain Error ±4 %FS Gain Temperature Coefficient ±00 ppm/ C ANALOG INPUT Differential Input oltage Range DIFF Differential or single-ended inputs ±.0 Common-Mode Input oltage Range CM D D / ±0. Input Resistance R IN Switched capacitor load 57 kω Input Capacitance C IN 5 pf CONERSION RATE Maximum Clock Frequency f CLK 00 MHz Data Latency 5 DYNAMIC CHARACTERISTICS (f CLK = 00MHz, 4096-point FFT) Signal-to-Noise Ratio SNR f INA or B = 7.5MHz at -db FS 48.5 f INA or B = 0MHz at -db FS f INA or B = 50MHz at -db FS 48.3 f INA or B = 5.MHz at -db FS 48. Clock Cycles db

3 ELECTRICAL CHARACTERISTICS (continued) ( DD = 3.3, O DD =.5, and.µf capacitors from REFP, REFN, and to GND; REFOUT connected to REFIN through a 0kΩ resistor, IN = P-P (differential with respect to ), C L = 0pF at digital outputs, f CLK = 00MHz, T A = T MIN to T MAX, unless otherwise noted. +5 C guaranteed by production test, <+5 C guaranteed by design and characterization. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS Signal-to-Noise and Distortion Spurious-Free Dynamic Range Third-Harmonic Distortion Intermodulation Distortion (First Five Odd-Order IMDs) Third-Order Intermodulation Distortion Total Harmonic Distortion (First Four Harmonics) SINAD SFDR HD3 IMD IM3 THD f INA or B = 7.5MHz at -db FS 48.3 f INA or B = 0MHz at -db FS f INA or B = 50MHz at -db FS 48. f INA or B = 5.MHz at -db FS 48 f INA or B = 7.5MHz at -db FS 67 f INA or B = 0MHz at -db FS f INA or B = 50MHz at -db FS 66 f INA or B = 5.MHz at -db FS 65 f INA or B = 7.5MHz at -db FS - 67 f INA or B = 0MHz at -db FS - 67 f INA or B = 50MHz at -db FS - 67 f INA or B = 5.MHz at -db FS - 66 f IN(A or B) =.989MHz at -7dB FS f IN(A or B) =.038MHz at -7dB FS (Note ) f IN(A or B) =.989MHz at -7dB FS f IN(A or B) =.038MHz at -7dB FS (Note ) f INA or B = 7.5MHz at -db FS - 66 db dbc dbc dbc - 80 dbc f INA or B = 0MHz at -db FS f INA or B = 50MHz at -db FS - 64 f INA or B = 5.MHz at -db FS - 58 Small-Signal Bandwidth Input at -0dB FS, differential inputs 500 MHz Full-Power Bandwidth FPBW Input at -db FS, differential inputs 400 MHz Gain Flatness (MHz Spacing) f IN(A or B) = 06MHz at -db FS f IN(A or B) = 8MHz at -db FS (Note 3) dbc 0.05 db Aperture Delay t AD ns Aperture Jitter t AJ db SNR degradation at Nyquist ps RMS Overdrive Recovery Time For.5 full-scale input ns IN T ER N A L REF ER EN C E ( RE FIN = RE FOU T thr oug h 0kΩ r esi stor ; RE FP, RE FN, and C OM l evel s ar e g ener ated i nter nal l y.) Reference Output oltage REFOUT (Note 4).048 ± 3% Positive Reference Output oltage Negative Reference Output oltage REFP (Note 5).6 REFN (Note 5).38 Common-Mode Level (Note 5) D D / ±0. 3

4 ELECTRICAL CHARACTERISTICS (continued) ( DD = 3.3, O DD =.5, and.µf capacitors from REFP, REFN, and to GND; REFOUT connected to REFIN through a 0kΩ resistor, IN = P-P (differential with respect to ), C L = 0pF at digital outputs, f CLK = 00MHz, T A = T MIN to T MAX, unless otherwise noted. +5 C guaranteed by production test, <+5 C guaranteed by design and characterization. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS Differential Reference Output oltage Range Reference Temperature Coefficient BUFFERED EXTERNAL REFERENCE ( REFIN =.048) Positive Reference Output oltage REF REF = REFP - REFN.04 ± 3% TC REF ±00 ppm/ C REFP (Note 5).6 Negative Reference Output oltage REFN (Note 5).38 Common-Mode Level (Note 5) D D / ± 0. Differential Reference Output oltage Range REF REF = REFP - REFN.04 ± % REFIN Resistance R REFIN > 50 MΩ Maximum REFP, Source Current I SOURCE 5 ma Maximum REFP, Sink Current I SINK - 50 µa Maximum REFN Source Current I SOURCE 50 µa Maximum REFN Sink Current I SINK - 5 ma U N B U F F ER ED EXT ER N A L R EF ER EN C E ( RE F IN = AGN D, r efer ence vol tag e ap p l i ed to RE FP, RE FN, and C OM ) REFP, REFN Input Resistance R REFP, R REFN Measured between REFP,, REFN, and 4 kω REFP, REFN, Input Capacitance C IN 5 pf Differential Reference Input oltage Range REF REF = REFP - REFN.04 ±0% Input oltage Range D D / ±5% REFP Input oltage REFP C OM + RE F / REFN Input oltage REFN C OM - RE F / DIGITAL INPUTS (CLK, PD, OE, SLEEP, T/B) CLK Input High Threshold IH PD, OE, SLEEP, T/B 0.8 DD 0.8 O DD 4

5 ELECTRICAL CHARACTERISTICS (continued) ( DD = 3.3, O DD =.5, and.µf capacitors from REFP, REFN, and to GND; REFOUT connected to REFIN through a 0kΩ resistor, IN = P-P (differential with respect to ), C L = 0pF at digital outputs, f CLK = 00MHz, T A = T MIN to T MAX, unless otherwise noted. +5 C guaranteed by production test, <+5 C guaranteed by design and characterization. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS 0. CLK DD Input Low Threshold IL 0. PD, OE, SLEEP, T/B O DD Input Hysteresis HYST 0.5 I IH IH = DD = O DD ±0 Input Leakage µa I IL IL = 0 ±0 Input Capacitance C IN 5 pf DIGITAL OUTPUTS ( D7A D0A, D7B D0B) Output oltage Low OL I SINK = -00µA 0. Output oltage High OH I SOURCE = 00µA O DD - 0. Three-State Leakage Current I LEAK OE = O DD ±0 µa Three-State Output Capacitance C OUT OE = O DD 5 pf POWER REQUIREMENTS Analog Supply oltage Range DD Output Supply oltage Range O DD C L = 5pF Analog Supply Current Output Supply Current Analog Power Dissipation Power-Supply Rejection TIMING CHARACTERISTICS CLK Rise to Output Data alid Time I DD I ODD PDISS PSRR Operating, f INA & B = 0MHz at -db FS applied to both channels Sleep mode Shutdown, clock idle, PD = OE = O DD µa Operating, f INA & B = 0MHz at -db FS applied to both channels (Note 6) Sleep mode ma.5 ma Shutdown, clock idle, PD = OE = O DD 0 Operating, f INA & B = 0MHz at -db FS applied to both channels Sleep mode 0.6 Shutdown, clock idle, PD = OE = O DD µw Offset, DD ±5% ±3 Gain, DD ±5% ±3 t DO C L = 0pF (Notes, 7) ns OE Fall to Output Enable Time t ENABLE 5 ns OE Rise to Output Disable Time t DISABLE 5 ns CLK Pulse Width High t CH Clock period: 0ns (Note 7) 5 ± 0.5 ns CLK Pulse Width Low t CL Clock period: 0ns (Note 7) 5 ± 0.5 ns µa mw m/ 5

6 ELECTRICAL CHARACTERISTICS (continued) ( DD = 3.3, O DD =.5, and.µf capacitors from REFP, REFN, and to GND; REFOUT connected to REFIN through a 0kΩ resistor, IN = P-P (differential with respect to ), C L = 0pF at digital outputs, f CLK = 00MHz, T A = T MIN to T MAX, unless otherwise noted. +5 C guaranteed by production test, <+5 C guaranteed by design and characterization. Typical values are at T A = +5 C.) PARAMETER SYMBOL CONDITIONS MIN T YP MAX UNITS Wake up from sleep mode Wake-Up Time t WAKE Wake up from shutdown mode (Note ) 0 CHANNEL-TO-CHANNEL MATCHING Crosstalk f INA or B = 0MHz at -db FS (Note 8) - 7 db Gain Matching f INA or B = 0MHz at -db FS (Note 9) 0.05 db Phase Matching f INA or B = 0MHz at -db FS (Note 0) ± 0. Degrees µs Note : Note : Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Guaranteed by design. Not subject to production testing. Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Analog attenuation is defined as the amount of attenuation of the fundamental bin from a converted FFT between two applied input signals with the same magnitude (peak-to-peak) at f IN and f IN. REFIN and REFOUT should be bypassed to GND with a (min) and.µf (typ) capacitor. REFP, REFN, and should be bypassed to GND with a (min) and.µf (typ) capacitor. Typical analog output current at f INA & B = 0MHz. For digital output currents vs. analog input frequency, see Typical Operating Characteristics. See Figure 3 for detailed system timing diagrams. Clock to data valid timing is measured from 50% of the clock level to 50% of the data output level. Crosstalk rejection is tested by applying a test tone to one channel and holding the other channel at DC level. Crosstalk is measured by calculating the power ratio of the fundamental of each channel s FFT. Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the fundamental of the calculated FFT. Note 0: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. Note : SINAD settles to within 0.5dB of its typical value in unbuffered external reference mode. 6

7 Typical Operating Characteristics ( DD = 3.3, O DD =.5, REFIN =.048, differential input at -db FS, f CLK = 00MHz, C L 0pF, T A = +5 C, unless otherwise noted.) AMPLITUDE (db) FFT PLOT CHA (DIFFERENTIAL INPUT, 89-POINT DATA RECORD) f INA f INB f CLK = MHz f INA = MHz f INB = MHz AIN = -db FS COHERENT SAMPLING HD HD toc0 AMPLITUDE (db) FFT PLOT CHA (DIFFERENTIAL INPUT, 89-POINT DATA RECORD) HD f INB f CLK = MHz f INA = MHz f INB = MHz AIN = -db FS COHERENT SAMPLING f INA HD toc0 AMPLITUDE (db) FFT PLOT CHA (DIFFERENTIAL INPUT, 89-POINT DATA RECORD) f INA f INB f CLK = MHz f INA = MHz f INB = MHz AIN = -db FS COHERENT SAMPLING HD HD toc03 AMPLITUDE (db) TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 89-POINT DATA RECORD) 0 f CLK = MHz -0 f IN = MHz f -0 IN = MHz AIN = -7dB FS -30 COHERENT SAMPLING f IN fin toc04 AMPLITUDE (db) TWO-TONE IMD PLOT (DIFFERENTIAL INPUT, 89-POINT DATA RECORD) 0 f CLK = MHz -0 f IN = MHz f IN = MHz -0 AIN = -7dB FS -30 COHERENT SAMPLING f IN fin toc05 SNR (db) SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY CHB CHA toc SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY CHA toc TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY toc SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY CHA toc09 SNR (db) CHB THD (dbc) CHB SFDR (dbc) CHB 4-7 CHA

8 Typical Operating Characteristics (continued) ( DD = 3.3, O DD =.5, REFIN =.048, differential input at -db FS, f CLK = 00MHz, C L 0pF, T A = +5 C, unless otherwise noted.) SNR/SINAD, THD/SFDR (db, dbc) SNR/SINAD, THD/SFDR vs. TEMPERATURE 90 f IN = MHz SNR SFDR SINAD THD toc0 GAIN (db) FULL-POWER INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL toc GAIN (db) SMALL-SIGNAL INPUT BANDWIDTH vs. ANALOG INPUT FREQUENCY, DIFFERENTIAL IN = 00m P-P toc TEMPERATURE ( C) SIGNAL-TO-NOISE RATIO vs. INPUT POWER (f IN = MHz) toc SIGNAL-TO-NOISE + DISTORTION vs. INPUT POWER (f IN = MHz) toc TOTAL HARMONIC DISTORTION vs. INPUT POWER (f IN = MHz) toc SNR (db) 40 SINAD (db) 40 THD (dbc) INPUT POWER (db FS) INPUT POWER (db FS) INPUT POWER (db FS) SPURIOUS-FREE DYNAMIC RANGE vs. INPUT POWER (f IN = MHz) toc INTEGRAL NONLINEARITY (644-POINT DATA RECORD) toc DIFFERENTIAL NONLINEARITY (644-POINT DATA RECORD) toc8 SFDR (dbc) INL (LSB) DNL (LSB) INPUT POWER (db FS) DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE 8

9 Typical Operating Characteristics (continued) ( DD = 3.3, O DD =.5, REFIN =.048, differential input at -db FS, f CLK = 00MHz, C L 0pF, T A = +5 C, unless otherwise noted.) GAIN ERROR (%FS) IDD (ma) GAIN ERROR vs. TEMPERATURE, EXTERNAL REFERENCE REFIN =.048 CHB CHA TEMPERATURE ( C) ANALOG SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE ( C) toc9 toc OFFSET ERROR (%FS) IODD (ma) OFFSET ERROR vs. TEMPERATURE, EXTERNAL REFERENCE REFIN =.048 CHB CHA TEMPERATURE ( C) DIGITAL SUPPLY CURRENT vs. ANALOG INPUT FREQUENCY toc0 toc3 SNR/SINAD, THD/SFDR (db, dbc) SNR/SINAD, THD/SFDR (db, dbc) SNR/SINAD, THD/SFDR vs. SAMPLING SPEED SFDR SNR/SINAD, THD/SFDR vs. CLOCK DUTY CYCLE SINAD THD SNR f IN = MHz SINAD SAMPLING SPEED (Msps) SFDR THD SNR f IN = MHz CLOCK DUTY CYCLE (%) toc toc INTERNAL REFERENCE OLTAGE vs. ANALOG SUPPLY OLTAGE toc INTERNAL REFERENCE OLTAGE vs. TEMPERATURE toc6 REFOUT () REFOUT () DD () TEMPERATURE ( C) 9

10 PIN NAME FUNCTION Common-Mode oltage I/O. Bypass to GND with a capacitor. Pin Description Analog Supply oltage. Bypass to GND with a capacitor combination of.µf in parallel with, 6,, 4, 5 DD. 3, 7, 0, 3, 6 GND Analog Ground 4 INA+ Channel A Positive Analog Input. For single-ended operation connect signal source to INA+. 5 INA- Channel A Negative Analog Input. For single-ended operation connect INA- to. 8 INB- Channel B Negative Analog Input. For single-ended operation connect INB- to. 9 INB+ Channel B Positive Analog Input. For single-ended operation connect signal source to INB+. CLK Converter Clock Input 7 T/B T/B Selects the ADC Digital Output Format High: Two s complement Low: Straight offset binary 8 SLEEP 9 PD 0 OE Sleep Mode Input High: Disables both quantizers, but leaves the reference bias circuit active Low: Normal operation Active-High Power-Down Input High: Power-down mode Low: Normal operation Active-Low Output Enable Input High: Digital outputs disabled Low: Digital outputs enabled D7B Three-State Digital Output, Bit 7 (MSB), Channel B D6B Three-State Digital Output, Bit 6, Channel B 3 D5B Three-State Digital Output, Bit 5, Channel B 4 D4B Three-State Digital Output, Bit 4, Channel B 5 D3B Three-State Digital Output, Bit 3, Channel B 6 DB Three-State Digital Output, Bit, Channel B 7 DB Three-State Digital Output, Bit, Channel B 8 D0B Three-State Digital Output, Bit 0, Channel B 9, 30, 35, 36 N.C. No Connection 3, 34 OGND Output Driver Ground Output Driver Supply oltage. Bypass to OGND with a capacitor combination of.µf in parallel 3, 33 O DD with. 37 D0A Three-State Digital Output, Bit 0, Channel A 38 DA Three-State Digital Output, Bit, Channel A 39 DA Three-State Digital Output, Bit, Channel A 40 D3A Three-State Digital Output, Bit 3, Channel A 4 D4A Three-State Digital Output, Bit 4, Channel A 0

11 PIN NAME FUNCTION 4 D5A Three-State Digital Output, Bit 5, Channel A 43 D6A Three-State Digital Output, Bit 6, Channel A 44 D7A Three-State Digital Output, Bit 7 (MSB), Channel A 45 REFOUT 46 REFIN Pin Description (continued) Internal Reference oltage Output. May be connected to REFIN through a resistor or a resistordivider. Reference Input. REFIN = x ( REFP - REFN ). Bypass to GND with a > capacitor. 47 REFP 48 REFN Positive Reference I/O. Conversion range is ±( REFP - REFN ). Bypass to GND with a > capacitor. Negative Reference I/O. Conversion range is ±( REFP - REFN ). Bypass to GND with a > capacitor. -BIT FLASH ADC -BIT FLASH ADC STAGE STAGE STAGE 6 STAGE 7 STAGE STAGE STAGE 6 STAGE 7 DIGITAL ALIGNMENT LOGIC DIGITAL ALIGNMENT LOGIC T/H 8 T/H 8 INA D7A D0A INB D7B D0B INA = INPUT OLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE ENDED) INB = INPUT OLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE ENDED) Figure. Pipelined Architecture Stage Blocks Detailed Description The uses a seven-stage, fully differential pipelined architecture (Figure ) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. Including the delay through the output latch, the total clock-cycle latency is five clock cycles. Flash ADCs convert the held input voltages into a digital code. Internal MDACs convert the digitized results back into analog voltages, which are then subtracted from the original held input signals. The resulting error signals are then multiplied by two, and the residues are passed along to the next pipeline stages where the process is repeated until the signals have been processed by all seven stages. Input Track-and-Hold (T/H) Circuits Figure displays a simplified functional diagram of the input T/H circuits in both track and hold mode. In track mode, switches S, Sa, Sb, S4a, S4b, S5a, and S5b

12 INA+ S4a S4c Ca INTERNAL BIAS Sa S Ca S5a S3a OUT INA- S4b Cb Cb OUT S3b Sb S5b INTERNAL BIAS HOLD HOLD CLK INTERNAL BIAS TRACK TRACK INTERNAL NONOERLAPPING CLOCK SIGNALS Sa Ca S5a S3a S4a INB+ S4c Ca S OUT INB- S4b Cb Cb OUT S3b Sb INTERNAL BIAS S5b Figure. T/H Amplifiers are closed. The fully differential circuits sample the input signals onto the two capacitors (Ca and Cb) through switches S4a and S4b. Sa and Sb set the common mode for the amplifier input, and open simultaneously with S sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors Ca and Cb to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors Ca and Cb. The amplifiers are used to charge capacitors Ca and Cb to the same values originally held on Ca and Cb. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input bandwidth T/H amplifiers allow the to track and sample/hold analog inputs of high frequencies (>Nyquist). Both ADC inputs (INA+, INB+ and INA-, INB-) can be driven either differentially or single ended.

13 ANALOG INPUT N t AD N + 5-CLOCK-CYCLE LATENCY N + N + 3 N + 4 N + 5 N + 6 CLOCK INPUT t DO t CH tcl DATA OUTPUT D7A D0A N - 6 N - 5 N - 4 N - 3 N - N - N N + DATA OUTPUT D7B D0B N - 6 N - 5 N - 4 N - 3 N - N - N N + Figure 3. System Timing Diagram Match the impedance of INA+ and INA-, as well as INB+ and INB-, and set the common-mode voltage to mid supply ( DD /) for optimum performance. Analog Inputs and Reference Configurations The full-scale range of the is determined by the internally generated voltage difference between REFP ( DD / + REFIN /4) and REFN ( DD / - REFIN /4). The full-scale range for both on-chip ADCs is adjustable through the REFIN pin, which is provided for this purpose. The provides three modes of reference operation: Internal reference mode Buffered external reference mode Unbuffered external reference mode In internal reference mode, connect the internal reference output REFOUT to REFIN through a resistor (e.g., 0kΩ) or resistor-divider, if an application requires a reduced full-scale range. For stability and noise-filtering purposes, bypass REFIN with a >0nF capacitor to GND. In internal reference mode, REFOUT,, REFP, and REFN become low-impedance outputs. In buffered external reference mode, adjust the reference voltage levels externally by applying a stable and accurate voltage at REFIN. In this mode,, REFP, and REFN are outputs. REFOUT can be left open or connected to REFIN through a >0kΩ resistor. In unbuffered external reference mode, connect REFIN to GND. This deactivates the on-chip reference buffers for REFP,, and REFN. With their buffers shut down, these nodes become high-impedance inputs and can be driven through separate, external reference sources. For detailed circuit suggestions and how to drive this dual ADC in buffered/unbuffered external reference mode, see the Applications Information section. Clock Input (CLK) The s CLK input accepts a CMOS-compatible clock signal. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (<ns). In particular, sampling occurs on the rising edge of the clock signal, requiring this edge to provide lowest possible jitter. Any significant aperture jitter would limit the SNR performance of the on-chip ADCs as follows: SNR = 0 log π fin taj where f IN represents the analog input frequency and t AJ is the time of the aperture jitter. Clock jitter is especially critical for undersampling applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines. 3

14 OE OUTPUT D7A D0A OUTPUT D7B D0B HIGH-Z HIGH-Z tenable Figure 4. Output Timing Diagram t DISABLE ALID DATA ALID DATA HIGH-Z HIGH-Z The clock input operates with a voltage threshold set to DD /. Clock inputs with a duty cycle other than 50% must meet the specifications for high and low periods as stated in the Electrical Characteristics table. Table. Output Codes For Differential Inputs D IFF ER EN T IAL IN PU T O LT A G E* REF x 55/56 D IFF ER EN T IAL IN PU T +Full Scale - LSB ST RA IG HT O F FSET B INA R Y T WO S C O M PL EM EN T T/B = 0 T/B = 0 REF x /56 +LSB Bipolar Zero REF x /56 -LSB 0 - REF x 55/56 -Full Scale + LSB REF x 56/56 -Full Scale System Timing Requirements Figure 3 depicts the relationship between the clock input, analog input, and data output. The samples at the rising edge of the input clock. Output data for channels A and B is valid on the next rising edge of the input clock. The output data has an internal latency of five clock cycles. Figure 3 also determines the relationship between the input clock parameters and the valid output data on channels A and B. Digital Output Data (D0A/B D7A/B), Output Data Format Selection (T/B), Output Enable (OE) All digital outputs, D0A D7A (channel A) and D0B D7B (channel B), are TTL/CMOS-logic compatible. There is a five-clock-cycle latency between any particular sample and its corresponding output data. The output coding can either be straight offset binary or two s complement (Table ) controlled by a single pin (T/B). Pull T/B low to select offset binary and high to activate two s complement output coding. The capacitive load on the digital outputs D0A D7A and D0B D7B should be kept as low as possible (<5pF), to avoid large digital currents that could feed back into the analog portion of the, thereby degrading its dynamic performance. Using buffers on the digital outputs of the ADCs can further isolate the digital outputs from heavy capacitive loads. To further improve the dynamic performance of the, small-series resistors (e.g., 00Ω) may be added to the digital output paths close to the. Figure 4 displays the timing relationship between output enable and data output valid, as well as powerdown/wakeup and data output valid. * REF = REFP - REFN Power-Down and Sleep Modes The offers two power-save modes sleep mode (SLEEP) and full power-down (PD) mode. In sleep mode (SLEEP = ), only the reference bias circuit is active (both ADCs are disabled), and current consumption is reduced to 3.mA. To enter full power-down mode, pull PD high. With OE simultaneously low, all outputs are latched at the last value prior to power-down. Pulling OE high forces the digital outputs into a high-impedance state. Applications Information Figure 5 depicts a typical application circuit containing two single-ended-to-differential converters. The internal reference provides a DD / output voltage for levelshifting purposes. The input is buffered and then split to a voltage follower and inverter. One lowpass filter per amplifier suppresses some of the wideband noise associated with high-speed op amps. The user can select the R ISO and C IN values to optimize the filter performance, to suit a particular application. For the application in Figure 5, a R ISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The pf C IN capacitor acts as a small filter capacitor. Using Transformer Coupling An RF transformer (Figure 6) provides an excellent solution to convert a single-ended source signal to a fully differential signal, required by the for optimum performance. Connecting the center tap of the transformer to provides a DD / DC level shift to the input. Although a : transformer is shown, a stepup transformer can be selected to reduce the drive 4

15 +5 MAX408-5 LOWPASS FILTER R IS0 50Ω C IN pf INA- 600Ω 600Ω INPUT MAX Ω MAX408 LOWPASS FILTER R IS0 50Ω C IN pf INA Ω LOWPASS FILTER MAX408 R IS0 50Ω C IN pf INB Ω 600Ω INPUT MAX Ω +5 MAX408 LOWPASS FILTER R IS0 50Ω C IN pf INB Ω Figure 5. Typical Application for Single-Ended-to-Differential Conversion 5

16 T 6 IN N.C MINICIRCUITS TT 6-KK8.µF 5Ω 5Ω pf pf INA+ INA- IN MAX408 00Ω 00Ω REFP REFN kω kω R ISO 50Ω C IN pf R ISO 50Ω C IN pf INA+ INA- T 6 IN 5Ω pf INB+ IN MAX408 00Ω REFP kω kω R ISO 50Ω C IN pf INB+ N.C MINICIRCUITS TT-6-KK8.µF 5Ω pf 00Ω REFN R ISO 50Ω C IN pf INB- INB- Figure 6. Transformer-Coupled Input Drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. In general, the provides better SFDR and THD with fully differential input signals than singleended drive, especially for very high input frequencies. In differential input mode, even-order harmonics are lower as both inputs (INA+, INA- and/or INB+, INB-) are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended mode. Single-Ended AC-Coupled Input Signal Figure 7 shows an AC-coupled, single-ended application. Amplifiers like the MAX408 provide high speed, high bandwidth, low noise, and low distortion to maintain the integrity of the input signal. Figure 7. Using an Op Amp for Single-Ended, AC-Coupled Input Drive Buffered External Reference Drives Multiple ADCs Multiple-converter systems based on the are well suited for use with a common reference voltage. The REFIN pin of those converters can be connected directly to an external reference source. A precision bandgap reference like the MAX606 generates an external DC level of.048 (Figure 8), and exhibits a noise-voltage density of 50n/ Hz. Its output passes through a -pole lowpass filter (with 0Hz cutoff frequency) to the MAX450, which buffers the reference before its output is applied to a second 0Hz lowpass filter. The MAX450 provides a low offset voltage (for high gain accuracy) and a low noise level. The passive 0Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision ADC operation. 6

17 3.3 MAX kΩ 3 5 µf 0Hz LOWPASS FILTER 4 MAX Ω 00µF 0Hz LOWPASS FILTER N.C REFOUT REFIN REFP REFN N = NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 000 ADCs..µF 0 N.C REFOUT REFIN REFP REFN N = 000 Figure 8. External Buffered (MAX450) Reference Drive Using a MAX606 Bandgap Reference Unbuffered External Reference Drives Multiple ADCs Connecting each REFIN to analog ground disables the internal reference of each device, allowing the internal reference ladders to be driven directly by a set of external reference sources. Followed by a 0Hz lowpass filter and precision voltage-divider, the MAX6066 generates a DC level of.500. The buffered outputs of this divider are set to.0,.5, and.0, with an accuracy that depends on the tolerance of the divider resistors. These three voltages are buffered by the MAX45, which provides low noise and low DC offset. The individual voltage followers are connected to 0Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3n/ Hz. The.0 and.0 reference voltages set the differential full-scale range of the associated ADCs at P-P. The.0 and.0 buffers drive the ADC s internal ladder resistances between them. Note that the common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX45 matching better than 0.%, the buffers and subsequent lowpass filters can be replicated to support as many as 3 ADCs. For applications that require more than 3 matched ADCs, a voltage reference and divider string common to all converters is highly recommended. Typical QAM Demodulation Application A frequently used modulation technique in digital communications applications is quadrature amplitude modulation (QAM). Typically found in spread-spectrum-based systems, a QAM signal represents a carrier frequency modulated in both amplitude and phase. At the transmitter, modulating the baseband signal with quadrature outputs, a local oscillator followed by subsequent upconversion can generate the QAM signal. The result is an in-phase (I) and a quadrature (Q) carrier component, where the Q component is 90 phase 7

18 3.3 MAX kΩ 3.5kΩ /4 MAX45 47Ω 0µF 6.47kΩ.0 AT 8mA 330µF 6 N.C REFOUT REFIN REFP REFN N = /4 MAX Ω.5 AT 0mA 3.3 µf MAX454 POWER-SUPPLY BYPASSING. PLACE CAPACITOR AS CLOSE AS POSSIBLE TO THE OP AMP..5kΩ.5kΩ.5kΩ /4 MAX45 8 0µF 6.47kΩ 47Ω 0µF 6.47kΩ.0 AT -8mA 330µF 6 330µF 6 N.C REFOUT REFIN REFP REFN N = 3.µF 0 NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 3 ADCs. Figure 9. External Unbuffered Reference Drive with MAX45 and MAX6066 shifted with respect to the in-phase component. At the receiver, the QAM signal is divided down into its I and Q components, essentially representing the modulation process reversed. Figure 0 displays the demodulation process performed in the analog domain, using the dual matched 3.3, 8-bit ADC and the MAX45 quadrature demodulator to recover and digitize the I and Q baseband signals. Before being digitized by the, the mixed down-signal components may be filtered by matched analog filters, such as Nyquist or pulse-shaping filters, which remove unwanted images from the mixing process, thereby enhancing the overall signal-to-noise (SNR) performance and minimizing intersymbol interference. Grounding, Bypassing, and Board Layout The requires high-speed board layout design techniques. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass DD, REFP, REFN, and with two parallel ceramic capacitors and a.µf bipolar capacitor to GND. Follow the same rules to bypass the digital supply (O DD ) to OGND. Multilayer boards with separated ground and power planes produce the highest level of signal integrity. Consider the use of a split ground plane arranged to match the 8

19 MAX INA+ INA- INB+ INB- DSP POST- PROCESSING DOWNCONERTER 8 Figure 0. Typical QAM Application Using the CLK ANALOG INPUT SAMPLED DATA (T/H) T/H t AD TRACK Figure. T/H Aperture Timing physical location of the analog ground (GND) and the digital output driver ground (OGND) on the ADC s package. The two ground planes should be joined at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes, which produces optimum results. Make this connection with a low-value, surface-mount resistor (Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane if the ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns. t AJ HOLD TRACK Static Parameter Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the are measured using the best-straight-line-fit method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of LSB. A DNL error specification of less than LSB guarantees no missing codes and a monotonic transfer function. Dynamic Parameter Definitions Aperture Jitter Figure depicts the aperture jitter (t AJ ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (t AD ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure ). Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC s resolution (N-bits): SNR db[max] = 6.0 db N +.76 db 9

20 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion SINAD is computed by taking the ratio of the RMS signal to all spectral components minus the fundamental and the DC offset. Effective Number of Bits Effective number of bits (ENOB) specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: ENOB = SINAD THD = 0 log where is the fundamental amplitude, and through 5 are the amplitudes of the nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset. Intermodulation Distortion The two-tone intermodulation distortion (IMD) is the ratio expressed in decibels of either input tone to the worst third-order (or higher) intermodulation products. The individual input tone levels are at -7dB full scale and their envelope is at -db full scale. Total Harmonic Distortion THD is typically the ratio of the RMS sum of the first four harmonics of the input signal to the fundamental itself. This is expressed as: Chip Information TRANSISTOR COUNT:,60 PROCESS: CMOS 0

21 DD GND INA+ INA- T/H ADC DEC 8 Functional Diagram OUTPUT DRIERS 8 OGND O DD D7A D0A CLK CONTROL OE INB+ INB- T/H ADC DEC 8 OUTPUT 8 DRIERS D7B D0B REFERENCE T/B PD SLEEP REFOUT REFN REFP REFIN Pin-Compatible Upgrades (Sampling Speed and Resolution) 8-BIT PART 0-BIT PART SAMPLING SPEED (Msps) MAX95 MAX83 40 MAX97 MAX8 60 MAX80 00 MAX96* MAX86 40, multiplexed *Future product, please contact factory for availability.

22 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 48L,TQFP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 0 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.