MAX1208ETL PART. Maxim Integrated Products 1

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1 9-; Rev ; 8/4 EVALUATION KIT AVAILABLE -Bit, 8Msps, 3.3V ADC General Description The is a 3.3V, -bit, 8Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input stage accepts singleended or differential signals. The is optimized for low power, small size, and high dynamic performance in baseband applications. Powered from a single 3.V to 3.6V supply, the consumes only 373mW while delivering a typical signal-to-noise (SNR) performance of 68.dB at an input frequency of 3.5MHz. In addition to low operating power, the features a 3µW power-down mode to conserve power during idle periods. A flexible reference structure allows the to use the internal.48v bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±.35V to ±.5V. The provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC s internal duty-cycle equalizer (DCE). ADC conversion results are available through a -bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide.7v to 3.6V supply, allowing the to interface with various logic levels. The is available in a 6mm x 6mm x.8mm, 4-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-4 C to +85 C) temperature range. See the Pin-Compatible Versions table for a complete family of 4-bit and -bit high-speed ADCs. Applications Communication Receivers Cellular, Point-to-Point Microwave, HFC, WLAN Ultrasound and Medical Imaging Portable Instrumentation Low-Power Data Acquisition Features Excellent Dynamic Performance 68.dB/68.dB SNR at f IN = 3MHz/7MHz 89.3dBc/85.dBc SFDR at f IN = 3MHz/7MHz 3.3V Low-Power Operation 373mW (Single-Ended Clock Mode) 399mW (Differential Clock Mode) 3µW (Power-Down Mode) Differential or Single-Ended Clock Fully Differential or Single-Ended Analog Input Adjustable Full-Scale Analog Input Range: ±.35V to ±.5V Common-Mode Reference CMOS-Compatible Outputs in Two s Complement or Gray Code Data-Valid Indicator Simplifies Digital Design Data Out-of-Range Indicator Miniature, 4-Pin Thin QFN Package with Exposed Paddle Evaluation Kit Available (Order MAXEVKIT) PART ETL PART TEMP RANGE -4 C to +85 C Ordering Information PIN- PACKAGE 4 Thin QFN (6mm x 6mm x.8mm) PKG CODE T466-3 Pin-Compatible Versions SAMPLING RATE (Msps) RESOLUTION (BITS) TARGET APPLICATION MAX IF/Baseband MAX9 8 IF MAX 65 IF 8 Baseband MAX7 65 Baseband MAX6 4 Baseband Pin Configuration appears at end of data sheet. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS V DD to GND...-.3V to +3.6V OV DD to GND...-.3V to the lower of (V DD +.3V) and +3.6V INP, INN to GND...-.3V to the lower of (V DD +.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND...-.3V to the lower of (V DD +.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND...-.3V to the lower of (V DD +.3V) and +3.6V D Through D I.C., DAV, DOR to GND...-.3V to (OV DD +.3V) Continuous Power Dissipation (T A = +7 C) 4-Pin Thin QFN 6mm x 6mm x.8mm (derated 6.3mW/ C above +7 C)...5.3mW Operating Temperature Range...-4 C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note ) Resolution Bits Integral Nonlinearity INL f IN = MHz ±.65 LSB Differential Nonlinearity DNL f IN = MHz, no missing codes over temperature -.83 ±.35 LSB Offset Error V REFIN =.48V ±.5 ±.9 %FS Gain Error V REFIN =.48V ±. ±5.6 %FS ANALOG INPUT (INP, INN) Differential Input Voltage Range V DIFF Differential or single-ended inputs ±.4 V Common-Mode Input Voltage V DD / V Input Capacitance C PAR Fixed capacitance to ground (Figure 3) C SAMPLE Switched capacitance.9 CONVERSION RATE Maximum Clock Frequency f CLK 8 MHz Minimum Clock Frequency 5 MHz Data Latency Figure DYNAMIC CHARACTERISTICS (differential inputs, Note ) Small-Signal Noise Floor SSNF Input at less than -35dBFS dbfs Signal-to-Noise Ratio Signal-to-Noise and Distortion SNR SINAD f IN = 3MHz at -.5dBFS 68. f IN = 3.5MHz at -.5dBFS f IN = 7MHz at -.5dBFS 68. f IN = 3MHz at -.5dBFS 68. f IN = 3.5MHz at -.5dBFS f IN = 7MHz at -.5dBFS 67.8 pf Clock cycles db db

3 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Spurious-Free Dynamic Range Total Harmonic Distortion Second Harmonic Third Harmonic Intermodulation Distortion SFDR THD HD HD3 IMD fin = 3MHz at -.5dBFS 89.3 fin = 3.5MHz at -.5dBFS fin = 7MHz at -.5dBFS 85. fin = 3MHz at -.5dBFS -87. fin = 3.5MHz at -.5dBFS fin = 7MHz at -.5dBFS -8. fin = 3MHz at -.5dBFS -93 fin = 3.5MHz at -.5dBFS -89 fin = 7MHz at -.5dBFS fin = 3MHz at -.5dBFS fin = 3.5MHz at -.5dBFS -95. fin = 7MHz at -.5dBFS -85. fin = 68.5MHz at -7dBFS fin = 7.5MHz at -7dBFS dbc dbc dbc dbc -8. dbc Third-Order Intermodulation IM3 fin = 68.5MHz at -7dBFS fin = 7.5MHz at -7dBFS dbc Two-Tone Spurious-Free Dynamic Range SFDRTT fin = 68.5MHz at -7dBFS fin = 7.5MHz at -7dBFS 85.4 dbc Aperture Delay tad Figure 4.9 ns Aperture Jitter taj Figure 4 <. psrms Output Noise nout INP = INN = COM.5 LSBRM Overdrive Recovery Time ±% beyond full scale INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) REFOUT Output Voltage VREFOUT V COM Output Voltage VCOM VDD /.65 V Differential Reference Output VREF VREF = VREFP - VREFN.4 V Clock cycles REFOUT Load Regulation 35 mv/ma REFOUT Temperature Coefficient TCREF +5 ppm/ C REFOUT Short-Circuit Current Short to VDD sinking.4 Short to GND sourcing. BUFFERED EXTERNAL REFERENCE (REFIN driven externally; VREFIN =.48V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage VREFIN.48 V REFP Output Voltage VREFP (VDD/) + (VREFIN / 4).6 V ma 3

4 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFN Output Voltage V REFN (V DD / ) - (V REFIN / 4).38 V COM Output Voltage V COM V DD / V Differential Reference Output Voltage Differential Reference Temperature Coefficient V REF V REF = V REFP - V REFN V ±5 ppm/ C REFIN Input Resistance >5 MΩ UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V REFP, V REFN, and V COM are applied externally) COM Input Voltage V COM V DD /.65 V REFP Input Voltage V REFP - V COM.5 V REFN Input Voltage V REFN - V COM -.5 V Differential Reference Input Voltage V REF V REF = V REFP - V REFN.4 V REFP Sink Current I REFP V REFP =.6V. ma REFN Source Current I REFN V REFN =.38V. ma COM Sink Current I COM.3 ma REFP, REFN Capacitance 3 pf COM Capacitance 6 pf CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold V IH V IL CLKTYP = GND, CLKN = GND CLKTYP = GND, CLKN = GND.8 x V DD. x V DD V V Differential Input Voltage Swing CLKTYP = high.4 V P-P Differential Input Common-Mode Voltage CLKTYP = high V DD / V Input Resistance R CLK Figure 5 5 kω Input Capacitance C CLK pf DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold V IH.8 x OV DD V 4

5 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Threshold V IL. x OV DD Input Leakage Current V IH = OV DD ±5 V IL = ±5 Input Capacitance C DIN 5 pf DIGITAL OUTPUTS (D D, DAV, DOR) D D, DOR, I SINK = µa. Output Voltage Low V OL DAV, I SINK = 6µA. V µa V D D, DOR, I SOURCE = µa Output Voltage High V OH DAV, I SOURCE = 6µA OV DD -. OV DD -. Tri-State Leakage Current I LEAK (Note 3) ±5 µa D D, DOR Tri-State Output Capacitance DAV Tri-State Output Capacitance POWER REQUIREMENTS C OUT (Note 3) 3 pf C DAV (Note 3) 6 pf Analog Supply Voltage V DD V Digital Output Supply Voltage OV DD.7. Analog Supply Current Analog Power Dissipation I VDD P DISS V DD +.3V Normal operating mode, f IN = 3.5MHz at -.5dBFS, 3 CLKTYP = GND, single-ended clock Normal operating mode, f IN = 3.5MHz at -.5dBFS, CLKTYP = OV DD, differential clock 3. Power-down mode clock idle, PD = OV DD. Normal operating mode, f IN = 3.5MHz at -.5dBFS, 373 CLKTYP = GND, single-ended clock Normal operating mode, f IN = 3.5MHz at -.5dBFS, CLKTYP = OV DD, differential clock Power-down mode clock idle, PD = OV DD.3 V V ma mw 5

6 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +5 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Output Supply Current TIMING CHARACTERISTICS (Figure 6) I OVDD Normal operating mode, f IN = 3.5MHz at -.5dBFS, OV DD =.V, C L 5pF Note : Specifications +5 C guaranteed by production test, <+5 C guaranteed by design and characterization. Note : See definitions in the Parameter Definitions section. Note 3: During power-down, D D, DOR, and DAV are high impedance. Note 4: Guaranteed by design and characterization. Note 5: Digital outputs settle to V IH or V IL. 9.9 ma Power-down mode clock idle, PD = OV DD.9 µa Clock Pulse Width High t CH 6.5 ns Clock Pulse Width Low t CL 6.5 ns Data-Valid Delay t DAV C L = 5pF (Note 5) 6.4 ns Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV t SETUP C L = 5pF (Note 4, Note 5) 7.7 ns t HOLD C L = 5pF (Note 4, Note 5) 4. ns Wake-Up Time from Power-Down t WAKE V REFIN =.48V ms 6

7 Typical Operating Characteristics (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = +5 C, unless otherwise noted.) AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (89-POINT DATA RECORD) HD HD3 f CLK = 8.353MHz f IN = MHz AIN = -.57dBFS SNR = 68.dB SINAD = 68.6dB THD = dBc SFDR = 9.6dBc FREQUENCY (MHz) toc AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (89-POINT DATA RECORD) f CLK = 8.353MHz f IN = MHz A IN = -.495dBFS SNR = 68.36dB SINAD = 68.73dB THD = dBc SFDR = dBc HD HD FREQUENCY (MHz) toc AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (89-POINT DATA RECORD) HD f CLK = 8.353MHz f IN = MHz A IN = -.5dBFS SNR = 68.dB SINAD = 67.89dB THD = -8.47dBc SFDR = 85.67dBc HD3 HD FREQUENCY (MHz) toc3 AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (6,384-POINT DATA RECORD) f CLK = 8MHz f IN = MHz A IN = -7.dBFS f IN = MHz A IN = -7.4dBFS SFDR TT = 87.39dBc IMD = dBc IM3 = dBc f IN f IN x f IN + f IN toc4 AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (6,384-POINT DATA RECORD) f IN f IN f IN + f IN f CLK = 8MHz f IN = MHz A IN = -7.43dBFS f IN = 7.499MHz A IN = -7.4dBFS IMD = dBc IM3 = dBc f IN + x f IN x f IN + f IN toc FREQUENCY (MHz) FREQUENCY (MHz)..8.6 INTEGRAL NONLINEARITY toc DIFFERENTIAL NONLINEARITY toc7.4.4 INL (LSB). -. DNL (LSB) DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE 7

8 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = +5 C, unless otherwise noted.) SNR, SINAD (db) f IN 3.5MHz SNR, SINAD vs. SAMPLING RATE 63 SNR SINAD f CLK (MHz) toc8 SFDR, -THD (dbc) f IN 3.5MHz SFDR, -THD vs. SAMPLING RATE 65 SFDR -THD f CLK (MHz) toc9 POWEER DISSIPATION (mw) POWER DISSIPATION vs. SAMPLING RATE DIFFERENTIAL CLOCK f IN 3.5MHz C L 5pF 5 ANALOG + DIGITAL POWER ANALOG POWER f CLK (MHz) toc SNR, SINAD (db) f IN 7MHz SNR, SINAD vs. SAMPLING RATE SNR SINAD f CLK (MHz) toc SFDR, -THD (dbc) f IN 7MHz SFDR, -THD vs. SAMPLING RATE SFDR -THD f CLK (MHz) toc POWEER DISSIPATION (mw) POWER DISSIPATION vs. SAMPLING RATE DIFFERENTIAL CLOCK f IN 7MHz C L 5pF ANALOG + DIGITAL POWER ANALOG POWER f CLK (MHz) toc3 SNR, SINAD (db) SNR, SINAD vs. ANALOG INPUT FREQUENCY f CLK 8MHz SNR SINAD toc4 SFDR, -THD (dbc) SFDR, -THD vs. ANALOG INPUT FREQUENCY f CLK 8MHz SFDR -THD toc5 POWER DISSIPATION (mw) POWER DISSIPATION vs. ANALOG INPUT FREQUENCY DIFFERENTIAL CLOCK f CLK 8MHz C L = 5pF ANALOG + DIGITAL POWER ANALOG POWER toc ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) 8

9 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = +5 C, unless otherwise noted.) SNR, SINAD (db) SNR, SINAD vs. ANALOG INPUT AMPLITUDE 75 f CLK = 8.37MHz 7 f IN = 3.557MHz SNR SINAD ANALOG INPUT AMPLITUDE (dbfs) toc7 SFDR, -THD (dbc) SFDR, -THD vs. ANALOG INPUT AMPLITUDE 9 f CLK = 8.37MHz 85 f IN = 3.557MHz SFDR -THD ANALOG INPUT AMPLITUDE (dbfs) toc8 POWER DISSIPATION (mw) POWER DISSIPATION vs. ANALOG INPUT AMPLITUDE DIFFERENTIAL CLOCK f CLK = 8.37MHz f IN = 3.557MHz C L 5pF ANALOG + DIGITAL POWER ANALOG POWER ANALOG INPUT AMPLITUDE (dbfs) toc9 SNR, SINAD (db) SNR, SINAD vs. ANALOG POWER-INPUT VOLTAGE 7 f CLK = MHz 69 f IN = 3.399MHz SNR SINAD V DD (V) toc SFDR, -THD (dbc) SFDR, -THD vs. ANALOG POWER-INPUT VOLTAGE f CLK = MHz f IN = 3.399MHz 65 SFDR -THD V DD (V) toc POWER DISSIPATION (mw) POWER DISSIPATION vs. ANALOG POWER-INPUT VOLTAGE DIFFERENTIAL CLOCK f CLK = MHz f IN = 3.399MHz C L 5pF 5 ANALOG + DIGITAL POWER ANALOG POWER V DD (V) toc SNR, SINAD (db) SNR, SINAD vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE 7 f CLK = MHz 69 f IN = 3.399MHz SNR 6 SINAD OV DD (V) toc3 SFDR, -THD (dbc) SFDR, -THD vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE f CLK = MHz 95 f IN = 3.399MHz SFDR -THD OV DD (V) toc4 SFDR, -THD (dbc) POWER DISSIPATION vs. OUTPUT-DRIVER POWER-INPUT VOLTAGE 55 DIFFERENTIAL CLOCK 5 f CLK = MHz f IN = 3.399MHz 45 C L 5pF ANALOG + DIGITAL POWER ANALOG POWER OV DD (V) toc5 9

10 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = +5 C, unless otherwise noted.) SNR, SINAD (db) SNR, SINAD vs. TEMPERATURE 7 f CLK = 8.37MHz 69 f IN = MHz SNR 6 SINAD TEMPERATURE ( C) toc6 SFDR, -THD (dbc) SFDR, -THD vs. TEMPERATURE 95 f CLK = 8.37MHz 93 f IN = MHz SFDR 77 -THD TEMPERATURE ( C) toc7 ANALOG POWER DISSIPATION (mw) ANALOG POWER DISSIPATION vs. TEMPERATURE DIFFERENTIAL CLOCK f CLK = 8.37MHz f IN = MHz TEMPERATURE ( C) toc8 OFFSET ERROR (%FS) OFFSET ERROR vs. TEMPERATURE.5 V REFIN =.48V TEMPERATURE ( C) toc9 GAIN ERROR (%FS) GAIN ERROR vs. TEMPERATURE 3 V REFIN =.48V TEMPERATURE ( C) toc3

11 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.V, GND =, REFIN = REFOUT (internal reference), V IN = -.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK = 8MHz (5% duty cycle), T A = +5 C, unless otherwise noted.) VREFOUT (V) REFERENCE OUTPUT VOLTAGE LOAD REGULATION C C C I REFOUT SINK CURRENT (ma) toc3 VREFOUT (V) REFERENCE OUTPUT VOLTAGE SHORT-CIRCUIT PERFORMANCE +85 C +5 C -4 C I REFOUT SINK CURRENT (ma) toc3 VREFOUT (V) REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE TEMPERATURE ( C) toc33 VOLTAGE (V) REFP, COM, REFN LOAD REGULATION V REFP V COM. V REFN.5 INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE - - SINK CURRENT (ma) toc34 VOLTAGE (V) REFP, COM, REFN SHORT-CIRCUIT PERFORMANCE V COM V REFP V REFN. INTERNAL REFERENCE.5 MODE AND BUFFERED EXTERNAL REFERENCE MODE SINK CURRENT (ma) toc35

12 PIN NAME FUNCTION REFP REFN 3 COM 4, 7, 6, 35 GND 5 INP Positive Analog Input Positive Reference I/O. The full-scale analog input range is ±(V REFP - V REFN ). Bypass REFP to GND with a capacitor. Connect a µf capacitor in parallel with a µf capacitor between REFP and REFN. Place the µf REFP to REFN capacitor as close to the device as possible on the same side of the printed circuit (PC) board. Negative Reference I/O. The full-scale analog input range is ±(V REFP - V REFN ). Bypass REFN to GND with a capacitor. Connect a µf capacitor in parallel with a µf capacitor between REFP and REFN. Place the µf REFP to REFN capacitor as close to the device as possible on the same side of the PC board. Common-Mode Voltage I/O. Bypass COM to GND with a.µf capacitor. Place the.µf COM to GND capacitor as close to the device as possible. This.µF capacitor can be placed on the opposite side of the PC board and connected to the through a via. 6 INN Negative Analog Input 8 DCE 9 CLKN CLKP CLKTYP Ground. Connect all ground pins and EP together. Pin Description Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OV DD or V DD ) to enable the internal duty-cycle equalizer. Negative Clock Input. In differential clock input mode (CLKTYP = OV DD or V DD ), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. Positive Clock Input. In differential clock input mode (CLKTYP = OV DD or V DD ), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND. Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OV DD or V DD to define the differential clock input. 5, 36 V DD Analog Power Input. Connect V DD to a 3.V to 3.6V power supply. Bypass V DD to GND with a parallel capacitor combination of.µf and. Connect all V DD pins to the same potential. 7, 34 OV DD Output-Driver Power Input. Connect OV DD to a.7v to V DD power supply. Bypass OV DD to GND with a parallel capacitor combination of.µf and. 8 DOR Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6). 9 D CMOS Digital Output, Bit (MSB) D CMOS Digital Output, Bit D9 CMOS Digital Output, Bit 9 D8 CMOS Digital Output, Bit 8 3 D7 CMOS Digital Output, Bit 7 4 D6 CMOS Digital Output, Bit 6 5 D5 CMOS Digital Output, Bit 5 6 D4 CMOS Digital Output, Bit 4 7 D3 CMOS Digital Output, Bit 3

13 PIN NAME FUNCTION 8 D CMOS Digital Output, Bit 9 D CMOS Digital Output, Bit 3 D CMOS Digital Output, Bit ( LSB) 3, 3 I.C. Internally Connected. Leave I.C. unconnected. 33 DAV Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the output data into an external back-end digital circuit. 37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. 38 REFOUT 39 REFIN 4 G/T EP Pin Description (continued) Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a capacitor. Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a capacitor. In these modes, V REFP - V REFN = V REFIN /. For unbuffered external reference-mode operation, connect REFIN to GND. Output Format Select Input. Connect G/T to GND for the two s complement digital output format. Connect G/T to OV DD or V DD for the Gray code digital output format. Exposed Paddle. The relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane. T/H + Σ FLASH ADC DAC INP INN T/H STAGE STAGE STAGE 9 STAGE END OF PIPE DIGITAL ERROR CORRECTION D D OUTPUT DRIVERS D D Figure. Pipeline Architecture Stage Blocks 3

14 CLKP CLKN DCE CLKTYP INP INN REFOUT REFIN REFP COM REFN CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER T/H -BIT PIPELINE ADC REFERENCE SYSTEM DEC OUTPUT DRIVERS POWER CONTROL AND BIAS CIRCUITS V DD GND OV DD D D DAV DOR G/T PD INP INN BOND WIRE INDUCTANCE.5nH BOND WIRE INDUCTANCE.5nH V DD V DD C PAR pf C PAR pf *C SAMPLE.9pF *C SAMPLE.9pF Figure. Simplified Functional Diagram Detailed Description The uses a -stage, fully differential, pipelined architecture (Figure ) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half-clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure shows the functional diagram. Input Track-and-Hold (T/H) Circuit Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies up to 7MHz and supports a common-mode input voltage of V DD / ±.5V. The sampling clock controls the ADC s switched-capacitor T/H architecture (Figure 3), allowing the analog input signal to be stored as charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these SAMPLING CLOCK *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: R SAMPLE = Figure 3. Simplified Input Track-and-Hold Circuit f CLK x C SAMPLE capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (V DD / ). The provides the optimum common-mode voltage of V DD / through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures,, and. Reference Output (REFOUT) An internal bandgap reference is the basis for all the internal voltages and bias currents used in the. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires ms to power up and settle when power is applied to the or when PD transitions from high to low. REFOUT has approximately 7kΩ to GND when the is in power-down. The internal bandgap reference and its buffer generate V REFOUT to be.48v. The reference temperature coefficient is typically +5ppm/ C. Connect an external bypass capacitor from REFOUT to GND for stability. 4

15 CLKP CLKN ANALOG INPUT SAMPLED DATA t AD t AJ T/H TRACK HOLD TRACK HOLD TRACK HOLD TRACK HOLD Figure 4. T/H Aperture Timing REFOUT sources up to.ma and sinks up to.ma for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits I REFOUT to a.ma source current when shorted to GND and a.4ma sink current when shorted to V DD. Analog Inputs and Reference Configurations The full-scale analog input range is adjustable from ±.35V to ±.5V with a commonmode input range of V DD / ±.5V. The provides three modes of reference operation. The voltage at REFIN (V REFIN ) sets the reference operation mode (Table ). To operate the with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD /, V REFP = V DD / + V REFIN / 4, V REFN = V DD / - V REFIN / 4. The REFIN input impedance is very large (>5MΩ). When driving REFIN through a resistive Table. Reference Modes V REFIN 35% V REFOUT to % V REFOUT.7V to.3v <.4V divider, use resistances kω to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the REFOUT. In buffered external reference mode, apply a stable.7v to.3v source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD /, V REFP = V DD / + V REFIN / 4, and V REFN = V DD / - V REFIN / 4. To operate the in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive V COM to V DD / ±5%, and drive REFP and REFN such that V COM = (V REFP + V REFN /. The full-scale analog input range is ±(V REFP - V REFN ). REFERENCE MODE Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is ±V REFIN / : V COM = V DD / V REFP = V DD / + V REFIN / 4 V REFN = V DD / - V REFIN / 4 Buffered External Reference Mode. Apply an external.7v to.3v reference voltage to REFIN. The full-scale analog input range is ±V REFIN / : V COM = V DD / V REFP = V DD / + V REFIN / 4 V REFN = V DD / - V REFIN / 4 Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is ±(V REFP - V REFN ). 5

16 All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a.µf capacitor to GND. Bypass REFP and REFN each with a capacitor to GND. Bypass REFP to REFN with a µf capacitor in parallel with a µf capacitor. Place the µf capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a capacitor. For detailed circuit suggestions, see Figures 3 and 4. Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP) The accepts both differential and singleended clock inputs. For single-ended clock-input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock-input operation, connect CLKTYP to OV DD or V DD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the is powered down (Figure 5). Low clock jitter is required for the specified SNR performance of the. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: SNR = log π fin tj where f IN represents the analog input frequency and t J is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 68.dB of SNR with an input frequency of 3.5MHz, the system must have less than.9ps of clock jitter. Clock Duty-Cycle Equalizer (DCE) Enable the clock duty-cycle equalizer by connecting DCE to OV DD or V DD. Disable the clock duty-cycle equalizer by connecting DCE to GND. V DD CLKP CLKN GND S L S H kω kω S L S H kω kω Figure 5. Simplified Clock Input Circuit DUTY-CYCLE EQUALIZER SWITCHES S _ AND S _ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S _ ARE OPEN IN SINGLE-ENDED CLOCK MODE. The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the requires approximately clock cycles to acquire and lock to new clock frequencies. Disabling the clock duty-cycle equalizer reduces the analog supply current by.5ma. System Timing Requirements Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN). 6

17 (V REFP - V REFN ) (V REFN - V REFP ) CLKN CLKP DAV D D DOR DIFFERENTIAL ANALOG INPUT (INP INN) N+4 N+5 N+3 N+6 N-3 N- N- N N+ N+ N+7 N+9 N+8 t AD t DAV t CL t CH t SETUP t HOLD N-3 N- N- N N+ N+ N+3 N+4 N+5 N+6 N+7 N+8 N CLOCK-CYCLE DATA LATENCY t SETUP thold Figure 6. System Timing Diagram Data-Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6). The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is the inverse of the signal at CLKP delayed by 6.8ns. With the duty-cycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D D and DOR are valid from 7.7ns before the rising edge of DAV to 4.ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.4ns (t DAV ) delay from the falling edge of CLKP. DAV is high impedance when the is in power-down (PD = high). DAV is capable of sinking and sourcing 6µA and has three times the drive strength of D D and DOR. DAV is typically used to latch the output data into an external backend digital circuit. Keep the capacitive load on DAV as low as possible (<5pF) to avoid large digital currents feeding back into the analog portion of the and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (V REFP - V REFN ) to (V REFN - V REFP ). Signals outside this valid differential range cause DOR to assert high as shown in Table and Figure 6. DOR is synchronized with DAV and transitions along with the output data D D. There is an 8.5 clockcycle latency in the DOR function as with the output data (Figure 6). DOR is high impedance when the is in power-down (PD = high). DOR enters a high-impedance state within ns after the rising edge of PD and becomes active ns after PD s falling edge. Digital Output Data (D D), Output Format (G/T) The provides a -bit, parallel, tri-state output bus. D D and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. The output data format is either Gray code or two s complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two s complement. See Figure 8 for a binary-to-gray and Gray-tobinary code-conversion example. The following equations, Table, Figure 7, and Figure 8 define the relationship between the digital output and the analog input: CODE 48 VINP VINN = ( VREFP VREFN) 496 for Gray code (G/T = ) 7

18 VINP VINN = ( VREFP VREFN) CODE 496 for two s complement (G/T = ) where CODE is the decimal equivalent of the digital output code as shown in Table. Digital outputs D D are high impedance when the is in power-down (PD = high). D D transition high ns after the rising edge of PD and become active ns after PD s falling edge. Table. Output Codes vs. Input Voltage Keep the capacitive load on the digital outputs D D as low as possible (<5pF) to avoid large digital currents feeding back into the analog portion of the and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the from heavy capacitive loading. To improve the dynamic performance of the, add Ω resistors in series with the digital outputs close to the. Refer to the MAX evaluation kit schematic for an example of the digital outputs driving a digital buffer through Ω series resistors. Power-Down Input (PD) The has two power modes that are controlled with the power-down digital input (PD). With PD low, the GRAY CODE OUTPUT CODE (G/T = ) TWO S-COMPLEMENT OUTPUT CODE (G/T = ) BINARY D D DOR HEXADECIMAL EQUIVALENT OF D D DECIMAL EQUIVALENT OF D D (CODE ) BINARY D D DOR HEXADECIMAL EQUIVALENT OF D D DECIMAL EQUIVALENT OF D D (CODE ) x x7ff +47 V INP - V INN V REFP =.6V V REFN =.38V ( ) >+.35V (DATA OUT OF RANGE) x x7ff V x x7fe V xc3 +5 x + +.V xc +49 x + +.5V xc +48 x +.V x4 +47 xfff - -.5V x4 +46 xffe - -.V x + x V x x V x x8-48 <-.4V (DATA OUT OF RANGE) 8

19 TWO'S COMPLEMENT OUTPUT CODE (LSB) x7ff x7fe x7fd x x xfff x83 x8 x8 x8 x V REF LSB = 496 V REF = V REFP - V REFN V REF V REF GRAY OUTPUT CODE (LSB) x8 x8 x83 xc xc x4 x x3 x x x V REF LSB = 496 V REF = V REFP - V REFN V REF V REF DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 7. Two s Complement Transfer Function (G/T = ) is in normal operating mode. With PD high, the is in power-down mode. The power-down mode allows the to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to µa, and the digital supply current reduces to.9µa. The following list shows the state of the analog inputs and digital outputs in power-down mode: INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). REFOUT has approximately 7kΩ to GND. REFP, COM, and REFN go high impedance with respect to V DD and GND, but there is an internal 4kΩ resistor between REFP and COM, as well as an internal 4kΩ resistor between REFN and COM. D D, DOR, and DAV go high impedance. CLKP and CLKN go high impedance (Figure 5). Figure 8. Gray Code Transfer Function (G/T = ) The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically ms with the recommended capacitor array (Figure 3). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. Applications Information Using Transformer Coupling In general, the provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure ) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the for optimum performance. Connecting the center tap of the transformer to COM provides a V DD / DC level shift to the input. Although a : transformer is shown, a 9

20 BINARY-TO-GRAY CODE CONVERSION ) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D D7 D3 D BINARY BIT POSITION GRAY CODE GRAY-TO-BINARY CODE CONVERSION ) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D D7 D3 D BIT POSITION GRAY CODE BINARY ) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAY X = BINARY X + BINARY X + ) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARY X = BINARY X+ + GRAY X WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: TABLE BELOW) AND X IS THE BIT POSITION: GRAY = BINARY + BINARY GRAY = + GRAY = BINARY = BINARY + GRAY BINARY = + BINARY = D D7 D3 D BIT POSITION D D7 D3 D BIT POSITION + BINARY GRAY CODE + GRAY CODE BINARY 3) REPEAT STEP UNTIL COMPLETE: GRAY 9 = BINARY 9 + BINARY GRAY 9 = + GRAY 9 = 3) REPEAT STEP UNTIL COMPLETE: BINARY 9 = BINARY + GRAY 9 BINARY 9 = + BINARY 9 = D D7 D3 D BIT POSITION D D7 D3 D BIT POSITION + BINARY GRAY CODE + GRAY CODE BINARY 4) THE FINAL GRAY CODE CONVERSION IS: 4) THE FINAL BINARY CONVERSION IS: D D7 D3 D BIT POSITION D D7 D3 D BIT POSITION BINARY GRAY CODE GRAY CODE BINARY EXCLUSIVE OR TRUTH TABLE A B Y = A + B Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion

21 V IN N.C. T MINICIRCUITS TT-6 OR T-T 4.9Ω pf.µf 4.9Ω INP COM INN V IN MAX48 Ω Ω 4.9Ω 4.9Ω 5.6pF.µF INP COM pf INN 5.6pF Figure. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist Figure. Single-Ended, AC-Coupled Input Drive step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure is good for frequencies up to Nyquist (f CLK / ). The circuit of Figure converts a single-ended input signal to fully differential just as Figure. However, Figure utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent 75Ω termination to the signal source. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two Ω resistors in series with the analog inputs allow high IF input frequencies. These Ω resistors can be replaced with low-value resistors to limit the input bandwidth. Single-Ended AC-Coupled Input Signal Figure shows an AC-coupled, single-ended input application. The MAX48 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Ω* V IN T 6 75Ω.5% T 6 Ω.% 5.6pF INP N.C. 5 N.C. 5 N.C. COM 3 4 MINICIRCUITS ADT-WT 75Ω.5% 3 4 MINICIRCUITS ADT-WT Ω.%.µF Ω* INN *Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH. 5.6pF Figure. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist

22 +3.3V MAX69EUK 5.48V 6.kΩ µf 3 NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING 5mA AND SINKING 3mA OF OUTPUT CURRENT. +3.3V 5 MAX Ω µf 6V.48V 33µF 6V +3.3V.µF V DD REFP 38 REFOUT REFN 39 REFIN COM GND +3.3V.µF 3 µf* µf.µf.47kω *PLACE THE µf REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. 38 REFOUT V DD REFP µf* µf REFN 39 REFIN GND COM 3.µF Figure 3. External Buffered Reference Driving Multiple ADCs Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >5MΩ. Figure 3 uses the MAX69EUK precision.48v reference as a common reference for multiple converters. The.48V output of the MAX69 passes through a one-pole, Hz lowpass filter to the MAX43. The MAX43 buffers the.48v reference and provides additional Hz lowpass filtering before its output is applied to the REFIN input of the.

23 +3.3V 3.V MAX69EUK kΩ % kω % V 5 MAX Ω µf 6V.57V 33µF 6V µf µf* +3.3V.µF V DD REFP REFOUT 38.47µF 6.7kΩ % 6.7kΩ % kω % kω % kω % V V 5 MAX kΩ 47Ω µf 6V MAX43.47kΩ 47Ω µf 6V.649V 33µF 6V.4V 33µF 6V µf REFN 3 COM REFIN 39 GND.µF +3.3V.µF REFP 38 REFOUT µf* REFN V DD.47kΩ *PLACE THE µf REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE..µF 3 COM GND REFIN 39 Figure 4. External Unbuffered Reference Driving Multiple ADCs Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, and allows REFP, REFN, and COM to be driven directly by a set of external reference sources. Figure 4 uses the MAX69EUK3 precision 3.V reference as a common reference for multiple converters. A five-component resistive divider chain follows the MAX69 voltage reference. The.47µF capacitor along this chain creates a Hz lowpass filter. Three MAX43 operational amplifiers buffer taps along this resistor chain providing.57v,.649v, and.4v to the s REFP, COM, and REFN reference inputs, 3

24 respectively. The feedback around the MAX43 op amps provides additional Hz lowpass filtering. The.57V and.4v reference voltages set the full-scale analog input range to ±.6V. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down. Grounding, Bypassing, and Board Layout The requires high-speed board layout design techniques. Refer to the MAX evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass V DD to GND with a ceramic capacitor in parallel with a.µf ceramic capacitor. Bypass OV DD to GND with a ceramic capacitor in parallel with a.µf ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All GNDs and the exposed backside paddle must be connected to the same ground plane. The relies on the exposed backside paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 9 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX evaluation kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of LSB. A DNL error specification of less than LSB guarantees no missing codes and a monotonic transfer function. For the, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale transition occurs at.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale transition occurs at.5 LSBs below positive full scale, and the negative full-scale transition occurs at.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Small-Signal Noise Floor (SSNF) Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to for application notes on thermal + quantization noise floor. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC s resolution (N bits): SNR [max] = 6. N

25 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD HD7), and the DC offset. Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: Single-Tone Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: THD ENOB = log SINAD 76. = 6. V + V3 + V4 + V5 + V6 + V7 V where V is the fundamental amplitude, and V through V 7 are the amplitudes of the nd- through 7th-order harmonics (HD HD7). Intermodulation Distortion (IMD) IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: IMD = log VIM + VIM VIM3 + VIM4 V + V The fundamental input tone amplitudes (V and V ) are at -7dBFS. Fourteen intermodulation products (V IM _) are used in the IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where f IN and f IN are the fundamental input tone frequencies: Second-order intermodulation products: f IN + f IN, f IN - f IN Third-order intermodulation products: x f IN - f IN, x f IN - f IN, x f IN + f IN, x f IN + f IN Fourth-order intermodulation products: 3 x f IN - f IN, 3 x f IN - f IN, 3 x f IN + f IN, 3 x f IN + f IN Fifth-order intermodulation products: 3 x f IN - x f IN, 3 x f IN - x f IN, 3 x f IN + x f IN, 3 x f IN + x f IN Third-Order Intermodulation (IM3) IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f IN and f IN. The individual input tone levels are at -7dBFS. The thirdorder intermodulation products are x f IN - f IN, x f IN - f IN, x f IN + f IN, x f IN + f IN. Two-Tone Spurious-Free Dynamic Range (SFDR TT ) SFDR TT represents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic. Aperture Delay The samples data on the falling edge of its sampling clock. In actuality, there is a small delay between the falling edge of the sampling clock and the actual sampling instant. Aperture delay (t AD ) is the time defined between the falling edge of the sampling clock and the instant when an actual sample is taken (Figure 4). Aperture Jitter Figure 4 depicts the aperture jitter (t AJ ), which is the sample-to-sample variation in the aperture delay. 5