PART. Maxim Integrated Products 1

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1 9-343; Rev ; /4 2-Bit, 9Msps, 3.3V ADC General Description The is a 3.3V, 2-bit, 9Msps analog-to-digital converter (ADC) featuring a fully differential wideband track-and-hold (T/H) input amplifier, driving a low-noise internal quantizer. The analog input accepts single-ended or differential signals. The is optimized for low power, small size, and high dynamic performance. Excellent dynamic performance is maintained from baseband to input frequencies of 7MHz and beyond, making the ideal for intermediate frequency (IF) sampling applications. Powered from a single 3.3V supply, the consumes only 492mW while delivering a typical 68.4dB signal-to-noise ratio (SNR) performance at a 7MHz input frequency. In addition to low operating power, the features a 63µW power-down mode to conserve power during idle periods. A flexible reference structure allows the to use the internal 2.48V bandgap reference or accept an externally applied reference. The reference structure allows the full-scale analog input range to be adjusted from ±.3V to ±.V. The provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The supports either a single-ended or differential input clock drive. The internal clock duty-cycle equalizer accepts a wide range of clock duty cycles. Analog-to-digital conversion results are available through a 2-bit, parallel, CMOS-compatible output bus. The digital output format is pin selectable to be either two s complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate digital power input accepts a wide.7v to 3.6V supply allowing the to interface with various logic levels. The is available in a 6mm x 6mm x.8mm, 4-pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-4 C to +8 C) temperature range. See the Pin-Compatible Versions table for a complete family of 4-bit and 2-bit high-speed ADCs. Applications IF and Baseband Communication Receivers Cellular, Point-to-Point Microwave, HFC Medical Imaging Including Positron Emission Tomography (PET) Video Imaging Portable Instrumentation Low-Power Data Acquisition Features Direct IF Sampling Up to 4MHz Excellent Dynamic Performance 7.9dB/68.4dB SNR at fin = 3MHz/7MHz 89.dBc/76.2dBc SFDR at fin = 3MHz/7MHz -7.dBFS Small-Signal Noise Floor 3.3V Low-Power Operation 46mW (Single-Ended Clock Mode) 492mW (Differential Clock Mode) 63µW (Power-Down Mode) Fully Differential or Single-Ended Analog Input Adjustable Full-Scale Analog Input Range: ±.3V to ±.V Common-Mode Reference CMOS-Compatible Outputs in Two s Complement or Gray Code Data-Valid Indicator Simplifies Digital Design Data Out-of-Range Indicator Miniature 6mm x 6mm x.8mm 4-Pin Thin QFN Package with Exposed Paddle Evaluation Kit Available (Order MAX2EVKIT) Ordering Information PART* PIN-PACKAGE PKG CODE ETL 4 Thin QFN T466-3 ETL+ 4 Thin QFN T Denotes lead-free package. *All devices are specified over the -4 C to +8 C operating range. PART Pin-Compatible Versions SAMPLING RATE (Msps) RESOLUTION (BITS) Pin Configuration appears at end of data sheet. TARGET APPLICATION MAX2 9 4 IF/Baseband MAX IF/Baseband MAX IF/Baseband 9 2 IF/Baseband MAX IF MAX2 6 2 IF MAX Baseband MAX Baseband MAX Baseband Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS V DD to GND...-.3V to +3.6V OV DD to GND...-.3V to the lower of (V DD +.3V) and +3.6V INP, INN to GND...-.3V to the lower of (V DD +.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND...-.3V to the lower of (V DD +.3V) and +3.6V CLKP, CLKN, CLKTYP, G / T, DCE, PD to GND...-.3V to the lower of (V DD +.3V) and +3.6V D D, I.C., DAV, DOR to GND...-.3V to (OV DD +.3V) Continuous Power Dissipation (T A = +7 C) 4-Pin Thin QFN 6mm x 6mm x.8mm (derated 26.3mW/ C above +7 C)...2.3mW Operating Temperature Range...-4 C to +8 C Junction Temperature...+ C Storage Temperature Range...-6 C to + C Lead Temperature (soldering s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, (% duty cycle), T A = -4 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 2) Resolution 2 Bits Integral Nonlinearity INL f IN = 3MHz -.7 ± LSB Differential Nonlinearity DNL f IN = 3M H z, no m i ssi ng codes over tem per atur e -. ± LSB Offset Error V REFIN = 2.48V ±. ±.8 %FS Gain Error V REFIN = 2.48V ±.6 ±4.9 %FS ANALOG INPUT (INP, INN) Differential Input Voltage Range V DIFF Differential or single-ended inputs ±.24 V Common-Mode Input Voltage V DD / 2 V Input Capacitance C PAR Fixed capacitance to ground 2 (Figure 3) C SAMPLE Switched capacitance 4. CONVERSION RATE Maximum Clock Frequency f CLK 9 MHz Minimum Clock Frequency MHz pf Data Latency Figure 6 8. Clock cycles DYNAMIC CHARACTERISTICS (Differential Inputs) (Note 2) Small-Signal Noise Floor SSNF Input at less than -3dBFS -7. dbfs f IN = 3MHz at -.dbfs (Note 3) Signal-to-Noise Ratio SNR f IN = 7MHz at -.dbfs 7.4 db f IN = 7MHz at -.dbfs (Note 3) f IN = 3MHz at -.dbfs (Note 3) Signal-to-Noise and Distortion SINAD f IN = 7MHz at -.dbfs 7. db f IN = 7MHz at -.dbfs (Note 3)

3 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, (% duty cycle), T A = -4 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Spurious-Free Dynamic Range Total Harmonic Distortion Second Harmonic Third Harmonic SFDR THD HD2 HD3 f IN = 3MHz at -.dbfs (Note 3) f IN = 7MHz at -.dbfs 83. f IN = 7MHz at -.dbfs (Note 3) f IN = 3MHz at -.dbfs (Note 3) f IN = 7MHz at -.dbfs -8.2 f IN = 7MHz at -.dbfs (Note 3) f IN = 3MHz at -.dbfs f IN = 7MHz at -.dbfs -9.3 f IN = 7MHz at -.dbfs f IN = 3MHz at -.dbfs f IN = 7MHz at -.dbfs f IN = 7MHz at -.dbfs dbc dbc dbc dbc Intermodulation Distortion IMD f IN = 68.MHz at -7dBFS f IN2 = 7.MHz at -7dBFS f IN = 72.MHz at -7dBFS f IN2 = 77.MHz at -7dBFS dbc Third-Order Intermodulation IM3 f IN = 68.MHz at -7dBFS f IN2 = 7.MHz at -7dBFS f IN = 72.MHz at -7dBFS f IN2 = 77.MHz at -7dBFS dbc Two-Tone Spurious Free Dynamic Range SFDR TT f IN = 68.MHz at -7dBFS f IN2 = 7.MHz at -7dBFS f IN = 72.MHz at -7dBFS f IN2 = 77.MHz at -7dBFS Aperture Delay t AD Figure 4.2 ns Aperture Jitter t AJ Figure 4 <.2 ps RMS Output Noise n OUT INP = INN = COM.36 LSB RMS Overdrive Recovery Time ±% beyond full scale INTERNAL REFERENCE (REFIN = REFOUT; V REFP, V REFN, and V COM are generated internally) REFOUT Output Voltage V REFOUT V COM Output Voltage V COM V DD / 2.6 V Differential-Reference Output Voltage V REF V REF = V REFP - V REFN = V REFIN x 3/4.36 V dbc Clock cycles REFOUT Load Regulation -.ma < I REFOUT <.ma 3 mv/ma REFOUT Temperature Coefficient TC REF + ppm/ C REFOUT Short-Circuit Current Short to V DD, sinking.24 Short to GND, sourcing 2. ma 3

4 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, (% duty cycle), T A = -4 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS BUFFERED EXTERNAL REFERENCE (REFIN driven externally; V REFIN = 2.48V, V REFP, V REFN, and V COM are generated internally) REFIN Input Voltage V REFIN 2.48 V REFP Output Voltage V REFP (V DD / 2) + (V REFIN x 3/8) 2.48 V REFN Output Voltage V REFN (V DD / 2) - (V REFIN x 3/8).882 V COM Output Voltage V COM V DD / V Differential-Reference Output Voltage V REF V REF = V REFP - V REFN = V REFIN x 3/ V Differential-Reference Temperature Coefficient ±2 ppm/ C REFIN Input Resistance > MΩ UNBUFFERED EXTERNAL REFERENCE (REFIN = GND; V REFP, V REFN, and V COM are applied externally) COM Input Voltage V COM V DD / 2.6 V REFP Input Voltage V REFP - V COM V REFN Input Voltage V REFN - V COM V D i ffer enti al - Refer ence Inp ut V ol tag e V REF V REF = V REFP - V REFN = V REFIN x 3/4.36 V REFP Sink Current I REFP V REFP = 2.48V.4 ma REFN Source Current I REFN V REFN =.882V. ma COM Sink Current I COM V COM =.6V. ma REFP, REFN Capacitance 3 pf COM Capacitance 6 pf CLOCK INPUTS (CLKP, CLKN) Single-Ended-Input High Threshold V IH CLKTYP = GND, CLKN = GND.8 x V DD V Single-Ended-Input Low Threshold V IL CLKTYP = GND, CLKN = GND.2 x V DD V Differential Input Voltage Swing CLKTYP = high.4 V P-P Differential Input Common-Mode Voltage CLKTYP = high V DD / 2 V Input Resistance R CLK Figure kω Input Capacitance C CLK 2 pf DIGITAL INPUTS (CLKTYP, DCE, G / T, PD) Input High Threshold V IH.8 x OV DD V Input Low Threshold V IL.2 x OV DD V Input Leakage Current V IH = OV DD ± V IL = ± µa Input Capacitance C DIN pf 4

5 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, (% duty cycle), T A = -4 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL OUTPUTS (D D, DAV, DOR) D D, DOR, I SINK = 2µA.2 Output-Voltage Low V OL DAV, I SINK = 6µA.2 D D, DOR, I SOURCE = 2µA Output-Voltage High V OH DAV, I SOURCE = 6µA OV DD -.2 OV DD -.2 Tri-State Leakage Current I LEAK (Note 4) ± µa D D, DOR Tri-State Output Capacitance DAV Tri-State Output Capacitance POWER REQUIREMENTS C OUT (Note 4) 3 pf C DAV (Note 4) 6 pf Analog Supply Voltage V DD V Digital Output Supply Voltage OV DD.7.8 V DD +.3V V V V Normal operating mode, f IN = 7MHz at -.dbfs CLKTYP = GND, single-ended clock 4 Analog Supply Current Analog Power Dissipation I VDD P DISS Normal operating mode, f IN = 7MHz at -.dbfs CLKTYP = OV DD, differential clock Power-down mode clock idle PD = OV DD.22 Normal operating mode, f IN = 7MHz at -.dbfs CLKTYP = GND, single-ended clock Normal operating mode, f IN = 7MHz at -.dbfs CLKTYP = OV DD, differential clock Power-down mode clock idle PD = OV DD Digital Output Supply Current I OVDD Normal operating mode, f IN = 7MHz at -.dbfs, C L pf 9.9 ma Power-down mode clock idle PD = OV DD. µa ma mw

6 ELECTRICAL CHARACTERISTICS (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, (% duty cycle), T A = -4 C to +8 C, unless otherwise noted. Typical values are at T A = +2 C.) (Note ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TIMING CHARACTERISTICS (Figure 6) Clock Pulse-Width High t CH.26 ns Clock Pulse-Width Low t CL.26 ns Data-Valid Delay t DAV C L pf (Note ) 6.8 ns Data Setup Time Before Rising Edge of DAV t SETUP C L pf (Notes, 6).7 ns Data Hold Time After Rising Edge of DAV t HOLD C L pf (Notes, 6) 4.2 ns Wake-Up Time from Power-Down t WAKE V REFIN = 2.48V ms Note : Specifications +2 C guaranteed by production test, <+2 C guaranteed by design and characterization. Note 2: See definitions in the Parameter Definitions section at the end of this data sheet. Note 3: Limit specifications include performance degradations due to production test socket. Performance is improved when the is soldered directly to the PC board. Note 4: During power-down, D D, DOR, and DAV are high impedance. Note : Digital outputs settle to V IH or V IL. Note 6: Guaranteed by design and characterization. 6

7 Typical Operating Characteristics (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK 9MHz (% duty cycle), T A = +2 C, unless otherwise noted. AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (892-POINT DATA RECORD) HD3 HD4 f IN = 3.344MHz A IN = -.9dBFS SNR = 7.89dB SINAD = 7.83dB THD = -89.3dBc SFDR = 93.6dBc FREQUENCY (MHz) 4 4 toc AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (892-POINT DATA RECORD) HD2 f IN = MHz A IN = -.dbfs SNR = 7.8dB SINAD = 7.4dB THD = -8.dBc SFDR = 83.2dBc FREQUENCY (MHz) HD 4 4 toc2 AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (892-POINT DATA RECORD) f IN = MHz A IN = -.472dBFS SNR = 7.6dB SINAD = 7.3dB THD = -82.dBc SFDR = 8.8dBc HD3 HD FREQUENCY (MHz) HD2 4 4 toc3 AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (892-POINT DATA RECORD) f IN = MHz A IN = -.2dBFS SNR = 69.2dB SINAD = 68.9dB THD = -7.8dBc SFDR = 76.8dBc HD3 HD HD FREQUENCY (MHz) 4 4 toc4 AMPLITUDE (dbfs) SINGLE-TONE FFT PLOT (892-POINT DATA RECORD) f IN = MHz A IN = -.3dBFS SNR = 68.4dB SINAD = 66.42dB THD = -7.3dBc SFDR = 72.4dBc HD2 HD3 HD FREQUENCY (MHz) 4 4 toc AMPLITUDE (dbfs) TWO-TONE FFT PLOT (6,384-POINT DATA RECORD) f IN = MHz A IN = -7.dBFS f IN2 = 7.93MHz A IN2 = -7.dBFS SFDR TT = 84.7dB IMD = -82.4dBc IM3 = -84.3dBc 2 f IN + f IN2 f IN + f IN2 2 f IN2 + f IN f IN FREQUENCY (MHz) f IN2 3 f IN + 2 f IN2 4 4 toc6 AMPLITUDE (dbfs) f IN2 TWO-TONE FFT PLOT (6,384-POINT DATA RECORD) f IN2 - f IN f IN f IN = MHz A IN = -7.dBFS f IN2 = MHz A IN2 = -7.dBFS SFDR TT = 7.dBc IMD = -73.6dBc IM3 = -76.dBc 2 f IN + f IN2 f IN + f 2 f IN2 + f IN IN FREQUENCY (MHz) 4 4 toc7 INL (LSB) INTEGRAL NONLINEARITY DIGITAL OUTPUT CODE toc8 DNL (LSB) DIFFERENTIAL NONLINEARITY DIGITAL OUTPUT CODE toc9 7

8 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK 9MHz (% duty cycle), T A = +2 C, unless otherwise noted. SNR, SINAD (db) SNR, SINAD vs. SAMPLING RATE f IN = 7MHz SNR SINAD f CLK (MHz) toc SFDR, -THD (dbc) SFDR, -THD vs. SAMPLING RATE SFDR -THD f CLK (MHz) f IN = 7MHz toc POWER DISSIPATION (mw) POWER DISSIPATION vs. SAMPLING RATE DIFFERENTIAL CLOCK f IN = 7MHz C L pf ANALOG + DIGITAL POWER ANALOG POWER f CLK (MHz) toc2 SNR, SINAD (db) SNR, SINAD vs. SAMPLING RATE f IN = 7MHz SNR SINAD f CLK (MHz) toc3 SFDR, -THD (dbc) SFDR, -THD vs. SAMPLING RATE SFDR -THD f IN = 7MHz f CLK (MHz) toc4 POWER DISSIPATION (mw) POWER DISSIPATION vs. SAMPLING RATE DIFFERENTIAL CLOCK f IN = 7MHz C L pf ANALOG + DIGITAL POWER ANALOG POWER f CLK (MHz) toc SNR, SINAD (db) SNR, SINAD vs. ANALOG INPUT FREQUENCY SNR SINAD ANALOG INPUT FREQUENCY (MHz) toc6 SFDR, -THD (dbc) SFDR, -THD vs. ANALOG INPUT FREQUENCY SFDR -THD ANALOG INPUT FREQUENCY (MHz) toc7 POWER DISSIPATION (mw) POWER DISSIPATION vs. ANALOG INPUT FREQUENCY DIFFERENTIAL CLOCK C L pf ANALOG + DIGITAL POWER ANALOG POWER ANALOG INPUT FREQUENCY (MHz) toc8 8

9 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK 9MHz (% duty cycle), T A = +2 C, unless otherwise noted. SNR, SINAD (db) SNR, SINAD vs. ANALOG INPUT AMPLITUDE 7 7 f IN = 7MHz SNR 3 SINAD ANALOG INPUT AMPLITUDE (dbfs) toc9 SFDR, -THD (dbc) SFDR, -THD vs. ANALOG INPUT AMPLITUDE 9 8 f IN = 7MHz SFDR 4 -THD ANALOG INPUT AMPLITUDE (dbfs) toc2 POWER DISSIPATION (mw) POWER DISSIPATION vs. ANALOG INPUT AMPLITUDE DIFFERENTIAL CLOCK f CLK = 96MHz f IN = 7MHz C L pf 4 ANALOG + DIGITAL POWER 4 ANALOG POWER ANALOG INPUT AMPLITUDE (dbfs) toc2 SNR, SINAD (db) SNR, SINAD vs. ANALOG SUPPLY VOLTAGE 72 7 f IN = 7MHz SNR 63 SINAD V DD (V) toc22 SFDR, -THD (dbc) SFDR, -THD vs. ANALOG SUPPLY VOLTAGE f IN = 7MHz 6 SFDR -THD V DD (V) toc23 POWER DISSIPATION (mw) POWER DISSIPATION vs. ANALOG SUPPLY VOLTAGE DIFFERENTIAL CLOCK f IN = 7MHz C L pf 3 ANALOG + DIGITAL POWER 3 ANALOG POWER V DD (V) toc24 SNR, SINAD (db) SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE 72 f IN = MHz SNR 63 SINAD OV DD (V) toc2 SFDR, -THD (dbc) SFDR, -THD vs. DIGITAL SUPPLY VOLTAGE f IN = MHz 6 SFDR -THD OV DD (V) toc26 POWER DISSIPATION (mw) POWER DISSIPATION vs. DIGITAL SUPPLY VOLTAGE DIFFERENTIAL CLOCK f IN = MHz f IN = 9MHz C L pf 4 ANALOG + DIGITAL POWER ANALOG POWER OV DD (V) toc27 9

10 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK 9MHz (% duty cycle), T A = +2 C, unless otherwise noted. SNR, SINAD (db) SNR, SINAD vs. TEMPERATURE 72 7 f IN = 7MHz SNR 63 SINAD TEMPERATURE ( C) toc28 SFDR, -THD (dbc) f IN = 7MHz SFDR, -THD vs. TEMPERATURE 6 SFDR -THD TEMPERATURE ( C) toc29 ANALOG POWER DISSIPATION (mw) POWER DISSIPATION vs. TEMPERATURE DIFFERENTIAL CLOCK f IN = 7MHz C L pf 4 ANALOG + DIGITAL POWER 4 ANALOG POWER TEMPERATURE ( C) toc3 OFFSET ERROR (%FS) OFFSET ERROR vs. TEMPERATURE. V REFIN = 2.48V TEMPERATURE ( C) toc3 GAIN ERROR (%FS) V REFIN = 2.48V GAIN ERROR vs. TEMPERATURE TEMPERATURE ( C) toc32

11 Typical Operating Characteristics (continued) (V DD = 3.3V, OV DD =.8V, GND =, REFIN = REFOUT (internal reference), V IN = -.dbfs, CLKTYP = high, DCE = high, PD = low, G/T = low, f CLK 9MHz (% duty cycle), T A = +2 C, unless otherwise noted. VREFOUT (V) REFERENCE OUTPUT VOLTAGE LOAD REGULATION C C.98-4 C I REFOUT SINK CURRENT (ma) toc33 VREFOUT (V) REFERENCE OUTPUT VOLTAGE SHORT-CIRCUIT PERFORMANCE +8 C +2 C -4 C I REFOUT SINK CURRENT (ma) toc34 VREFOUT (V) REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE TEMPERATURE ( C) toc V REFP REFP, COM, REFN LOAD REGULATION toc REFP, COM, REFN SHORT-CIRCUIT PERFORMANCE toc37 VOLTAGE (V) 2.. V COM VOLTAGE (V) V REFP V COM.. -2 V REFN INTERNAL REFERENCE MODE AND BUFFERED EXTERNAL REFERENCE MODE. - SINK CURRENT (ma) 2. V REFN INTERNAL REFERENCE MODE. AND BUFFERED EXTERNAL REFERENCE MODE SINK CURRENT (ma)

12 PIN NAME FUNCTION REFP 2 REFN Pin Description Positive Reference I/O. The full-scale analog input range is ±(V REFP - V REFN ) x 2/3. Bypass REFP to GND with a.µf capacitor. Connect a µf capacitor in parallel with a µf capacitor between REFP and REFN. Place the µf REFP-to-REFN capacitor as close to the device as possible on the same side of the PC board. Negative Reference I/O. The full-scale analog input range is ±(V REFP - V REFN ) x 2/3. Bypass REFN to GND with a.µf capacitor. Connect a µf capacitor in parallel with a µf capacitor between REFP and REFN. Place the µf REFP-to-REFN capacitor as close to the device as possible on the same side of the PC board. 3 COM Common-Mode Voltage I/O. Bypass COM to GND with a 2.2µF capacitor. Place the 2.2µF COM-to- GND capacitor as close to the device as possible. This 2.2µF capacitor can be placed on the opposite side of the PC board and connected to the through a via. 4, 7, 6, 3 GND Ground. Connect all ground pins and EP together. INP Positive Analog Input 6 INN Negative Analog Input 8 DCE Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OV DD or V DD ) to enable the internal duty-cycle equalizer. 9 CLKN CLKP Negative Clock Input. In differential clock input mode (CLKTYP = OV DD or V DD ), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND. Positive Clock Input. In differential clock input mode (CLKTYP = OV DD or V DD ), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND. CLKTYP Clock-Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OV DD or V DD to define the differential clock input. 2, 36 V DD Analog Power Input. Connect V DD to a 3.V to 3.6V power supply. Bypass V DD to GND with a parallel capacitor combination of 2.2µF and.µf. Connect all V DD pins to the same potential. 7, 34 OV DD Output-Driver Power Input. Connect OV DD to a.7v to V DD power supply. Bypass OV DD to GND with a parallel capacitor combination of 2.2µF and.µf. 8 DOR Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range (Figure 6). 9 D CMOS Digital Output, Bit (MSB) 2 D CMOS Digital Output, Bit 2 D9 CMOS Digital Output, Bit 9 22 D8 CMOS Digital Output, Bit 8 23 D7 CMOS Digital Output, Bit 7 24 D6 CMOS Digital Output, Bit 6 2 D CMOS Digital Output, Bit 26 D4 CMOS Digital Output, Bit 4 27 D3 CMOS Digital Output, Bit 3 28 D2 CMOS Digital Output, Bit 2 2

13 PIN NAME FUNCTION 29 D CMOS Digital Output, Bit 3 D CMOS Digital Output, Bit (LSB) 3, 32 I.C. Internally Connected. Leave I.C. unconnected. 33 DAV Pin Description (continued) Data-Valid Output. DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. DAV is typically used to latch the output data into an external back-end digital circuit. 37 PD Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. 38 REFOUT 39 REFIN 4 G/ T EP Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a.µf capacitor. Reference Input. In internal reference mode and buffered external reference mode, bypass REFIN to GND with a.µf capacitor. In these modes V REFP - V REFN = V REFIN x 3/4. For unbuffered external reference mode operation, connect REFIN to GND. Output-Format-Select Input. Connect G/ T to GND for the two s-complement digital output format. Connect G/ T to OV DD or V DD for the Gray-code digital output format. Exposed Paddle. The relies on the exposed paddle connection for a low-inductance ground connection. Connect EP to GND to achieve specified performance. Use multiple vias to connect the top-side PC board ground plane to the bottom-side PC board ground plane. INP INN FLASH ADC T/H + DAC Σ T/H STAGE STAGE 2 STAGE 9 STAGE END OF PIPE CLKP CLKN DCE CLKTYP INP INN REFOUT CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER T/H 2-BIT PIPELINE ADC DEC OUTPUT DRIVERS V DD GND OV DD D D DAV DOR G/T DIGITAL ERROR CORRECTION D D OUTPUT DRIVERS D D REFIN REFP COM REFN REFERENCE SYSTEM POWER CONTROL AND BIAS CIRCUITS PD Figure. Pipeline Architecture Stage Blocks Figure 2. Simplified Functional Diagram Detailed Description The uses a -stage, fully differential, pipelined architecture (Figure ) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output, the total clock-cycle latency is 8. clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the functional diagram. 3

14 INP INN BOND WIRE INDUCTANCE.nH BOND WIRE INDUCTANCE.nH SAMPLING CLOCK V DD V DD C PAR 2pF C PAR 2pF *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: R SAMPLE = Figure 3. Simplified Input Track-and-Hold Circuit *C SAMPLE 4.pF *C SAMPLE 4.pF f CLK x C SAMPLE Input Track-and-Hold (T/H) Circuit Figure 3 displays a simplified functional diagram of the input track-and-hold (T/H) circuit. This input T/H circuit allows for high analog input frequencies of 7MHz and beyond and supports a V DD / 2 ±.V commonmode input voltage. The sampling clock controls the ADC s switched-capacitor T/H architecture (Figure 3), allowing the analog input signal to be stored as charge on the sampling capacitors. These switches are closed (track) when the sampling clock is high and they are open (hold) when the sampling clock is low (Figure 4). The analog input signal source must be capable of providing the dynamic current necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these capacitors must be charged to /2 LSB accuracy within one half of a clock cycle. The analog input of the supports differential or single-ended input drive. For optimum performance with differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (V DD / 2). The provides the optimum common-mode voltage of V DD / 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures,, and 2. Reference Output (REFOUT) An internal bandgap reference is the basis for all the internal voltages and bias currents used in the. The power-down logic input (PD) enables and disables the reference circuit. The reference circuit requires ms to power up and settle when power is applied to the or when PD transitions from high to low. REFOUT has approximately 7kΩ to GND when the is in power-down. The internal bandgap reference and its buffer generate V REFOUT to be 2.48V. The reference temperature coefficient is typically +ppm/ C. Connect an external.µf bypass capacitor from REFOUT to GND for stability. REFOUT sources up to.ma and sinks up to.ma for external circuits with a load regulation of 3mV/mA. Short-circuit protection limits I REFOUT to a 2.mA source current when shorted to GND and a.24ma sink current when shorted to V DD. CLKP CLKN ANALOG INPUT t AD t AJ SAMPLED DATA T/H TRACK HOLD TRACK HOLD TRACK HOLD TRACK HOLD Figure 4. T/H Aperture Timing 4

15 Table. Reference Modes V REFIN 3% V REFOUT to % V REFOUT.7V to 2.2V REFERENCE MODE Internal Reference Mode. Drive REFIN with REFOUT either through a direct short or a resistive divider. The full-scale analog input range is ±V REFIN / 2: V COM = V DD / 2 V REFP = V DD / 2 + V REFIN x 3/8 V REFN = V DD / 2 - V REFIN x 3/8 Buffered External Reference Mode. Apply an external.7v to 2.2V reference voltage to REFIN. The full-scale analog input range is ±V REFIN / 2: V COM = V DD / 2 V REFP = V DD / 2 + V REFIN x 3/8 V REFN = V DD / 2 - V REFIN x 3/8 <.4V Unbuffered External Reference Mode. Drive REFP, REFN, and COM with external reference sources. The full-scale analog input range is ±(V REFP - V REFN ) x 2/3. Analog Inputs and Reference Configurations The full-scale analog input range is adjustable from ±.3V to ±.V with a commonmode input range of V DD / 2 ±.V. The provides three modes of reference operation. The voltage at REFIN (V REFIN ) sets the reference operation mode (Table ). To operate the with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive divider. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, V REFP = V DD / 2 + V REFIN x 3/8, and V REFN = V DD / 2 - V REFIN x 3/8. The REFIN input impedance is very large (>MΩ). When driving REFIN through a resistive divider, use resistances kω to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the REFOUT. In buffered external reference mode, apply a stable.7v to 2.2V source at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, V REFP = V DD / 2 + V REFIN x 3/8, and V REFN = V DD /2 - V REFIN x 3/8. To operate the in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With the respective buffers deactivated, COM, REFP, and REFN become highimpedance inputs and must be driven through separate, external reference sources. Drive V COM to V DD / 2 ±%, and drive REFP and REFN such that V COM = (V REFP + V REFN ) / 2. The full-scale analog input range is ±(V REFP - V REFN ) x 2/3. All three modes of reference operation require the same bypass capacitor combinations. Bypass COM with a 2.2µF capacitor to GND. Bypass REFP and REFN each with a.µf capacitor to GND. Bypass REFP to REFN with a µf capacitor in parallel with a µf capacitor. Place the µf capacitor as close to the device as possible on the same side of the PC board. Bypass REFIN and REFOUT to GND with a.µf capacitor. For detailed circuit suggestions, see Figures 3 and 4.

16 V DD CLKP CLKN GND S L S H kω kω S 2L S 2H kω kω Figure. Simplified Clock Input Circuit DUTY-CYCLE EQUALIZER SWITCHES S _ AND S 2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S 2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE. Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP) The accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock input operation, connect CLKTYP to OV DD or V DD, and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the is powered down (Figure ). Low clock jitter is required for the specified SNR performance of the. Analog input sampling occurs on the falling edge of the clock signal, requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: SNR = 2 log 2 π fin t J where f IN represents the analog input frequency and t J is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 68.4dB of SNR with an input frequency of 7MHz, the system must have less than.3ps of clock jitter. In actuality, there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than.23ps to obtain the specified 68.4dB of SNR at 7MHz. Clock Duty-Cycle Equalizer (DCE) Connect DCE high to enable the clock duty-cycle equalizer (DCE = OV DD or V DD ). Connect DCE low to disable the clock duty-cycle equalizer (DCE = GND). With the clock duty-cycle equalizer enabled, the is insensitive to the duty cycle of the signal applied to CLKP and CLKN. Duty cycles from 3% to 6% are acceptable with the clock duty-cycle equalizer enabled. The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are duty-cycle independent. Due to this DLL, the requires approximately clock cycles to acquire and lock to new clock frequencies. Although not recommended, disabling the clock dutycycle equalizer reduces the analog supply current by.ma. With the clock duty-cycle equalizer disabled, the s dynamic performance varies depending on the duty cycle of the signal applied to CLKP and CLKN. 6

17 System Timing Requirements Figure 6 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8. clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the rising edge of the conversion clock (CLKP-CLKN). Data-Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). Output data changes on the falling edge of DAV, and DAV rises once output data is valid (Figure 6). The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE = low), the DAV signal is the inverse of the signal at CLKP delayed by 6.8ns. With the dutycycle equalizer enabled (DCE = high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D D and DOR are valid from.7ns (t SETUP ) before the rising edge of DAV to 4.2ns (t HOLD ) after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.8ns (t DAV ) delay from the falling edge of CLKP. DAV is high impedance when the is in powerdown (PD = high). DAV is capable of sinking and sourcing 6µA and has three times the drive strength of D D and DOR. DAV is typically used to latch the output data into an external back-end digital circuit. Keep the capacitive load on DAV as low as possible (<2pF) to avoid large digital currents feeding back into the analog portion of the and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX2 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (V REFP - V REFN ) x 2/3 to (V REFN - V REFP ) x 2/3. Signals outside this valid differential range cause DOR to assert high as shown in Table 2 and Figure 6. DOR is synchronized with DAV and transitions along with the output data D D. There is an 8. clockcycle latency in the DOR function, as is with the output data (Figure 6). DOR is high impedance when the is in power-down (PD = high). DOR enters a high-impedance state within ns after the rising edge of PD and becomes active ns after PD s falling edge. (V REFP - V REFN ) x 2/3 DIFFERENTIAL ANALOG INPUT (INP INN) N - 3 N - 2 N - N N + N + 2 N + 3 N + 4 N + N + 6 N + 7 N + 9 (V REFN - V REFP ) x 2/3 N + 8 CLKN t AD CLKP DAV t DAV t CL t CH D D DOR t SETUP t HOLD N - 3 N - 2 N - N N + N + 2 N + 3 N + 4 N + N + 6 N + 7 N + 8 N CLOCK-CYCLE DATA LATENCY t SETUP thold Figure 6. System Timing Diagram 7

18 Digital Output Data (D D), Output Format (G/ T) The provides a 2-bit, parallel, tri-state output bus. D D and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. The output data format is either Gray code or two s complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two s complement. See Figure 9 for a binary-to-gray and Gray-tobinary code conversion example. The following equations, Table 2, Figure 7, and Figure 8 define the relationship between the digital output and the analog input: 4 CODE VINP VINN = ( VREFP VREFN) for Gray code (G/T = ). 4 CODE VINP VINN = ( VREFP VREFN) where CODE is the decimal equivalent of the digital output code as shown in Table 2. Digital outputs D D are high impedance when the is in power-down (PD = high). D D transition high ns after the rising edge of PD and become active ns after PD s falling edge. Keep the capacitive load on the digital outputs D D as low as possible (<pf) to avoid large digital currents feeding back into the analog portion of the and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolates the from heavy capacitive loading. To improve the dynamic performance of the, add 22Ω resistors in series with the digital outputs close to the. Refer to the MAX2 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 22Ω series resistors. for two s complement (G/T = ). TWO'S-COMPLEMENT OUTPUT CODE (LSB) x7ff x7fe x7fd x x xfff x83 x82 x8 x8 (V REFP - V REFN ) x 2/3 (V REFP - V REFN ) x 2/3 GRAY OUTPUT CODE (LSB) x8 x8 x83 xc xc x4 x2 x3 x x (V REFP - V REFN ) x 2/3 (V REFP - V REFN ) x 2/ DIFFERENTIAL INPUT VOLTAGE (LSB) DIFFERENTIAL INPUT VOLTAGE (LSB) Figure 7. Two s-complement Transfer Function (G/ T = ) Figure 8. Gray-Code Transfer Function (G/ T = ) 8

19 Table 2. Output Codes vs. Input Voltage BINARY D D DOR GRAY-CODE OUTPUT CODE (G/T = ) HEXADECIMAL EQUIVALENT OF D D D EC IM A L EQ U IVA L EN T O F D D (CODE) BINARY D D TWO S-COMPLEMENT OUTPUT CODE (G/T = ) DOR H EXA D EC IM A L EQ U IVA L EN T O F D D DECIM AL EQUIVALENT OF D D (CODE) VINP - VINN VREFP = 2.48V VREFN =.882V >+.23V x8 +49 x7ff +247 (DATA OUT OF RANGE) x8 +49 x7ff V x x7fe V xc3 +2 x V xc +249 x + +.V xc +248 x +.V x xfff - -.V x xffe -2 -.V x + x V x x V <-.24V x x8-248 (DATA OUT OF RANGE) 9

20 BINARY-TO-GRAY-CODE CONVERSION ) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D D7 D3 D BINARY 2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAY X = BINARY X + BINARY X + BIT POSITION GRAY CODE GRAY-TO-BINARY-CODE CONVERSION ) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D D7 D3 D 2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARY X = BINARY X+ + GRAY X BIT POSITION GRAY CODE BINARY WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: TABLE BELOW) AND X IS THE BIT POSITION: GRAY = BINARY + BINARY GRAY = + GRAY = D D7 D3 D BIT POSITION BINARY = BINARY + GRAY BINARY = + BINARY = D D7 D3 D BIT POSITION + BINARY GRAY CODE + GRAY CODE BINARY 3) REPEAT STEP 2 UNTIL COMPLETE: GRAY 9 = BINARY 9 + BINARY GRAY 9 = + GRAY 9 = 3) REPEAT STEP 2 UNTIL COMPLETE: BINARY 9 = BINARY + GRAY 9 BINARY 9 = + BINARY 9 = D D7 D3 D BIT POSITION D D7 D3 D BIT POSITION + BINARY GRAY CODE + GRAY CODE BINARY 4) THE FINAL GRAY-CODE CONVERSION IS: 4) THE FINAL BINARY CONVERSION IS: D D7 D3 D BIT POSITION D D7 D3 D BIT POSITION BINARY GRAY CODE GRAY CODE BINARY EXCLUSIVE OR TRUTH TABLE A B Y = A + B Figure 9. Binary-to-Gray and Gray-to-Binary Code Conversion 2

21 V IN.μF N.C. 2 T MINI-CIRCUITS TT-6 OR T-T 24.9Ω 2pF 2.2μF 24.9Ω 2pF INP COM INN V IN MAX48 Ω Ω.μF 24.9Ω 24.9Ω.6pF 2.2μF INP COM Figure. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist.6pF INN Figure 2. Single-Ended, AC-Coupled Input Drive Ω* V IN.μF T 6 7Ω.% T2 6 Ω.%.6pF** INP N.C. 2 N.C. 2 N.C. COM 3 4 MINI-CIRCUITS ADT-WT 7Ω.% 3 4 MINI-CIRCUITS ADT-WT Ω.% 2.2μF Ω* INN.6pF** *Ω RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE BANDWIDTH. **TUNE THESE CAPACITORS FROM.6pF TO 8pF IN ORDER TO OPTIMIZE DYNAMIC PERFORMANCE VARIATIONS DUE TO: PRINTED CIRCUIT BOARD (PCB) LAYOUT ANALOG INPUT SIGNAL POWER ANALOG INPUT CARRIER FREQUENCY Figure. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist Power-Down Input (PD) The has two power modes that are controlled with the power-down digital input (PD). With PD low, the is in normal operating mode. With PD high, the is in power-down mode. The power-down mode allows the to efficiently use power by transitioning to a low-power state when conversion is not required. Additionally, the parallel output bus is high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to.2ma, and the digital supply current reduces to µa. The following list shows the state of the analog inputs and digital outputs in power-down mode: INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). REFOUT has approximately 7kΩ to GND. REFP, COM, REFN go high impedance with respect to V DD and GND, but there is an internal 4kΩ resistor between REFP and COM, as well as an internal 4kΩ resistor between REFN and COM. 2

22 .μf +3.3V 2 MAX629EUK2 2.48V NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING ma AND SINKING 3mA OF OUTPUT CURRENT..μF +3.3V 2.2μF.μF V DD REFP 38 REFOUT REFN 2.μF μf* μf.μf +3.3V.μF 6.2kΩ μf 3 2 MAX Ω μf 6V 2.48V 33μF 6V 39 REFIN GND COM +3.3V 2.2μF.μF 3 2.2μF.47kΩ.μF *PLACE THE μf REFP-to-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE..μF 38 REFOUT V DD REFP μf* μf REFN 2.μF 39 REFIN GND COM 3 2.2μF Figure 3. External Buffered Reference Driving Multiple ADCs D D, DOR, and DAV go high impedance. CLKP, CLKN go high impedance (Figure ). The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode the wake-up time is typically ms with the recommended capacitor array (Figure 3). When operating in unbuffered external reference mode, the wake-up time is dependent on the external reference drivers. Applications Information Using Transformer Coupling In general, the provides better SFDR and THD performance with fully differential input signals as opposed to single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to singleended input mode. An RF transformer (Figure ) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level 22

23 .μf +3.3V 2.47μF 3.V MAX629EUK3 2kΩ % 2kΩ % 2.3kΩ % 2.3kΩ % 2kΩ % 2kΩ % 2kΩ %.μf 3.μF 3.μF V V V 2 MAX423 47Ω 4 μf 6V.47kΩ MAX423 47Ω 4 μf 6V.47kΩ MAX423 47Ω 4 μf 6V 2.43V 33μF 6V.647V 33μF 6V.88V 33μF 6V μf μf +3.3V 2.2μF.μF.μF V DD REFP 38 REFOUT μf* 2 REFN.μF 3 COM REFIN 39 GND 2.2μF +3.3V 2.2μF.μF.μF REFP 38 REFOUT μf* 2 REFN.μF V DD.μF.μF.47kΩ *PLACE THE μf REFP-TO-REFN BYPASS CAPACITOR AS CLOSE TO THE DEVICE AS POSSIBLE. 2.2μF 3 COM GND REFIN 39 Figure 4. External Unbuffered Reference Driving Multiple ADCs shift to the input. Although a : transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure is good for frequencies up to Nyquist (fclk / 2). The circuit of Figure converts a single-ended input signal to fully differential just as Figure. However Figure utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. The two sets of termination resistors provide an equivalent Ω termination to the signal source, as the ADT-WT transformer has a :. impedance ratio. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two Ω resistors in series with the analog inputs allow high IF input frequencies. These Ω resistors can be replaced with lowvalue resistors to limit the input bandwidth. Single-Ended AC-Coupled Input Signal Figure 2 shows an AC-coupled, single-ended input application. The MAX48 operational amplifier provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. 23

24 Buffered External Reference Drives Multiple ADCs The buffered external reference mode allows for more control over the reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >MΩ. Figure 3 uses the MAX629EUK2 precision 2.48V reference as a common reference for multiple converters. The 2.48V output of the MAX629 passes through a one-pole, Hz lowpass filter to the MAX423. The MAX423 buffers the 2.48V reference and provides additional Hz lowpass filtering before its output is applied to the REFIN input of the. Unbuffered External Reference Drives Multiple ADCs The unbuffered external reference mode allows for precise control over the reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. Figure 4 uses the MAX629EUK3 precision 3.V reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX629 voltage reference. The.47µF capacitor along this chain creates a Hz lowpass filter. Three MAX423 operational amplifiers buffer taps along this resistor chain providing 2.43V,.647V, and.88v to the s REFP, COM, and REFN reference inputs, respectively. The feedback around the MAX423 op amps provides additional Hz lowpass filtering. The 2.43V and.88v reference voltages set the full-scale analog input range to ±.22V = ±(V REFP - V REFN ) x 2/3. A common power source for all active components removes any concern regarding power-supply sequencing when powering up or down Grounding, Bypassing, and Board Layout The requires high-speed board layout design techniques. Refer to the MAX2 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side of the board as the ADC, using surface-mount devices for minimum inductance. Bypass V DD to GND with a.µf ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Bypass OV DD to GND with a.µf ceramic capacitor in parallel with a 2.2µF ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All GNDs and the exposed backside paddle must be connected to the same ground plane. The relies on the exposed backside paddle connection for a low-inductance ground connection. Use multiple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 9 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX2 evaluation kit data sheet for an example of symmetric input layout. Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. For the, this straight line is between the end points of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of LSB. A DNL error specification of less than LSB guarantees no missing codes and a monotonic transfer function. For the, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table. Offset Error Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally the midscale transition occurs at. LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point. Gain Error Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally the positive full-scale transition occurs at. 24

25 LSB below positive full scale, and the negative fullscale transition occurs at. LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points. Small-Signal Noise Floor (SSNF) Small-signal noise floor is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -3dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Go to for application notes on thermal + quantization noise floor. Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC s resolution (N bits): SNR [max] = 6.2 N +.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 to HD7), and the DC offset: SIGNAL SNR RMS = 2 log NOISE RMS Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: Single-Tone Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: THD where V is the fundamental amplitude, and V 2 through V 7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2 HD7). Intermodulation Distortion (IMD) IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as: IMD = 2 log = 2 log SINAD ENOB = V2 2 + V3 2 + V4 2 + V 2 + V6 2 + V7 2 V VIM 2 + VIM VIM3 2 + VIM V + V2 Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 HD7), and the DC offset. RMS distortion includes the first six harmonics (HD2 HD7): SINAD = 2 log SIGNALRMS 2 2 NOISERMS + DISTORTIONRMS The fundamental input tone amplitudes (V and V 2 ) are at -7dBFS. Fourteen intermodulation products (V IM _) are used in the IMD calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies, where f IN and f IN2 are the fundamental input tone frequencies: Second-order intermodulation products: f IN + f IN2, f IN2 - f IN Third-order intermodulation products: 2 x f IN - f IN2, 2 x f IN2 - f IN, 2 x f IN + f IN2, 2 x f IN2 + f IN Fourth-order intermodulation products: 3 x f IN - f IN2, 3 x f IN2 - f IN, 3 x f IN + f IN2, 3 x f IN2 + f IN 2