ID 620C: Complete Motor Control Integration with Rx62T

Transcription

1 ID 620C: Complete Motor Control Integration with Rx62T Renesas Electronics America Inc. Yashvant Jani Ph. D. Director, Applications Engineering 13 October 2010 Version 2.0

2 Yashvant Jani, Ph. D. Director, MPU Applications Engineering MPU Solutions, SH2A and SH4A architecture, managing hardware design and software development, New Product Specifications OTHER RELEVANT DETAILS 15+ years in semiconductor industry in solution development, performance evaluation, technical training, hardware design to support software and firmware and 15 years in space industry supporting shuttle operations and advance space vehicles Technical courses at UC-Berkeley, University of Tennessee, Duke University, Technical workshops and papers in Motor Control, Fuzzy Logic, Neural Networks, VoIP/Networking and AI learning (at ESC, SPIE, IEEE, IATC and AIAA Control conferences) Experience in Data Compression, Networking & Communication, systems engineering, verification and validation of space system software and performance evaluation of hardware, hardware modeling, simulation Ph.D. in Physics University of Texas at Dallas, M.S. in Physics and Mathematics, M.Sc. In Nuclear physics 60+ published papers and presentations Interests in Photography & Traveling 2

3 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 3

4 Renesas Technology and Solution Portfolio Microcontrollers & Microprocessors #1 Market share worldwide * ASIC, ASSP & Memory Advanced and proven technologies Solutions for Innovation Analog and Power Devices #1 Market share in low-voltage MOSFET** * MCU: 31% revenue basis from Gartner "Semiconductor Applications Worldwide Annual Market Share: Database" 25 March 2010 ** Power MOSFET: 17.1% on unit basis from Marketing Eye 2009 (17.1% on unit basis). 4

5 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive High Performance CPU, Low Power Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 ua standby Medical, Automotive & Industrial High Performance CPU, FPU, DSC Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 ua standby Ethernet, CAN, USB, Motor Control, TFT Display Legacy Cores Next-generation migration to RX General Purpose Up to 10 DMIPS, 130nm process 350 ua/mhz, 1uA standby Capacitive touch Ultra Low Power Up to 25 DMIPS, 150nm process 190 ua/mhz, 0.3uA standby Application-specific integration Embedded Security Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 5

6 Microcontroller and Microprocessor Line-up Superscalar, MMU, Multimedia Up to 1200 DMIPS, 45, 65 & 90nm process Video and audio processing on Linux Server, Industrial & Automotive High Performance CPU, Low Power Up to 500 DMIPS, 150 & 90nm process 600uA/MHz, 1.5 ua standby Medical, Automotive & Industrial High Performance CPU, FPU, DSC Up to 165 DMIPS, 90nm process 500uA/MHz, 2.5 ua standby Ethernet, CAN, USB, Motor Control, TFT Display RX Motor Control Legacy Cores Next-generation migration to RX General Purpose Up to 10 DMIPS, 130nm process 350 ua/mhz, 1uA standby Capacitive touch RX600 Ultra Low Power (100 MHz, Low Power) Up to 25 DMIPS, 150nm process 190 ua/mhz, RX uA standby (50 MHz, Application-specific integration Ultra Low Power) Embedded Security Up to 25 DMIPS, 180, 90nm process 1mA/MHz, 100uA standby Crypto engine, Hardware security 6

7 Innovation Silicon for Motor Control Issues commonly heard from designers and developers Wish the firmware code can be smaller Need more CPU bandwidth Must have simultaneous automatic ADC triggering How are we going to meet standards? Too many tasks to do in software 7

8 The RX62T Motor Control Viewpoint Overcome problems and meet market demand Higher MHz for performance Better code efficiency Support for Standards Rx62T Higher level of peripheral integration Internal interfaces to support firmware 8

9 Agenda RX62T Overview CPU enhancements and FPU 7 min 10 min Peripheral integration MTU3 Break time ADC GPT Standards support Examples peripherals usage Q&A 15 min 10 min 7 min 8 min 5 min 15 min 15 min 9

10 Key Takeaways By the end of this session you will be able to: Identify the strengths of the Rx devices Understand the peripheral integration available Effectively use hardware constructs for firmware efficiency 10

11 Rx62T Overview 11

12 Overview of RX62T 100 MHz 165 DMIPS Harvard CPU FLASH 256KB/ 128KB SRAM 16KB/ 8KB DATA FLASH 8KB FPU CRC MUL & DIV MAC ICU DEBUG DTC ADC 10b 10ch, 2S/H ADC 12b 4ch, 3S/H OSC 125Khz PLL I-WDT MTU3 16bit x 8chn CMT 16bit X 4chn ADC 12b 4ch, 3S/H 3OP Amp 3Comp POR/LVD EXT OSC WDT GPT 16bit X 4chn GPIO w/mux 3OP Amp 3Comp RSPI x1 SCI x3 I2C x1 RCAN (optional) CPU MEMORY ANALOG TIMER I/O 12

13 Overview of RX62T RX600 CPU Core 100MHz CISC CPU with Harvard Architecture 165 DMIPS at 100MHz Floating Point Unit (FPU) Multiply Accumulate (MAC) Flash Memory 100 MHz, zero wait-state access Analog 4 ch x 2 units 12-bit ADC 4 sample & hold, 1usec conversion 12 ch x10-bit ADC, 2 sample-hold, 1usec 6 Op. Amp and 6 Comparator Timers MTU3 16bit x 8chn General purpose PWM timer 16bit x 4ch Compare Much Timer 16bit x 4 channels Communication UART/Clock synchronous serial x 3Unit RSPI x 1 Unit, LIN I/F x 1Unit, I2C bus I/F 1 Unit RCAN 1unit(Option) Others Data Transfer Controller (DTC) POR, LVD On chip oscillator 125KHz for independent WDT Package LQFP-100 (14x 14mm, 0.5mm pitch) FPU 100 MHz 165 DMIPS Harvard CPU MUL & DIV ADC 10b 10ch, 2S/H ADC 12b 4ch, 3S/H ADC 12b 4ch, 3S/H 3OP Amp 3Comp 3OP Amp 3Comp CRC POR/LVD CPU MAC OSC 125Khz PLL EXT OSC RSPI x1 MEMORY FLASH 256KB/ 128KB ICU I-WDT WDT SCI x3 ANALOG SRAM 16KB/ 8KB DEBUG MTU3 16bit x 8chn TIMER GPT 16bit X 4chn I2C x1 I/O DATA FLASH 8KB DTC CMT 16bit X 4chn GPIO w/mux RCAN (optional) 13

14 RX62T Group RX CPU Core 100MHz (2.7 to 5.5V) Enhanced Harvard Architecture 165 DMIPS at 100MHz Floating Point Unit (FPU) Multiply Accumulate (MAC) Low Power Consumption 500 µa per MHz, all peripherals active True 5V Operation Choose devices 2.7V-3.6V, or 4.0V-5.5V Flash Memory 100 MHz, zero wait-state access Analog 8 channels 12-bit ADC, 1 µs conversion time 12 channels 10-bit ADC, dual sample-hold, 1 µs 6 Op. Amp w/pga and 6 Comparators Advanced Timers to Drive 2 Motors MTU3 16-bit x 8 channels General purpose PWM timer 16-bit x 4 channels Compare Match Timer 16-bit x 4 channels Communication UART/Clock synchronous serial x 3 Unit RSPI x 1 Unit, LIN I/F x 1Unit, I2C bus I/F 1 Unit RCAN 1unit (Option) Others DMA capability with Data Transfer Controller (DTC) POR, LVD On chip oscillator 125KHz±10% for independent WDT Low pin count Small Packages, 64, 80, 100, and 112 pin True 5V Advanced Timers Advanced Analog RX62T Memory Zero-Wait Flash up to 256KB SRAM up to 16KB Data Flash 8KB System Data Management DTC Interrupt Cont. 16 levels 9 pins Clock Generation OSC PLL IRC POR/ LVD Analog 2 x ADC 12-bit 4 ch with PGA, S/H, & Comparators ADC 10-bit 12 ch Timers MTU3 16-bit 8 ch GPT 16-bit 4 ch 2 x CMT 16-bit 2 ch WDT 8-bit 1 ch I-WDT 14-bit 1 ch Communication CAN 2.0B LIN I2C 3 x SCI SPI GPIO 14

15 RX62T Product Selection FLASH / SRAM 256 KB / 16 KB 80 MHz R5F562TAADFM RX62TA CAN, 4.0V TO 5.5V 80 MHz R5F562TADDFM RX62TA 4.0V TO 5.5V R5F562TABDFM 2.7V to 5.5V Version R5F562TAEDFM 2.7V to 5.5V Version R5F562TAADFF RX62TA CAN, 4.0V TO 5.5V R5F562TADDFF RX62TA 4.0V TO 5.5V R5F562TABDFF 2.7V to 5.5V Version R5F562TAEDFF 2.7V to 5.5V Version R5F562TAADFP RX62TA CAN, 4.0V TO 5.5V R5F562TADDFP RX62TA 4.0V TO 5.5V R5F562TABDFP 2.7V to 5.5V Version R5F562TAEDFP 2.7V to 5.5V Version R5F562TAADFH RX62TA CAN, 4.0V TO 5.5V R5F562TADDFH RX62TA 4.0V TO 5.5V R5F562TABDFH 2.7V to 5.5V Version R5F562TAEDFH 2.7V to 5.5V Version CAN No CAN 128 KB / 8 KB 80 MHz R5F562T7ADFM RX62T7 CAN, 4.0V TO 5.5V 80 MHz R5F562T7DDFM RX62T7 4.0V TO 5.5V R5F562T7BDFM 2.7V to 5.5V Version R5F562T7EDFM 2.7V to 5.5V Version R5F562T7ADFF RX62T7 CAN, 4.0V TO 5.5V R5F562T7DDFF RX62T7 4.0V TO 5.5V R5F562T7BDFF 2.7V to 5.5V Version R5F562T7EDFF 2.7V to 5.5V Version R5F562T7ADFP RX62T7 CAN, 4.0V TO 5.5V R5F562T7DDFP RX62T7 4.0V TO 5.5V R5F562T7BDFP 2.7V to 5.5V Version R5F562T7EDFP 2.7V to 5.5V Version R5F562T7ADFH RX62T7 CAN, 4.0V TO 5.5V R5F562T7DDFH RX62T7 4.0V TO 5.5V R5F562T7BDFH 2.7V to 5.5V Version R5F562T7EDFH 2.7V to 5.5V Version CAN No CAN 64 KB / 8 KB 80 MHz R5F562T6ADFM RX62T6 CAN, 4.0V TO 5.5V 80 MHz R5F562T6DDFM RX62T6 4.0V TO 5.5V R5F562T6BDFM 2.7V to 5.5V Version R5F562T6EDFM 2.7V to 5.5V Version R5F562T6ADFF RX62T6 CAN, 4.0V TO 5.5V R5F562T6DDFF RX62T6 4.0V TO 5.5V R5F562T6BDFF 2.7V to 5.5V Version R5F562T6EDFF 2.7V to 5.5V Version All Devices : 40 o C to +85 o C CAN No CAN 64 pins LQFP 10x pitch 80 pins LQFP 14x pitch 100 pins LQFP 14x pitch 112 pins LQFP 20x pitch 15

16 Rx CPU Enhancements 16

17 RX CPU Features 32-bit RX CPU Mostly single clock instructions 5-stage execution pipeline Ultra fast 5-cycle interrupts Dhrystone DMIPS per MHz ARM7 ARM9 Cortex-M3 Cortex-M RX 1.65 DMIPS/MHz 32-bit FPU Single precision IEEE-754 compliant Direct access to General Registers Note: Dhrystone numbers for ARM processors taken from DSP Repeated Multiply & Accumulate 64-bits Multiply & Accumulate 48-bits Barrel shifter 32-bits Multiple busses Enhanced Harvard bus Internal DTC and DMA controllers External bus with DMA controller 17

18 RX CPU Features for Performance CPU Architecture Hardware divider and FPU in addition to multiplier and MAC 64-bit instruction bus with memory protection unit Enhanced Harvard architecture Parallel execution of instruction fetches and memory accesses boosts pipeline performance Five-stage pipeline The five-stage pipeline configuration speeds up instruction execution. Zero Wait state flash access (up to 100MHz) Single-precision floating-point unit The single-precision floating-point unit uses general registers for operations. 18

19 Register Set : Sixteen 32-Bit General Registers Facilitating register-register operations reduces memory accesses. The use of general registers simplifies compiler optimization. High-speed interrupt registers speed up interrupt handling. Augmented general registers can be allocated for dedicated use by interrupts, enabling a further speed increase. General registers Control registers 32 bits R0 (SP * ) R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 High-speed interrupt registers 32 bits ISP USP INTB PC PSW BPSW BPC FINTV FPSW CPEN Interrupt stack pointer User stack pointer Interrupt table register Program counter Processor status word register Backup PSW Backup PC Fast interrupt vector register Floating-point status word register Coprocessor enable register * Stack pointer 19

20 RX Architecture RX600 CISC CPU 100MHz CPU Core 16 x 32bit General Purpose Registers 32bit Floating Point Unit 9 x 32bit Control Registers Memory Protection Unit 32 x 32 MAC to 48bit or 80bit Result 32 x 32 DIV or MULT to 32bit or 64bit Result Interrupt Control On-Chip Debug 20

21 Enhanced Harvard Architecture Simultaneous instruction fetches and memory accesses boosts performance Flash RAM Instruction Fetch 64-bit IF Shifter Shifter RX CPU core Instruction Interface ALU ALU Peripheral Functions Separate buses allow parallel execution Memory Access Multiplier Multiplier Data Interface Divider Divider 32-bit registers x16 21

22 RX600 internal bus configuration One bus for CPU and second for the other bus-master modules RX CPU Instruction Bus Operates in synchronization with ICLK Operates in synchronization with PCLK Operates in synchronization with BCLK Operand Bus ROM Internal main bus 1 RAM DTC Internal main bus 2 EXDMAC Internal peripheral bus External bus control External bus MTU3 GPT SCI AD USB Data Flash. Bus Name Bus master Connected module or bus Instruction / Operand bus CPU Internal Flash ROM / RAM Internal main bus 1 CPU Internal peripheral bus and external bus Internal main bus 2 DMAC, DTC and E-DMAC Internal peripheral bus CPU, DMAC, DTC and E-DMAC Internal peripheral module External bus CPU, DMAC, DTC, E-DMAC and EXDMAC External devices Internal Flash ROM / RAM, Internal peripheral bus and external bus 22

23 Multiple Busses Increase Performance RX CPU Instruction Bus Operand Bus Flash Main Bus 1 Main Bus 2 External DMA controller RAM Peripheral Bus DMA controller Three simultaneous operations 1. RX CPU executing out of Flash 2. DMA storing ADC data to RAM 3. EXDMAC sending data from external memory to External LCD External bus control External Bus TMR SCI ADC. External LCD External Memory RX CPU DMA controller External DMA controller 23

24 RX Architecture CPU Core and Pipeline RX600 CISC CPU 100MHz CPU Core 9 x 32bit Control Registers 16 x 32bit General Purpose Registers 32bit Floating Point Unit 32 x 32 MAC to 48bit or 80bit Result 32 x 32 DIV or MULT to 32bit or 64bit Result Interrupt Control Memory Protection Unit On-Chip Debug 64bit Instructions 32bit Operands TICK F D 5-STAGE PIPELINE TICK F TICK E D F TICK M E D F TICK W M E D F TICK F D E M W M E ENHANCED HARVARD ARCHITECTURE D TICK F W M E TICK D F W M TICK E D F W PRE-FETCH QUEUE 64bits 64bits 64bits 64bits Holds 4 to 32 Instructions for Slower Memory WRITE BUFFER Buffer Only for Writes For Slower Memory CODE DATA Typically Flash Memory 64 Memory Interface 32 Typically SRAM 5 STAGES OF PIPELINE F = FETCH INSTRUCTION D = DECODE INSTRUCTION E = EXECUTE INSTRUCTION M = READ OR WRITE MEMORY W = WRITE BACK TO REGISTER 24

25 Five Stage Pipeline Parallel execution of instruction fetch and data memory access provides ideal execution rate of one clock cycle per instruction. 5 stages IF D E M WB IF D E M WB IF: Instruction Fetch D: Decode E: Execution M: Memory access WB: Write Back IF D E M WB IF D E M WB IF D E M WB Harvard architecture allows parallel execution 25

26 Out-of-Order Completion 5 Stage Pipeline and Out-of-Order Completion Example. RX efficiently executes the instruction. Order Completion MOV [R1], R2 ADD R4, R5 SUB R6, R7 IF D E M M M M WB IF D S S S S E WB IF S S S S D E WB Loss of instruction Out-of-Order Completion MOV [R1], R2 ADD R4, R5 SUB R6, R7 IF D E M M M M WB IF D E WB IF D E WB <<When there is no dependence in the following instruction>> The stall is not generated on the pipeline since it the next orders. IF: Instruction Fetch D: Decode E: Execution M: Memory access WB: Write Back S: Stall *The order of executing instruction 26

27 Rx Flash Technology Processing performance 90nm MONOS cell 1.5 Billion Flash MCU shipped Zero-Wait access up to 100MHz 2 wait cycles RX with 100 MHz flash Processing performance gap Competing MCU with 30 MHz flash 3 or more 1 wait cycle 30 MHz 100 MHz MCU operating frequency IF D E M WB IF D E M WB IF D E M WB IF D E M WB no wait IF W D E M WB IF W IF D E M WB W IF D E M WB W 1 wait cycle D E M WB IF W W D E M WB IF W IF W W IF D E M WB W W D E M WB W 2 wait cycle D E M WB 27

28 Single-Precision Floating-Point Unit The single-precision (32-bit) data format defined in IEEE 754* is supported. The exceptions defined in IEEE 754 are supported. Subtract, multiply, divide, and integer-convert instructions general registers are supported. Operation using dedicated data registers RX operation using general registers General registers No load/store instruction needed General register Load/store Floatingpoint unit Dedicated data registers Floatingpoint unit Effective when performing sequential calculations * IEEE Standard for Binary Floating-Point Arithmetic 28

29 RX-FPU Benchmarks Single precision operations are 1.5 times or more faster using FPU Single precision RX600 without FPU (Number of Cycle) RX600 with FPU (Number of Cycle) Comparison (No FPU/RX-FPU) Sinf Cosf Tanf Asinf 1, Acosf 1, Atanf Logf Expf Powf 5,

30 FPU Improves Performance We implemented sensorless vector control for 3-phase BLDC motor in RX62T Both, fixed point formulation as well as FPU based formulation were implemented and tested We also implemented full trig functions as well as table based trig functions to reduce the CPU bandwidth in both methods For trig functions, we used library approach with basic FPU instructions Tests were run at 10kHz carrier frequency We compared the performance of both in terms of CPU bandwidth and code size 30

31 FPU Improves Performance CPU Bandwidth and Code Size Comparison at 10KHz PWM Frequency for Sensorless Vector Control CPU Bandwidth Fixed-Point SVC FPU SVC Sine, Cosine, Atan functions 38% 23% Sine, Cosine, Atan tables 26% 18% Code Size Fixed-Point SVC FPU SVC Sine, Cosine, Atan functions K 7.222K Sine, Cosine, Atan tables K 6.221K 31

32 Peripheral Support 32

33 Multifunction Timer Unit 3 33

34 MTU3 For Motor Control MTU3 can generate two sets of 6 PWM outputs to control two motors Automatic dead time insertion Interrupt skip function for slow current loops ADC triggering during PWM period for current measurements Timer counter clock up to 100MHz Encoder and Hall sensor input measurements Protection Functions PWM output shut down by an external trigger Main clock stop detection PWM out put shut down Mode registers and counters not accessible by CPU when in operation (protection from CPU malfunction) Register data can be transferred by DTC Additional channels for related functions 34

35 Multi Function Timer Pulse Unit 3 MTU33 MTU3 Eight channels with 16 bit counters Maximum 24 pulse input/output, and 3 input Input clock up to 100MHz Operation Modes Output compare match (Low, High, Toggle) Synchronous operation: Multiple channels synchronized simultaneous clear by compare match or input capture PWM Mode: 0 to 100% duty PWM output Input capture event timing, Encoder counting ADC start, Interrupt generation, DMAC/DTC trigger MTU3 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 Encoder Input 3 Ph.PWM Output Input capture 3 ph PWM output 35

36 Multi Function Timer Pulse Unit 3 MTU33 MTU3 Motor Related PWM Output Ch 3 & 4 for first PWM set, Ch 6 & 7 for second PWM set Each set has six PWM output with automatic dead time insertion Types of PWM waveform Reset synchronous PWM mode: saw tooth PWM wave Complementary PWM mode: Triangle waveform Carrier period TGR3A Ch3 TGR3B Ch 4 PWM duty TGR4A TGR4B Offset = deadtime U phase PWM V phase PWM W phasepwm OFF OFF ON ON OFF OFF ON ON OFF Dead time 36

37 0/100% Duty PWM Output Example of 0/100% duty output in complementary PWM mode TGRA_3 TCDR Value of TGRB_3 TCNTS TCNT_3 TCNT_4 TDDR H'0000 TIOC3B TIOC3D 0% Value of TGRB_3 100% 0%duty: same as the value of TGRA_3 100%duty : H

38 Dead-time 0 Generate Ideal PWM Output without dead time Set 0 on Dead time Reg. TGR3A TGR3B TGR4A TGR4B TCNT3 TCNT4 U-phase V-phase W-phase TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D 38

39 MTU3 Double Buffer Function With two buffers, one for up counter and another for down counter, MTU3 can generate asymmetric PWM waveforms with reduced CPU overhead TGRA_3 TCDR *Temp -> timing of transferring TGRB_4 TDDR Buffer-A (for down counter) Buffer-B ((for up counter) ) Temp-A (for down counter) Temp-B ((for up counter) TGRB_4 (compare register) H'1111 H'1110 H'1111 H'1110 H'1110 H'1111 H'1110 H'1111 H'1110 H'1111 TIOC4B(out) TIOC4D(out) 39

40 Interrupt Skip Function To Reduce CPU Load on Interrupt Handling interrupt skip number can be set from 0 to 7 times interrupt skip request signal: TGI3A*Top* and TGI4V(Bottom* Ex. 1* Interrupt request signal*top end, skip number*2 times Interrupt request No interrupt Request Ex. 2* Interrupt request signal*bottom end, skip number*one time Interrupt request No interrupt Request No interrupt Request Usually, Current Loop frequency is not the same as PWM carrier frequency. This function is used when Interrupt every PWM period is NOT required. 40

41 Synchronizing A/D conversion with PWM Automatic generation of trigger Counter A/D conversion start trigger Time A/D conversion start trigger 41

42 ADC synchronization within PWM MTU can generate ADC Start Trigger for Motor Control Two sets of a register for generating trigger and its buffer register built-in Can work in conjunction with interrupt skip function TADCOR4x (MTU reg.) A/D start trigger Using Interrupt Skip Function Top end, skip number 2 times TADCOR4x (MTU reg.) A/D start trigger No interrupt & No trigger 42

43 Protection Functions for Inverter Unit 1. PWM Output shut- down by external trigger The 6-phase PWM output pins can be set automatically to high-impedance state by external signals 2. Halting of PWM Output when Oscillator is Stopped Upon detecting that the clock input to this LSI has stopped, the 6-phase PWM output pins are automatically set to the high-impedance state. 3. Register and Counter Miswrite Prevention Function This function can disable CPU access to the mode registers, control registers, and counters to prevent miswriting due to CPU runaway. In the access-disabled state, the applicable registers are read as undefined and writing to these registers is ignored. 43

44 PWM Output Shut down by External Trigger POE Function Input pins for Fault Signals from Power Module Can select falling edge or low level sampling respectively for detection PWM output can be set automatically to high-impedance To analyze the cause of fault/error condition, detection flag is available for each input pin If the selected edge or level is detected, interrupt is generated POE block diagram Input POE3 POE2 POE1 Digital Noise Filtering Circuit Falling edge detection circuit Low level detection circuit High Impedance control Interrupt request PWM Output CPU POE0 44

45 Speed & Position Detection Two-phase encoder pulse measurement Phase count mode/mtu 16 bit up/down counter Up/down count by detecting phase difference between A and B phase Count up/down condition is able to choose from four conditions (mode1 to 4) Can be utilized as automatic speed / location data measurement Automatic measurement of encoder pulse width Measurement can start every periodic cycle Can be used as 32 bit up counter Ch1 and ch2 can operate as 32 bit counter 45

46 Encoder Pulse Count Function - Example of phase count mode 1 - TCLKA or TCLKC TCLKB or TCLKD Counter value Count Up TCNT1 or TCNT2 Count Down Time 46

47 Speed & Position detection - Automatic speed/ Position detection - A Phase B Phase Edge Detect circuit Counter clock TCNT1(Up down counter) TGR1A Capture the value oftcnt1) TGR1B (Capture the value oftcnt1) Channel 1 Internal capture trigger signal TCNT0 (Interval timer) Compare match signal TGR0A (speed control period) Internal capture trigger signal TGR0CLocation control period TGR0B Capture the pulse width of counter clock of TCNT1) TGR0D (Buffer register of TGR0B) Channel 0 47

48 Break Time Part 2 to follow 48

49 ADC & Comparators 49

50 Features of 12bit AD Converter 2 units (AD0 and AD1), 4 channels per unit (Total 8 cha ) Each unit has the same functionality, independent operation Simultaneous sampling is possible for 1-3 input channels Conversion time depends on operating voltage 1.0µs per 1 to 5.5V and PCLK=50MHz 2.0µs per 1 to 4.0V and PCLK=50MHz Self-diagnostic functions Voltage can be generated internally (AVREFHx0V, AVREFHx1/2V, or AVREFH) Programmable gain amplifiers, 3 channels/unit Window comparators, 3 channels/unit 50

51 12bit A/D Configuration with PGA Unit 0 AN0 AN1 AN2 AN03/CVref L Each unit designed for one shunt or Three shunt current detection * OP OP OP External Reference Voltage 3 S/H for 3 shunt current detection Double data register for one shunt S/H S/H S/H Multiplexer S/H A/D ch0 Data Register Data Register ch1 Data Register ch2 Data Register ch3 Data Register Continuous AD Conversion for same channel Unit1 AN4 OP AN5 OP AN6 OP AN07/CVref H External Reference Voltage S/H S/H S/H Multiplexer S/H A/D ch0 Data Register Data Register ch1 Data Register ch2 Data Register ch3 Data Register Comparator Input *Choice of Gain *6ch, x 2.0/2.5/3.077/3.636/4.0/4.444/5.0/5.714/6.667/10.0/13.3 OpAmp can through when you do not needs 51

52 Comparator Configuration Each 12bit AD unit has three window comparators AN00 * OP Window Comparator ch0 12bit AD Unit 0 AN01 OP Window Comparator ch1 Timer (GPT) Input AN02 AN03/CVref L OP External Reference Voltage Window Comparator ch2 Comparator output Noise Canceller CPU Interrupt AN04 OP Window Comparator ch4 POE Circuit 12bit AD Unit 1 AN05 OP Window Comparator ch5 Upper side Reference AN06 AN07/CVref H OP External Reference Voltage Window Comparator ch6 Window Exceeding This level Lower side Reference Exceeding This level *Choice of Gain *6ch, x 2.0/2.5/3.077/3.636/4.0/4.444/5.0/5.714/6.667/10.0/13.333* Op Amp can through when you do not needs CPU interrupt or POE or timer input 52

53 Features of PGA On-chip op-amp (3 op-amp per AD unit: Total 6) Programmable gain: x 2.0, 2.5, 3.077, 3.636, 4.0, 4.444, 5.0, 5.714, 6.667, 10.0, and (11 steps in total) 3ch out of 4ch of 12-bit A/D incorporates the op-amp 12-bit A/D unit0 x bit A/D unit x 3: 6 in total The PGA can be skipped if not necessary. 53 Note1: Load capacitance of operational amplifier monitor terminal is up to 20pF and load resistance is below 1MΩ

54 Features of Comparators 6 Window comparators 2 Reference pins: high CVrefH and low CVrefL Comparison performed before or after OpAmp. (selectable) Comparator output enables several operations Link to POE and convert an output of specific timer to HiZ Interrupt to CPU and monitor active comparators Internally specifies C1 to C6 output and use them as GPT trigger Trigger signal (counter start, stop or clear, IC trigger or OC output forced change (High/Low/HiZ)) Output stage incorporates noise canceller. ADCLK cancels noise (to avoid sensitive reaction). Noise canceller is supported by digital filter. φ CLK, /2, /4, /8, /16, and /128 enables level sampling (x 16) 7 levels reference voltage for comparator - 1/8 to 7/8 AVrefh 54

55 General purpose PWM Timer (GPT) 55

56 General purpose PWM Timer (GPT) Design of GPT is based on the following functional capabilities Software PFC One shot PWM, start/stop control by external pin Power Supply Control AC/DC, DC/AC,DC/DC Independent chopping control needed for each phase Output compare with buffering Motor control timer 56

57 Block Diagram of GPT Clock Source ICLK Frame register with double buffer GTPDBR GTPBR GTPR Internal Comparator Output C1 to C6 CH0 CH1 CH2 CH3 Internal Bus Up Down Counter IC Comparator GTCCRA GTCCRB GTCCRC GTCCRD GTCCRE GTCCRF OC/IC register with buffers GTIOCA GTIOCB GTETRG GTADTRA GTADTRB GTDVU GTDVF GTADTBRAGTADTBRB GTDBU GTDBF GTADTDBRAGTADTDBRB AD Trigger register with buffers Dead time register with buffer Up slope/ Down slope Low speed OCO counter Counter Synchronous Circuit Low speed OCO LOCO counter Measured Value Measured Value Control Register Deviation Value Average 57

58 GPT Functionality Compare Match Output Frame period Register PWM Duty Register GTPR GTCCRA GTCCRB TCNT Saw tooth waveform GTIOCxA Ex. GTIOCxB Every compare match occur of GTCCR and counter, port will change High/Low/toggle* Ex.2GTIOCxA Every compare match of GTCCR and counter, Port will be high. And every frame, the port will be Low Buffer operation of compare match register G*CCRF G*CCRD Buffer register 2 TCNT G*CCRE G*CCRC G*CCRB G*CCRA Buffer register 1 Compare match register GTCCRD GTCCRC GTCCRA AA yy xx BB AA yy CC BB AA 58 ****

59 GPT Functionality Compare Match Output Frame period Register GTPR Triangle waveform PWM Duty Register GTCCRA GTCCRB Ex.1 Buffer operation of compare match register G*CCRF G*CCRD Buffer register 2 TCNT G*CCRE G*CCRC G*CCRB G*CCRA **** Buffer register 1 Compare match register GTCCRD GTCCRC GTCCRA AA BB AA CC BB AA 59

60 GPT Functionality Complementary PWM Frame period Register GTPR Triangle waveform PWM Duty Register GTCCRA GTCCRB (GTCCRA-GTDVU) PWM Duty (GTCCRA-GTDVD) Compare match register Ex.1 Buffer operation of compare match register Buffer register 2 Buffer register 1 Low Active PWM Duty G*CCRD G*CCRC G*CCRA **** Dead time Up Dead time G*BU G*DVU G*CCRB Up G*BD G*DVD Down (GTCCRA-GTDVU/D) Dead time Down TCNT GTCCRD GTCCRC GTCCRA dead time values for up counting and down counting can be specified individually AA BB AA CC BB AA 60

61 GPT Functionality Complementary PWM Frame period Register GTPR GTCCRA-GTDVD PWM Duty Register GTCCRD GTCCRC GTCCRC-GTDVU Saw tooth waveform PWM Duty Ex.1 Low Active Dead time Up Dead time Down PWM Duty end Buffer operation of compare match register PWM Duty G*CCRD Dead time G*BU G*BD TCNT PWM Duty start Compare match register G*CCRC G*CCRA **** G*DVU Up Internal register G*DVD Down GTCCRD GTCCRC GTCCRA AA BB AA CC BB AA 61

62 GPT Functionality Phase Shifting Timer synchronization Ex.1) Counter of CH0 Counter of CH1 Synchronous circuit CH0 CH1 CH2 CH3 GTIOC0A GTIOC0B GTIOC1A GTIOC1B GTIOC2A GTIOC2B GTIOC3A GTIOC3B Counter of CH2 Ex.2) Phase shift Counter of CH0 Counter of CH1 Counter of CH2 You can specify the timing by using another channel 62

63 Support for Standards 63

64 IEC60730 ** Requirements and Rx62T Hardware IEC60730 Item** Corresponding features of Rx62T Interrupt handling and execution Clock External communication Input/Output peripheral A/D converter Monitoring by Independent Watchdog Timer with Checker software. Clock stop detection and clock delay monitoring CRC(Cyclic Redundancy Check) on chip Port values are always readable even when pins are other peripheral function Provide three level (Avreff,1/2AV ref, AVrefss) for self test ** International fail safe standard ** Not all of IEC

65 Examples Peripherals Usage 65

66 3 Phase BLDC Motor with Hall Sensors Hall sensors are connected with Ch5 as shown It measures the count between each transition giving the speed Interrupt is generated for commutation ADC triggered by PWM for current measurement CMT or any other timer channel can be used for speed loop as well as current loop MTU3 ch3 ch4 3 Ph.PWM Output ch5 Hall sensor Input + ADC0 + CMT Current loop Alternatively Ch 6 and 7 can be used for PWM output And ADC1 can be used for current measurements 66

67 3 Phase BLDC Motor without Hall Sensors BEMF employed for control Comparators can be used to detect the zero crossing ADC measurements for current loop CMT or any other timer channel for speed and current loop MTU3 + ADC0 OR ADC1 ch3 ch4 OR ch6 ch7 Comparators & current loop 3 Ph.PWM Output 3 ph PWM output + CMT 67

68 3-Phase BLDC Motor with Digital Encoder Set up ch 3 and 4 to generate 3-phase PWM Alternate is ch 6 and 7 for the PWM output Use ch 1 or ch 2 for digital encoder inputs CMT or any other timer channel for speed and current loop timings MTU3 + ADC0 OR ADC1 ch1 ch2 ch3 ch4 OR ch6 ch7 Current Measurements Digital Encoder Input 3 Ph.PWM Output Alternate PWM + CMT 68

69 3-Phase BLDC Motor with Resolver Set up ch 3 and 4 to generate 3-phase PWM Alternate ch 6 and 7 for PWM output Operation Mode: Output Compare in Toggle mode, complementary with dead time insertion Use ADC0 or ADC1 for Resolver inputs ch3 ch4 3 Ph.PWM Output MTU3 OR ch6 ch7 3 ph PWM output + ADC0 OR ADC1 Resolvers + CMT 69

70 Two 3-phase Motors Advanced Analog 12-bit ADC with 8-channels and 1µs conversion time per channel 6 Programmable Op Amps 6 Sample/Hold circuits 6 Window comparators CAN Analog RX62T Analog S/H PGA 12-bit ADC Comparator Detection Circuit Motor Current 3 Fan Motor GPIO Timers Timer PWM Generation PWM Interrupt 6 PWM Output Fault Signal Advanced timers PWM Generation using MTU3 (Multi-function Timer Unit) and GPT (General Purpose Timer) PWM Interrupt using Port Output Enable function Analog S/H PGA 12-bit ADC Comparator Detection Circuit Motor Current 3 Compressor Inverter Timer PWM Generation PWM Interrupt 6 PWM Output Fault Signal 70

71 Two 3-phase 3 Motors with Sensors Set up ch 3 and 4 to generate first set of 3-phase PWM Set up ch 6 and 7 for the second set Input clock typically 50 MHz, carrier freq 20kHz Operation Mode: Output Compare in Toggle mode, complementary with dead time insertion Sensor based implementation Use channel 5 for Hall sensor inputs Use ch 1 or ch 2 for digital encoder inputs Use ADC0 and ADC1 for Resolver inputs ch0 ch1 ch2 ch3 ch4 MTU3 ch5 ch6 ch7 + ADC0 + ADC1 Current loop Digital Encoder Input 3 Ph.PWM Output Hall sensor Input 3 ph PWM output + CMT 71

72 Two 3-phase 3 Motors Sensorless Set up ch 3 and 4 to generate first set of 3-phase PWM Set up ch 6 and 7 for the second set Input clock typically 50 MHz, carrier freq 20kHz Operation Mode: Output Compare in Toggle mode, complementary with dead time insertion Sensorless implementation Set up ADC0 for one motor and ADC1 for second motor Trapezoidal method can use comparators for zero cross Vector control can use current measurements for flux and angle estimation MTU3 ch3 ch4 ch6 ch7 + CMT Trigger ADC0 3 Ph.PWM Output 3 ph PWM output Trigger ADC1 72

73 GPT in 3-Phase Motor Control Three channels of GPT can be synchronized and used in complementary mode to generate complete set of PWM for a 3 phase motor Timer synchronization Synchronous circuit CH0 CH1 CH2 CH3 GTIOC0A GTIOC0B GTIOC1A GTIOC1B GTIOC2A GTIOC2B GTIOC3A GTIOC3B Ex.1) Counter of CH0 Counter of CH1 Counter of CH2 73

74 GPT in Power Supply Control Compare Match Output using saw tooth waveform PWM with cycle by cycle TCNT AA BB CC GTCCRD GTCCRC GTCCRA AA BB AA BB AA CC DD CC BB EE DD CC EE DD FF Comparator Or Trigger Internal timer Output Final output wave form when over current is detected, the PWM output is shut off during every carrier period 74

75 GPT in PFC Control Compare Match Output using saw tooth waveform One shot pulse mode PWM with comparator start TCNT GTCCRD GTCCRC GTCCRA Comparator Output Initialize BB AA Operation start BB AA CPU interrupt AA BB Write DD CC BB DD CC CC DD DD FF EE EE EE FF FF Final output wave form Every zero cross timing, GPT starts one shot PWM waveform as shown. 75

76 GPT in Interleaved PFC Three channels of GPT can be phase shifted to generate proper PWM output for each interleaved PFC wave form Timer synchronization Synchronous circuit GTIOC0A CH0 GTIOC0B GTIOC1A CH1 GTIOC1B GTIOC2A CH2 GTIOC2B GTIOC3A CH3 GTIOC3B Ex.2) Phase shift Counter of CH0 Counter of CH1 Counter of CH2 You can specify the timing by using another channel 76

77 GPT in Main Clock Monitoring Main Clock Monitoring function overview This function measure the LOCO clock period using internal count clock as source. Every period, the value is written in LCNT registers. There are 16 such registers to store the values (LCNT0 to 15). Always latest 16 values are kept in those resisters like a FIFO Average value of 16 measurements is calculated in Average register (by summation of LCNT0 to 15 and 4bit shift) Firmware can set the acceptable value in compare register. When the measured average value is different compared to acceptable value, GPT generates an interrupt to the CPU. LOCO *IWDT must be in operation Divider 1/1 1/16 1/128 1/256 GPT count clock LOCO counter Measurement result 0 Measurement result 1 Measurement result 2... Measurement result 15 Average Deviation acceptable value Measurement finish interrupt Interrupt 77

78 Many Combinations Are Possible Rx family provides basic structure to have many combinations possible MTU3 ADC0 and ADC1 GPT CMT Comparators DTC 78

79 Summary Rx62T is a special semiconductor design that provides complete motor control capability CPU combined with FPU provides unique ability for algorithm implementation and execution MTU3 + ADC + protection functions are extremely helpful Comparators and PGA provide enhanced capability to create differentiated solutions DTC reduces CPU load and helps design better firmware architecture 79

80 Questions? 80

81 Questions Question 1: Is it possible to control two motors and also implement PFC using one MCU? Answer 1: Yes, if Renesas devices such Rx62T and SH7216 are used. 81

82 Thank You! 82

83 Appendix 83

84 Features of MTU3 (compared with MTU2 & MTU2S MTU3 is able to control two motors Ch0 Ch1 MTU2 Ch2 (50MHz) Ch3 Ch4 Ch5 MTU2S Ch3 (100MHz) Ch4 Ch5 PWM(Output compare), Input Capture, buffer operation PWM(Output compare), Input Capture, Encoder count mode, Two 16bit or One 32bit counter PWM(Output compare), Input Capture, buffer operation 3p. PWM for motor control with single buffer Input capture, Pulse wide measurement for dead time compensation PWM(Output compare), Input Capture, buffer operation 3p. PWM for motor control with single buffer Same with ch5 of MTU2 MTU3 (100MHz) Ch0 Ch1 Ch2 Ch3 Ch4 Ch5 Ch6 Ch7 Compatible Compatible Improved function Double buffer for PWM duty Compatible Improved function Double buffer for PWM duty MTU 2S Complementary PWM with Single buffer 50MHz resolution with every carrier duty setting MTU 3 Complementary PWM with Single buffer Duty setting 100MHz resolution With every half carrier duty setting (CPU load is higher) 100MHz resolution With every carrier duty setting (CPU load is lower than previous) 87

85 Wait Cycle Delays When there is no wait, the pipeline continues to operate at its efficiency When there is a wait in memory access, it impacts fetch operation for sure, and then for some instructions it creates additional pipeline stalls as shown in second figure This is the reason why performance slope changes. IF D E M WB IF D E M WB IF D E M WB IF D E M WB no wait IF W D E M WB IF W IF D E M WB W IF D E M WB W 1 wait cycle D E M WB IF W D E M W WB IF W D S E M WB IF W IF S W 1 wait cycle D E M WB S D E M WB 88

86 Renesas Electronics America Inc.