< HVIC > M81748FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER

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Shauna Hopkins
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1 < HIC > DESCRIPTION is 1200 high voltage Power MOSFET and IGBT module driver for half bridge applications. FEATURES Floating supply voltage up to 1200 Low quiescent power supply current Sink and source current output up to ±2A (typ) Active Miller effect clamp up to 2A (typ) Input noise filters (,,) Desat detection and protection with output soft shutdown Under voltage lockout Synchronization signal to synchronize shutdown with other phases APPLICATIONS Power MOSFET and IGBT gate driver for Inverter or general purpose. PIN CONFIGURATION (TOP IEW) NC 1 24 NC NC 2 23 NC HDESAT NC B HCLAMP C NC LDESAT S 9 16 LO NC LCLAMP NC PGND NC GND Outline:24P2Q SSOP-Lead PACKAGE BLOCK DIAGRAM H Levelshift Filter B Interlock Noise Filter Oneshot U+POR Desat Protection Miller Clamp Soft Shutdown HCLAMP HDESAT GND Filter H Reverse Levelshift S LO Delay C timer POR Desat Protection Miller Clamp LCLAMP LDESAT Noise Filter Protection Soft Shutdown PGND 1

2 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings indicate limitation beyond which destruction of device may occur. All voltage parameters are absolute voltage reference to GND and PGND unless otherwise specified. Symbol Parameter Test conditions Raitings Unit B High side floating supply absolute voltage -0.5~1224 S High side floating supply offset voltage B -24~ B +0.5 BS High side floating supply voltage BS =B- S -0.5~24 High side output voltage S -0.5~ B +0.5 HCLAMP High side CLAMP input/output voltage S -05~ 0.5 B +0.5 HDESAT High side DESAT input/otuput voltage S -0.5~ B +0.5 CC Low side fixed supply voltage -0.5~24 LO Low side output voltage -0.5~ CC +0.5 LCLAMP Low side CLAMP input/output voltage -0.5~ CC +0.5 LDESAT Low side DESAT input/output voltage -0.5~ CC +0.5 IN input voltage, -0.5~ CC +0.5 input/output voltage -0.5~ CC +0.5 d S /dt Allowable offset voltage slew rate S GN ND and PGND ±50 /ns Pd Package power dissipation Ta= 25 C,On our standard PCB ~1.11 W Kθ Linear derating factor Ta 25 C,On our standard PCB ~11.1 mw/ C Rth(j-a) Junction-ambient air thermal resistance On our standard PCB ~90 C/W Tj Junction temperature -40~125 Topr Operation temperature -40~105 Tstg Storage temperature -55~150 TL Solder reflow condition Pb-freee 255:10s, max260 RECOMMENDED OPERATING CONDITIONS For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND and PGND unless otherwise specified. Symbol Parameter Test conditions Limits Min. Typ. Max. Unit B High side floating supply absolute voltage S S +15 S S High side floating supply offset voltage BS > BS High side floating supply ppy voltage BS = B - S High side output voltage S - S HCLAMP High side CLAMP input/output voltage S - S HDESAT High side DESAT input/output voltage S - S CC Low side fixed supply voltage LO Low side output voltage 0 - CC LCLAMP Low side CLAMP input/output voltage 0 - CC LDESAT Low side DESAT input/otuput voltage 0 - CC IN input voltage,, 0 - CC input/output t t voltage 0 - CC PERRMANCE CURES n Pd (W) Pa ackage Power Dissipatio Thermal Derating Factor Characteristics Ambience temperature ( ) 2

3 TYPICAL CONNECTION P HDESAT GND B To Controller 5~15 HCLAMP S LDESAT To Load To Controller and other phase's LO LCLAMP Emitter C PGND N(Power GND) Note: If HIC is working in high noise environment, it is recommended to connect a 1nF ceramic capacitor to pin. It is recommended to connect PGND pin to Emitter and Power GND(N). If PGND pin is not connected to Power GND(N), please pay attention to a noise between PGND pin and Power GND(N). 3

4 ELECTRICAL CHARACTERISTICS (Ta=25 C, CC = BS (= B - S )=15, unless otherwise specified) Symbol Parameter Test conditions Limits Min. Typ. Max. Unit I FS High side leakage current B = S = ua I BS BS quiescent supply current = = ma I CC CC quiescent supply current = = ma OH High level output voltage I O = 20mA,, LO OL Low level output voltage I O = -20mA A,, LO IH High level input threshold voltage, IL Low level input threshold voltage, I IH High level input bias current IN = ma I IL Low level input bias current IN = ma tfilter Input signals filter time on-pulse off-pulse on-pul se ns ns ns off-pulse off-pulse ns ns HCT High side active Miller clamp NMOS input threshold voltage IN = LCT Low side active Miller clamp NMOS input threshold voltage IN = OL Low level output voltage I = 1mA IH IL BSuvr BSuvt BSuvh BS supply U hysteresis voltage BSuvh = BSuvr- BSuvt t BSuv LPOR I OH Output high level short circuit pulsed current (LO) = 0, IN = 5, PW 10μs A I OL1 Output low level short circuit pulsed current (LO) = 15, IN = 0, PW 10μs A I OL2 High level input threshold voltage Low level input threshold voltage BS supply U reset voltage BS supply U trip voltage BS supply U filter time us Low side POR trip voltage Active Miller clamp NMOS output low level HCLAMP(LCLAMP) = 15, IN = 0, PW 10μs A short circuit pulsed current tdlh() High side turn-on propagation delay short to HCLAMP, CL = 1nF us tdhl() High side turn-off propagation delay short to HCLAMP, CL = 1nF us tdlh(lo) Low side turn-on propagation delay LO short to LCLAMP, CL = 1nF us tdhl(lo) Low side turn-off propagation delay LO short to LCLAMP, CL = 1nF us tr Output turn-on rise time CL = 1nF ns tf Output turn-off fall time CL = 1nF ns ΔtdLH Delay matching, high side turn-on and low side turn-off tdlh()-tdhl(lo) us ΔtdHL Delay matching, high side turn-off and low side turn-on tdlh(lo)-tdhl() us Note: Typ. is not specified. 4

5 ELECTRICAL CHARACTERISTICS (Ta=25 C, CC = BS (= B - S )=15, unless otherwise specified) Limits Symbol Parameter Test conditions Unit Min. Typ. Max. I CHG Blanking Capacitor Charging Current DESAT = ma I DSCHG Blanking Capacitor Discharge Current DESAT = ma DESAT DESAT Threshold t DESAT(90%) DESAT Sense to 90%O Delay CL = 1nF us t DESAT(10%) DESAT Sense to 10%O Delay CL= 1nF t DESAT(FAULT)_H t DESAT(FAULT)_L t DESAT(LOW) HDESAT Sense to Low Level FAULT Signal Delay LDESAT Sense to Low Level FAULT Signal Delay DESAT Sense to DESAT Low Propagation Delay R F = 15kΩ R F = 15kΩ t timer C=1nF Note: Typ. is not specified us us us C DESAT = 1nF us us 5

6 FUNCTION TABLE (Q: Keep previous status) t HDESAT LDESAT BS / (Input) U L L - L L H L L H - L L H L H L - L L H H H H - L L H L H X - H X H L X H - X H H L X X L X X X L X H - L L L L LO (Output) Behavioral status L H H H L H L H Interlock active L L Hige side DESAT L L Low side DESAT L - Output shuts down when = L H H BS power reset is tripping when = H Note1 : L status of BS /U indicates a high side U reset condition. Note2 : In the case of both input signals ( and ) are H, outputt signals ( and LO) become L. Note3 : X () : L H or H L. Other : H or L. Note4 : Output signal () is triggered by the edge of input signal. Note5 : Please see FUNCTIONAL DESCRIPTION 7(p.9) for detailed sequences of desaturation. FUNCTIONAL DESCRIPTION 1. INPUT/OUTPUT TIMING DIAGRAM 50% 50% tr tf tdlh() 90% td HL() 90% 10% 10% LO tdlh 90% tdlh(lo) tdhl tr 90% tdhl(lo) tf 10% 10% 6

7 2. INPUT INTERLOCK TIMING DIAGRAM When the input signals (/) are high level at the same time, the outputs (/LO) shuts down. Note1 :The minimum input pulse width at / should be to more than 500ns (because of / input noise filter circuit). Note2 :Delay times between input and output signals are not shown in the figure above. 3. INPUT TIMING DIAGRAM When is pulled down to low level in case the of other phases becomes low level (fault happened) or the MCU/DSP sets to low level, the outputs (UT, LOUT) of the driver will be shut down. As soon as goes high again, the output will respond to the following active input signal. UT LOUT Note1 :Delay times between input and output signals are not shown in the figure above. Note2 :The minimum pulse width should be more than ns (because of input filter circuit). 7

8 4. LOW SIDE CC SUPPLY POWER RESET SEQUENCE When the CC supply voltage is lower than power reset trip voltage, the power reset gets active and the outputs (LOUT) become L. As soon as the CC supply voltage goes higher than the power reset trip voltage, the outputs will respond to the following active input signals. POR voltage UT LOUT Note1 :Delay times between input and output signals are not shown in the figure above. 5. HIGH SIDE BS SUPPLY UNDER OLTAGE LOCKOUT SEQUENCE When BS supply voltage drops below the BS supply U trip voltage and the duration in this status exceeds the BS supply U filter time, the output of the high side is locked. As soon as the BS supply voltage rises above the BS supply U reset voltage, the output will respond to the following active signal. BSuvr BSuvr BS BSuvt BS supply U filter time BS supply U hysteresis voltage UT LOUT Note1 :Delay times between input and output signals are not shown in the figure above. 8

9 6. POWER START-UP SEQUENCE At power supply start-up the following sequence is recommended when bootstrap supply topology is used. (1). Apply CC. (2). Make sure that is at high level. (3). Set to high level and to low level so that bootstrap capacitor could be charged. (4). Set to low level. l LOUT Note : If two power supply are used for supplying CC and BS individually, it is recommended to set CC first and then set BS. 7. DESATURATION DETECTION AND HIGH CURRENT PROTECTION HDESAT(LDESAT) detects the IGBT ce voltage. When the IGBT is ON and the DESAT voltage exceeds DESAT threshold voltage, (LO) output slowly falls to a low level to softly turn-offf the IGBT and prevent high di/dt noises. And output falls to a low level to transmit the fault signal to the micro controller. Once the fault condition is detected, all input signals are ignored during the t period to complete the soft shutdown. () t DESAT(LOW) HDESAT (LDESAT) DESAT Threshold 50% t BLANK t DESAT(10%) (LO) 90% 10% t DESAT(90%) 50% 50% t DESAT(FAULT) t 9

10 8. ACTIE MILLER EFFECT CLAMP NMOS OUTPUT TIMING DIA AGRAM The structure of the output driver stage is shown in following figure. This circuit structure employs a solution for the problem of the Miller current through Cres in IGBT switching applications. Instead of driving the IGBT gate to a negative voltage to increase the safety margin, this circuit structure uses a NMOS to establish a low impedance path to prevent the self-turn-on due to the parasitic Miller capacitor in power switches. BS/ PG High dv/dt IN=0 (from /) /LO OUT Cres HCLAMP /LCLAMP Cies N1G N2G S/PGND Active Miller Clamp NMOS When / is at low level and the voltage of the OUT (IGBT gate voltage) is below active Miller effect clamp NMOS input threshold voltage, the active Miller effect clamp NMOS is being turned on and opens a low resistive path for the Miller current through Cres. IN PG P1 ON P1 OFF P1 ON N1G N1 OFF N1 ON N1 OFF OUT Active Miller clamp NMOS input threshold voltage N2G N2 OFF N2 ON N2 OFF Tw Active Miller effect clamp NMOS keeps turn-on if T W does not exceed active Miller clamp NMOS filter time 10

11 INTERNAL DIODE CLAMP CIRCUITS R INPUT AND OUTPUTPINS LO LCLAMP LDESAT GND PGND GND B B HCLAMP HDESAT C S GND ENIRONMENTAL CONSCIOUSNESS is compliant with the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment ( RoHS) directive 2011/65/EU. PACKAGE OUTE 11

12 Main Revision for this Edition Revision No. Date Pages Points A 3, Feb New making 12

13 Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammablematerial l or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer s s a pplication; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third- diagrams, charts, programs, algorithms, or party s rights, originating in the use of any product data, circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page ( When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or re-export contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein MITSUBISHI ELECTRIC CORPORATION. ALL RIGHTS RESERED. 13

< HVIC > M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER

< HVIC > M81738FP 1200V HIGH VOLTAGE HALF BRIDGE DRIVER < HVIC > DESCRIPTION is 1200V high voltage Power MOSFET and IGBT module driver for half bridge applications. PIN CONFIGURATION (TOP VIEW) FEATURES Floating supply voltage up to 1200V Low quiescent power