Predicting Circuit Performance Using Circuit- level Statistical Timing Analysis

Transcription

1 Predicting Circuit Performance Using Circuit- level Statistical Timing Analysis Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, and M. Ray Mercer Department of Electrical and Computer Engineering The University of Texas at Austin Austin, Texas Abstract Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a methodology for statistical timing analysis. We present a triple-node delay model which inherently captures the effect of input transition time on the gate delays. Response Surface Methods are used so that the statistical gate delays are generated efficiently. A new path sensitization criterion based on the minimum propagatable pulse width (MPPW) of the gates along a path is used to check for false paths. The overlap of a path with longer paths determines its statistical significance to the overall circuit delay. Finally, the circuit delay probability density function is computed by performing a Monte Carlo simulation on the statistically significant path set. 1 Introduction Timing analysis is an essential step in the processes of designing, optimizing, and testing integrated circuits. It is used to determine whether a circuit will operate at a certain speed, and, more importantly, to identify portions of the circuit that do not meet timing specifications. Circuit simulation, though extremely accurate, is prohibitively expensive for large circuits in terms of computation time. In contrast, the efficient unit delay model or the fixed-gate delay models used in many timing analysis tools often yield erroneous results. Since the delay of a circuit can be extremely sensitive to errors in component delays, the use of more accurate delay models leads to a better estimate of the circuit delay. On the other hand, accuracy is not so important as hithert o believed since manufacturing process variations lead to deviations in component delays very similar to those due to inaccurate component delay estimation. Deterministic timing analysis, therefore, is insufficient for reliable estimation of circuit delays since it cannot effectively model thv deviations in component delays due to process parameter - inter- and intra-die - variations. During production This work was supported in part by the Semiconductor Research Corporation under contracts 92-DP-142 and 93-DJ- 343, the Advanced Research Program Agency under contract DAAL1-93-I<-3317 administered through the Army, the Innovative Science and Technology Office of Strategic Defense Initiative Organization under contract N administered through the Office of Naval Research, IBM Corporation, and the National Science Foundation under contract MIP these component delay deviations can be as high as 3%. False paths further complicate this problem since a small change in a component delay can cause a false path to become functional, and vice versa. This becomes more evident in highly optimized circuits where the longest path delays are nearly equal. Statistical timing analysis has, therefore, been considered in order to alleviate these problems [2, 3, 4, 51. In this paper, we develop a method for determining the probability density function (pdf) of the delay of a combinational circuit. It is shown that the accuracy of this computation is greatly enhanced by using realistic delay distributions. While calculating the overall circuit delay distribution, we not only consider the contribution of the longest path but also that of the statistically significant path set. False paths are excluded from the process by applying a new sensitizability criteria based on the notion of the minimum propagatable pulse width (MPPW) of the gates along a path, which has been developed by observing circuit behavior at the physical level. Sensitizable paths are classified as being either pulse propagation paths or edge propagation paths depending on the type of events they can propagate. The flowchart in Figure 1 summarizes our approach. 2 Delay Modeling Since accurate statistical delay models require a transistor-level description of the circuit we begin with a SPICE netlist description of the circuit which is parsed by the timing analyzer. The transistors are then clustered into DC coupled groups of components (DCCS). Each DCC is then analyzed symbolically to determine Its Boolean function with respect to its inputs using a technique similar to that presented in [7]. This data is used extensively in precharacterizing the delay models and later in sensitizing paths. Given the DCCs (gates), we can now proceed with their statistical delay precharacterization. 2.1 Triple-node path delay descriptions Because of the interconnect effects, the delay along a path through a gate is more accurately described from the input of a gate to the input of the next gate along the path. For example, in Figure 2, we associate a delay with the subpath 5-6 instead of 5-6 because of the interconnect present along 6-6. Given the shape of the waveform at 6, the RC interconnect delay along 6-6 can be accurately determined using AWE [12]. The gate delay, however, is more troublesome to compute $ IEEE 332

2 input 4 swkching G2 Raharscedze d(1-5-6) - dr,l.5) + d(l.5.6) d(4-5-6) - dr.4.5) + d(4.5.6) Figure 2: Precharacterizing a path delay I -p Figure 1: Flow chart of the approach The gate delay is largely a function of its load and input signal transition time. The load is accurately modeled by considering the interaction of the gate and a CzRCldriving-point admittance model of the interconnect as described in [Ill. The input signal slope effect, however, is not so easily precharacterized as the loading effect. For example, in Figure 2, when determining the delay along 5-6, the delay of gate G2 is strongly dependent on the rise (or fall) time of the signal at the input node 5. The rise time at node 5 is, in turn, strongly dependent on which input of gate GI caused this event. If input 1 connects to the topmost transistor of the N-channel pull-down path of gate GI, and input 4 to the bottom-most N-channel transistor, depending on whether input 1 or input 4 is switching, the rise time at the output of G1 can vary by 3-4 % for a submicron CMOS technology. Hence, the delay along 5-6 may depend strongly on which input of gate G1 is switching. This effect is easily modeled using a trzple-node description for the input-pin to input-pin delays. The delay from an input a to a consecutive input b is expressed in term of the triples (zt, a, b) where z, is an input node of the gate whose output is a. In Figure 2, the delay along path 5-6 has four different values for each input of gate G1. d(l,5,6), d(2,5,g), d(3,5, G), and d(4,5,6). If we weie calculating the delay along a path which includes subpath , the delay from 5 to 6 would be calculated using d(3,5,6). We should point out that the output transition time of gate G1 and, therefore, the delay of gate G2, is also a function of the input slope to gate GI. However, for a particular input node of gate G1, the transition (rise/fall) time at node 5 is largely independent of the transition time at that node. Because of the high-gain behavior of CMOS gates, the transition time at node 5 is strongly dependent on which input of gate G1 is switching and not on the transition time at the switching input. Hence, higher order tuple descriptions are not necessary to capture slope effects - a triple-node delay description is adequate. 2.2 Stat istical precharacterization Delay precharacterization of a circuit for statistical timing analysis is inherently expensive since it involves obtaining the probability density function (pdf) of the delay for each triple-node combination in the circuit. This involves performing a timing simulation of the minimal subcircuit which contains the nodes of a triple-node combination a statistically significant number of times, varying the factors affecting delay simultaneously during each simulation. The computationally-expensive problem of the multiple timing simulations required to obtain the delay pdf of a triple-node combination is overcome by approximating the delay using response surface method (RSM) techniques [9]. RSM methods model the output response of a system as a simple function (a surface in n-dimensional space) of the factors affecting the system performance. In our case, the output response of interest is the delay along a path ancl the factors affecting the delay are the process parameters, the geometry of the layout, and the interconnect load at the output of a gate. If XI, XZ, XJ,..., X, are the factors affecting delay, a first-order RS of the delay would be deluy=bo+blx1 +bzxz+b3x3+~~' +b,x, (1) The above approximation is equivalent to fitting a straight line for a single-variable function. The constants of this fit, bo, bl, bz,..., b,, can be determined by sampling the output response for appropriately chosen values of the input variables. In [l], it is shown that the variation in the performance of a MOSFET can be attributed to four factors: the gate oxide thickness, to,, the flatband voltage, Vfb, and the length and width of the transistor. To model interconnect variations, we add a fifth factor: the width of interconnect lines, W,nt. Since these factors are determined at different stages of the manufacturing process they are statistically independent [l]. 333

3 We use the method described in [lo] to obtain the constants b, for a second-order RSM which involves performing 21 different timing simulations using a quasi-static forward Euler approach [8] (which offers a 4X speedup over SPICE) of the minimal subcircuit containing the nodes of the triple-node combination. Statistical tests are applied to check the significance and validity of the constants. Insignificant constants are discarded. The error obtained using this approximation does not exceed 5%. Having obtained a simple closed-form expression for the triple-node delay in terms of the five fundamental process variables, a Monte Carlo simulation of 5 runs is performed. Randomly-generated values of t,,, Vfb, W, L, and Lb', (assuming a normal distribution) are substituted in the RSM equation to obtain a delay distribution. A Gausslan fit is then applied to the resulting distribution so that each triple-node delay can be statistically described by a mean and standard deviation value. This process is repeated for each triple node combination in the circuit. The precharacterization phase can be accelerated using lookuptable based techniques. 3 Path Modeling After a triple-node delay graph is constructed, we proceed with the selection of paths which determine the overall circuit delay pdf. Paths are enumerated in nonincreasing order of delay, and sensitized. The delay pdfs for the long paths in the circuit are then calculated. We select only those paths whose contribution to the overall circuit delay is considered statistically significant. Once the set of significant paths has been determined, we combine them to create the circuit delay pdf. Each step is explained in detail below. 3.1 Graph construction In order to efficiently handle paths and their delays, we use a graph representation of the circuit. First, the inputpin to input-pin graph is constructed based on the connectivity of the components in the circuit. Next, a graph transform is applied to handle unequal rising/falling delays [15]. Then the graph is modified to accommodate the triple-node delay model. Starting from the primary output arcs, every arc with multiple fanins is duplicated once for each fanin and assigned a weight (delay information) corresponding to the fanin. A copy of the original input pin to input pin graph is also kept because the modified graph is usually much larger and can be cumbersome for operations such as sensitization. 3.2 Path enumeration and sensitization Path selection starts with enumerating the longest topological path using the maximum (mean + 4. standard deviation) values of the delay pdfs, followed by sensitizability analysis and significance checking. This procedure is repeated until all significant paths are found. It is usually not possible to predict the number of these paths in advance, which precludes the usage of certain type of path enumerators. For our purpose, an incremental path enumerator, which can efficiently enumerate paths in non-increasing order of their delay is used [13]. For the purpose of path sensitization checking, we apply a sensitization criteria similar to [14] and, additionally, apply a minimum propagatable pulse width condition (to be described in Section 3.3.2). 3.3 Path delay pdf computation Edge paths and pulse paths We define the notion of edge-paths and pulse-paths based on their capability of propagating an event. If a path can propagate an edge (i.e. single rising or falling transition) we call it an edge-path. If it can propagate only a pulse, it is called a pulse-path. If it can do neither, it is called a false path. Edge-paths and pulse-paths have different pdfs. If the delay components are independent, an edge-path delay is the sum of the component random delay variables along the path. In addition, since the delay components have Gaussian distributions, the path delay pdf is given by: However, if the delay components are not independent, the path delay pdf can be calculated from the joint pdf of the delay components. In contrast, a pulse path occurs when a non-sensitizing signal arrives at a gate after an edge has already propagated through that gate. The pulse width is defined as the difference in arrival times of the original edge and the late side input signal. The delay of a pulse path is defined as the sum of the arrival time for the late input and the delay through the remainder of the path. The difference in the edge-path and pulse-path pdfs arises from the necessary condition for a pulse to occur. Specifically, the arrival time at the side input of a gate along a pulse path must be greater than the arrival time of the path input. Let S be the set of side inputs at a gate along a pulse path and AT(() be the arrival time of a non-sensitizing side input i E S. D,, the delay of the pulse path is then defined as: where F and L &re the delay of the path up to the conflicting gate, and the delay of the remainder of the path, respectively. A pulse path may have any number of late side inputs. To model multiple late side inputs, it is necessary to recursively apply Equation (3) to determine F and L. Since a direct solution to Equation (3) does not exist, simulation is recommended to evaluate the pdf Minimum propagatable pulse width There are physical effects to consider when examining pulses. It is well understood that gates have inertial delays which can attenuate pulses or possibly filter them out completely. Previous attempts to model this phenomenon [6] have considered only the elimination of instantaneous or zero width pulses. However, by using realistic delay values and the precharacterization process described previously, the minimum propagatable pulse width (MPPW) for a delay arc can be computed empirically and used to correctly model the circuit response. 334

4 AT+$$# (.) if no longer edge-paths have been found, the path is considered significant. All subsequent edge paths are compared to this first and longest edge-path. Let PI be the first and longest edge-path, P, be the current edge-path. Let Psubl be the portion of PI that does not belong to P,, and Psubr be the portion of Pi that does not belong to PI. Let Fl be the delay probability distribution function (PDF) of Pa,& and F, be the delay PDF of PSub1. Since they share no common component delays, they are statistically independent and the joint PDF is the product of the two PDFs. Thus the probability that both paths have delay of at most z can be written 1 a Delay" (b) Figure 3: (a) An example circuit with pulse path (b) Pulse path delay pdf MPPW can be used in statistical timing analysis to reduce the observable delays of the pulses.' If the maximum pulse width for a pulse path is less than the MPPW of the path, the path is not sensitizable. If w is the maximum MPPW for the delay arcs in L, then we can rewrite the delay distribution of a pulse D, as: D,={ min(at(z)) + L if min(at(i)) < F + w otherwise A typical pdf of this form is shown in Figure 3. The impulse covers over 6% of the area under the pdf curve. Notice that the non-zero portion of the delay pdf is nearly normal, but is slightly irregular since the observability condition depends on a portion of the delay itself. 3.4 Selecting the path set The objective of this analysis is to compute the total circuit delay pdf. Yet knowing how to find the pdf for a particular path or even a set of paths is not enough to calculate the circuit delay pdf. To calculate the circuit pdf, the relevant subset of the paths must first be selected. Since a circuit can have an exponential number of paths, it is important to select only those paths which can realistically affect the circuit response. Otherwise, the number of paths can be prohibitive. Essentially, when we compare a path for statistical significance to another path, we only need to consider the portions of the paths which are not common to both. Once a sensitizable path has been found and its delay pdf calculated, the question is whether it is significant with respect tu the overall circuit delay pdf. First, given an edge-path, Analogously, applying the concept of minimum pulse width to discrete timing analysis can reduce the number of observed pulses significantly. In one experiment using the ETA tool [8], the MPPW was used to eliminate over half of the potential pulses in the ISCAS c432. This experiment clearly demonstrated that false signals can be discarded in a large percentage of cases based solely on MPPW. (4) P(Psub1 < Z and Psubr < 2) = P(Psub1 < 2). P(P5ubt < 2) = FI(z). F~(I) (5) Let u1 and U, be the standard deviations of F1 and F,, respectively. If the mean of F, is more than 2(al + U,) below the mean of F1, then we say that the product is approximately equal to F1 and that the path F, is not significant. A pulse-path is considered significant if the path would be considered significant under the edge-path criterion. In other words, if the side input condition of the pulse path were ignored and the path was found to be significant, then the pulse path is significant. This assumption keeps the set of statistically significant paths conservative. 3.5 Circuit delay pdf computation The circuit delay pdf is the density of the delay of the maximum delay path of the circuit (this path can be different for different values of component delays). We approximate this by the pdf of the maximum delay path of the significant path set. If the pdfs of the paths in the significant path set are not independent, then in order to compute the circuit delay pdf we have to evaluate the joint pdf of the paths in the path set. If we assume that the individual path delays are Gaussian then the joint pdf for these paths is given by where k = [(2i~)"lRl]"~, 2 is the row vector of the delays of the paths in the significant path set, and R the correlation matrix. Computing this joint pdf, however. is complex and time intensive. Instead we use a faster method which also allows for path pdfs which are not Gaussian. The path set and corresponding component delay models are given to a postprocess for a Monte Carlo simulation. The component delays are simulated as normal distributions which are evaluated using numbers generated by a multiplicative linear congruential generator. At each pass of the simulation, they are evaluated and a discrete delay value is stored for the corresponding delay arc. The edge paths are simulated by summing up their component delay arc delay values for a given simulation pass. The pulse paths are simulated by calculating the delay of the first half of the path, F, the side input delay, S, and the delay of the last half of the path, L. If the difference between S and F is greater than the maximum MPPW for 335

5 Figure 4: Pdf for a 4x4 multiplier L, U, then the pulse path delay is S + L. Otherwise, the delay of the pulse path is set to zero. Once the path set has been simulated, the maximum delay of all the simulated delays for the path set is found and stored as the simulated delay of the circuit. These results are binned and reported after a sufficient number of simulations. Note that the delay model can be much more complex and still work with this scheme. As long as it is possible to construct the delay graph and evaluate the delay model with a random number generator used for process variations, it is usable in this context. This technique includes delay models which have interdependence between delays. As long as the joint probability distribution of the component delays is known, the circuit timing response can be found in the manner we have described. 4 Results The proposed statistical timing analysis algorithm was implemented as an extension of an earlier tool, ETA [8], in a version called SETA consisting of approximately 12 lines of C++ code. SETA was run on several circuits, some of which are transistor level descriptions of the IS- CAS benchmark circuits. The data was gathered on a SUN SparcStation 1. Run times for path selection and sensitizing as well as for the final Monte Carlo simulation are reasonable. A Monte Carlo simulation of 2 runs was performed to determine the delay pdf and took no longer than 9 minutes for the largest circuit consisting of several thousand transistors. Precharacterization for the largest circuit took approximately two hours. The circuit delay pdfs for some circuits exhibit a nearnormal distribution (Figure 4). The majority of signals have almost the same delay or mean. This is partly because many of the paths are highly correlated. Since they all have nearly equal normal distributions, their maximum is approximately a normal distribution. Yet the circuits shown in Figure 5 have more interesting distributions. The unusual nature of these pdfs is due to the contributions of the longer pulse-path delays. The effect of these pulse-paths is dampened by the corresponding MPPW resulting in a complex delay response. In order to better understand these distributions and facilitate a comparison with previous research, additional ( (b) 11.2 Figure 5: (a) Pdf for a full adder (b) Pdf for ISCAS C1355 analyses of the full adder circuit have been performed. Figure 6 shows the pdfs obtained for the full adder by performing additional analyses under varying assumptions. The first plot shows two data sets. The first is the pdf of the full adder determined by the algorithm presented in this paper. The second data set in Figure 6(a) shows the same circuit analyzed without the benefits of MPPW sensitization. Here, the pdfs of the pulse paths completely overwhelm the effects of the edge paths. It is clear from the figure that ignoring MPPW can lead to very pessimistic results. In Figure 6(b) we have again plotted the circuit delay pdf of the full adder against plots which result from considering only one path. In this case, the two normal plots correspond to considering the longest edge path only and the longest pulse path only. Hence, it becomes clear that this approach, ignoring the other potentially statistically significant paths, can lead to optimistic results which must be avoided at all costs. 5 Conclusion Accurate design, optimization and testing of integrated circuits relies heavily on the results of timing analyzers. Recognizing that timing analysis is extremely sensitive to inaccuracies either due to delay modeling inadequacies or to variations in production process parameters, we have 336

6 With MPPW (4 - - AllPaths - ;kt Longest Edge - I. ; Longest Pulse :i I t I I * Figure 6: (a) Full adder pdfs computed with and without MPPW. (b) Full adder pdfs computed from all paths, single edge and single pulse paths presented a complete and novel approach to statistical timing analysis. Among the main contributions of this paper are the triple-node delay graph which incorporates the effects of input transition time on gate delays, the use of RSMs to determine the statistical gate delays, and an effective application of the concept of minimum propagatable pulse width to determine the delay contributions of potential pulses in the circuit. We have also shown that deterministic timing analysis sometimes leads to both overly pessimistic or optimistic results. This inaccuracy can be avoided by accurate statistical modeling of circuit level behavior in conjunction with correct higher level considerations such as path interdependence and sensitization, and proper application of phenomena such as the minimum propagatable pulse width. Acknowledgments: Thanks to Satyamurthy Pullela for the several discussions which lead to a better understanding of some concepts in probability. References [l] P. Cox, P. Yang, S. Mahant-Shetti, and P. Chatterjee, Statistical Modeling for Efficient Parametric Yield Estimation of MOS VLSI Circuits, IEEE Journal of Solid-State Circuits, Vol. SC-2, No. 1, pp , Feb [2] R. Hitchcock, Timing Verification and the Timing Analysis Program, Proc. of the 19th Design Automation Conference, pp , [3] J. Shelly and D. Tryon, Statistical Techniques of Timing Verification, Proc. of the 2th Design Automation Conference, pp , [4] J. Benkoski and A. Strojwas, A New Approach to Hierarchical and Statistical Timing Simulations, IEEE Trans. on CAD, vol. CAD-6, no. 6, pp , Nov [5] S. Devadas, H. Jyu, K. Keutzer, and S. Malik, Statistical Timing Analysis of Combinational Circuits, Proc. of the Int? Conference on Computer Design, pp , NOV [6] S. Devadas, K. Keutzer, S. Malik, and A. Wang, Certified Timing Verification and the Transition Delay of Combinational Logic Circuits, Proc. of the 29th Dcsign Automation Conference, pp , R. Bryant, Boolean Analysis of MOS Circuits, IEEE Trans. on CAD, vol. CAD-6, no. 4, pp , July R. Brashear, D. Holberg, M. Mercer and L. Pillage, ETA: Electrical-Level Timing Analysis, Proc. of the Int l Conference on Computer Aided Design, pp , NOV A. A. Alvarez, et al., Applications of Statistical Design and Response Surface Methods to Computer- Aided VLSI Device Design, IEEE Trans. on CAD, vol. 7, no. 2, pp , Feb N. R. Draper and H. Smith, Chapter 7, Applied Regression Analysis, John Wiley & Sons, P. O Brien and T. Savarino, Modeling the Drivingpoint Characteristic of Resistive Interconnect for Accurate Delay Estimation, Proc. of the Int l Conference on Computer Aided Design, pp , Nov L. Pillage and R. Rohrer, Asymptotic Waveform Evaluation for Timing Analysis, IEEE Trans. on CAD, vol. 9, no. 4, pp , Apr Y. Ju and R. Saleh, Incremental Techniques for the Identification of Statically Sensitizable Critical Paths, Proc. of the 28th Design Automation Conference, pp , H. Chen and D. Du, Path Sensitization in Critical Path Problem, Proc. of the Int l Conference on Computer Aided Design, pp , Nov W. Li, S. Reddy, and S. Sahui, On Path Selection in Combinational Logic Circuits, IEEE Trans. on CAD, vol. 8, no. 1, pp , Jan