DESIGN OF LOW POWER ETA FOR DIGITAL SIGNAL PROCESSING APPLICATION 1

Transcription

1 833 DESIGN OF LOW POWER ETA FOR DIGITAL SIGNAL PROCESSING APPLICATION 1 K.KRISHNA CHAITANYA 2 S.YOGALAKSHMI 1 M.Tech-VLSI Design, 2 Assistant Professor, Department of ECE, Sathyabama University,Chennai-119,India. ABSTRACT Error Tolerant Addition is the backbone of Digital Signal Processing. Digital Signal Processing (DSP) blocks form the backbone of various multimedia applications used in portable devices. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. The adders used in that applications must be numerically approximate rather than accurate. A methodology that can be used to harness maximum power savings using approximate adders, subject to a specific quality constraint is proposed. Normally ETA is a 8bit in which 4-bits (LSBs) are inaccurate and another 4-bits (MSBs) are accurate. In proposed system, instead of conventional full adder in MSBs replace it with 10-T full adder and in LSBs which consists of XOR gates replace it with approximate adder. So, power and area will be consumed automatically 25-30% of power consumption had obtained with the proposed modification. Index Terms: Approximate Adders, ETA, Full Adder, Mirror Adder, Least Significant Bit (LSB) I. Introduction During the design of an adder we have to make two choices in regard to different design abstraction levels. One is liable for the adder's architecture implemented with the one-bit full adder as a building block. The other defines the specific propose style at transistor level to implement the one-bit full adder. In many applications, such as a communication system, the analog signal coming from the outside world must first be sampled before being converted to digital data. The digital data are then processed and transmitted in a noisy channel before converting back to an analog signal. During this process, errors may occur anywhere. Error Tolerant Addition is the backbone of Digital Signal Processing. DIGITAL SIGNAL PROCESSING (DSP) blocks form the backbone of various multimedia applications used in portable devices. Error correction and error reduction is the employed in DSP techniques. The adders used in that applications must be numerically approximate rather than accurate. DSP block that uses approximate adders is proposed. A methodology that can be used to harness maximum power savings using approximate adders, subject to a specific quality constraint is proposed. The Error Tolerant truncation low power adder the ETA is the basic concept of this paper, Before going into the explanation, let us have a look at the definitions of some commonly used terminologies shown in this paper are given as follow. Error (E): E = Oca - Oela, where Oca is the result obtained by the adder, and Oela denotes the correct result (all the results are represented as decimal numbers). Accuracy (A): In the error-tolerant design, the accuracy of an adder is used to indicate how "correct" the output of an adder is for a particular input. It is defined as: A= (l-(e/0ca» x 100%Its value ranges from 0% to 100%. Minimum acceptance accuracy (MAA): Although some errors are allowed to exist at the output of an ETA, the accuracy of an acceptable output should be "high enough"(higher than a threshold value) to meet the requirement of the whole system. Minimum acceptable accuracy is just that threshold value. The result obtained whose accuracy is higher than the minimum acceptable accuracy is called acceptable result. Acceptance probability (AP): Acceptance probability is the probability that the accuracy of an adder is higher than the minimum acceptable accuracy. It can be expressed as AP = P (ACC > MAA),with its value ranging from 0 to1. Increasingly huge data sets and the need for instant response require the adder to be large and fast. The traditional ripple-carry adder(rca) is therefore no longer suitable for large adders because of its low speed performance. Many different types of fast adder, such as the carry-skip adder (CSK), carry select adder(cla) have been developed. Also, there are many low power adder design techniques that have been proposed. However, there are always trade-offs between speed and power. The error-tolerant design can be a potential solution to this problem. By sacrificing on accuracy, the ETA can attain great improvement in both the power consumption and speed performance. II. Addition Arithmetic Of ETA In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from the least significant bit (LSB) to the most significant bit (MSB).Also glitches in the carry propagation chain dissipate a significant proportion of dynamic power dissipation., if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved. Here, discuss about the addition arithmetic proposed where the input operand is split into two parts: with higher order bits grouped into accurate part and remaining lower order bits into inaccurate part. The length of each part

2 834 need not necessary be equal. The addition process starts from the demarcation line toward the two opposite directions simultaneously. In the example, the two 8-bit input operands, A=" " (183) and B= " " (189), are divided equally into 4 bits each for the accurate and inaccurate parts. The addition of the higher order bits ( accurate part) of the input operands is performed from right to left (LSB to MSB) starting from the demarcation line with normal addition method applied. This is to preserve its correctness since the higher order bits play a more important role than the lower order bits. The lower order bits of input operands (inaccurate part) are added using error tolerant addition mechanism. No carry signal will be generated or taken in at any bit position to eliminate the carry propagation path. To minimize the overall error due to the elimination of the carry chain, a special strategy is adapted and can be described as follows: Check every bit position from left to right (MSB - LSB) starting from right of demarcation line. If both input bits are "0" or different, normal one-bit addition is performed and the operation proceeds to next bit position. The checking process is stopped when both input bits are encountered as high i.e., 1, and from this bit on wards, all sum bits to the right (LSB) are set to "1." This is how this adder saves carry propagation delay and enhances the overall performance. III. Proposed Work The most straightforward structure consists of two parts: an accurate part and an inaccurate part. The accurate part is constructed using conventional adder, ere the RCA( 28T used usually) is replaced by a lot full-adder. The carry-in of this accurate part adder is connected to ground. The inaccurate part constitutes two blocks: a carry-free addition block and a control block as shown in the control block is used to generate the control signals to determine the working mode of the carry-free addition block. In addition, the Least Significant Bit(LSB) of the multiplier(bit B(O)) is used as control bit P for both accurate part and inaccurate part of the proposed adder.for B(O) is one, the adder cells performs normal addition operation. For B(O) equals to zero, the adder Cells are brought into OFF state with NMOS and PMOS transistor driven by P brought into open state and the line from supply to ground is cut off, thus minimizing leakage power dissipation. Based on the proposed methodology, an 8-bit Error tolerant adder is designed by considering 4 bits accurate part and 4 bits in inaccurate part. IV. Need For Error-Tolerant Adder Increasingly huge data sets and the need for instant response require the adder to be large and fast. The traditional ripple-carry adder (RCA) is therefore no longer suitable for large adders because of its low-speed performance.many different types of fast adders, such as the carry skip adder(csk), carry-select adder (CSL), and carry-look-ahead adder (CLA), have been developed. Also, there are many low-power adder design techniques that have been proposed. However, there are always trade-offs between speed and power. The error-tolerant design can be a potential solution to this problem. By sacrificing some accuracy, the ETA can attain great improvement in both the power consumption and speed performance. Error Tolerant Addition The commonly used terminologies in Error Tolerant addition are as follows: Overall error (OE): OE= Rc-Re, where Re is the result obtained by the Error tolerant addition technique, and Rc denotes the correct result (all the results are represented as decimal numbers). Accuracy (ACC): In the scenario of the error tolerant design, the accuracy of an addition process is utilized to indicate how correct the output of an adder is for a particular input. It is defined as ACC%=(1-(OE/Rc)) x 100. Its value ranges from 0-100%. Addition Arithmetic Fig1 Arithmetic Procedure For 8 Bit Error Tolerant Adder In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from the least significant bit (LSB) to the most significant bit (MSB). Also glitches in the carry

3 835 propagation chain dissipate a significant proportion of dynamic power dissipation. Therefore, if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved. This new addition arithmetic can be illustrated via an example shown above. Here, we discuss about the addition arithmetic proposed in where the input operand is split into two parts: with higher order bits grouped into accurate part and remaining lower order bits into in accurate part. The length of each part need not necessary be equal. The addition process starts from the demarcation line toward the two opposite directions simultaneously. The addition of the higher order bits (accurate part) of the input operands is performed from right to left (LSB to MSB) starting from the demarcation line with normal addition method applied. This is to preserve its correctness since the higher order bits play a more important role than the lower order bits. The lower order bits of input operands (inaccurate part) are added using error tolerant addition mechanism. No carry signal will be generated or taken in at any bit position to eliminate the carry propagation path. To minimize the overall error due to the elimination of the carry chain, a special strategy is adapted, and can be described as follows: Check every bit position from left to right (MSB - LSB) starting from right of demarcation line ;If both input bits are 0 or different, normal one-bit addition is performed and the operation proceeds to next bit position; The checking process is stopped when both input bits are encountered as high i.e., 1, and from this bit onwards,all sum bits to the right (LSB) are set to 1. The addition mechanism described can be easily understood from the example given in Fig. 3 with a final result of (367) which should actually yield (372) if normal arithmetic has been applied. The overall error generated can be computed as OE= =5. The accuracy of the adder with respect to these two input operands is ACC=(1- (5/372)) 100=98.66%. This accuracy level is acceptable for most of the image processing applications. Hence by eliminating carry propagation path in the inaccurate part and performing addition in two separate parts simultaneously, the overall delay time and power consumption is greatly reduced. The plot of accuracy and delay of proposed 8 bit adder with different number of bits in accurate and inaccurate parts, it is observed that the design with 4 bits in accurate part and 4 bits in inaccurate part yields an average accuracy of more than 98% for 100 samples taken. Fig2 16bit Error Tolerant Adder Design V Experimental Results Conventional Full adder Fig 3 Conventional full adder Fig4 Fig. 3 and Fig. 4 illustrates the circuit diagram and simulation results of the Conventional full adder.

4 836 Vol 05, Article 03276; March Approximate Adder ISSN: Fig5 Approximate Adder Fig6 Fig. 5 and Fig. 6 illustrates the circuit diagram and simulation results of the Approximate adder. Existing ETA Circuit Fig7 Existing ETA Circuit Fig8 Fig. 7 and Fig. 8 illustrates the circuit diagram and simulation results of the existing ETA circuit. Proposed ETA Circuit Fig9 Proposed ETA Circuit Fig10 Fig. 9 and Fig. 10 illustrates the circuit diagram and simulation results of the Proposed ETA circuit.

5 837 Existing Application Fig11 Existing Application Fig12 Fig. 11 and Fig. 12 illustrates the circuit diagram and simulation results of the existing Application. Proposed Application Fig13 Proposed Application Fig14 Fig. 13 and Fig. 14 illustrates the circuit diagram and simulation results of the Proposed Application. POWER CONSUMPTION Table 1 Power Comparison For Different Circuits TYPES OF ADDERS EXISTING (Watts) PROPOSED (Watts) CONVENTIONAL 2.053e e-006 ETA 1.165e e-004 APPLICATION 2.331e e-004 Comparing all the simulation results of proposed Error Tolerant Adder with those of the conventional adders, it is evident that the Error Tolerant Adder performed the best in terms of power consumption, delay, and Power- Delay Product as shown in table 1. CONCLUSION In conventional digital VLSI design, one usually assumes that a usable circuit/system should always provide definite and accurate results. But in fact, such perfect operations are seldom needed in our non digital worldly experiences. The world accepts analog computation, which generates good enough results rather than totally accurate results. The data processed by many digital systems may already contain errors. In many applications, such as a communication system, the analog signal coming from the outside world must first be sampled before being converted to digital data. The digital data are then processed and transmitted in a noisy channel before converting back to an analog signal.during this process, errors may occur anywhere. Furthermore, due to the

6 838 advances in transistor size scaling, factors such as noise and process variations which are previously insignificant are becoming important in today s digital IC design.based on the characteristic of digital VLSI design, some novel concepts and design techniques have been proposed. The concept of error tolerance and the PCMOS technology are two of them. According to the definition, a circuit is error tolerant if: It contains defects that cause internal and may cause external error. The system that incorporates this circuit produces acceptable results. The error tolerant adder was thus designed with an idea to minimize power consumption. The power consumption of the ETA was calculated using T-SPICE. Our approach aimed to simplify the complexity of a conventional MA cell by reducing the number of transistors. Extensive comparisons with conventional Adders showed that the proposed ETA outperformed the conventional Adders Applications Speed performance. The project explains the concept of Error Tolerant Adder (ETA).With small loss in accuracy; provide tremendous improvement in power, delay and area.the ETA was tested using the T-SPICE and was compared with the other conventional adders. Note that this approach differed from previous approaches where errors were introduced due to VOS. The concept of error tolerance is introduced in VLSI design. The potential applications of the ETA fall mainly in areas where there is no strict requirement on accuracy or where super low power consumption and high-speed performance are more important than accuracy. Our approach focused to simplify the complexity of a conventional MA cell by reducing the number of transistors. The error tolerant adder can be used in the DSP application for portable devices such as cell phones, laptops. As the previous works are considered it can be found that reduced power saving is important criteria for the electronic devices especially for portable multimedia devices are being used in a wide range. By taking this into consideration it is necessary to considered sign techniques from the adders which form the basic unit of the building blocks of these devices. FUTURE SCOPE In all the types of DSP applications, adders will play a crucial role in order to sustain power consumption. Applications can be made in digital field with the help of the proposed ETA. REFERENCES [1] Cho.H, Leem.L, and Mitra.S, ERSA: Error resilient system architecture for probabilistic applications, IEEE Trans. CAD of Integrated Circuits and Systems, 2012, vol. 31, no. 4, pp [2] Dally. W, Balfour. J, Black-Shaffer. D, Chen. J, Harting. R, Parikh. V, Park. J and Sheffield. D, Efficient embedded computing, Computer, 2008, vol. 41, no. 7, pp [3] Gupta. V, Mohapatra.D, Raghunathan.A and Roy.K, Low-Power Digital Signal Processing Using Approximate Adders, IEEE Trans. CAD of Integrated Circuits and Systems, 2013, 32(1), pp [4] Han.J and Orshansky.M, Approximate computing: an emerging paradigm for energy-efficient design, in ETS 13, May [5] Han.J, Chen.H, Liang.J, Zhu.P, Yang.Z and Lombardi.F, A stochastic computational approach for accurate and efficient reliability evaluation, IEEE Trans. Computers, 2013, in press. Advance access at IEEEXplore [6] Hegde.R and Shanbhag.N, Energy-efficient signal processing via algorithmic noise-tolerance, in Proc. IEEE/ACM Int. Symp. Low Power Electron. Design, Aug. 1999, pp [7] Hegde.R and Shanbhag.N.R., Soft digital signal processing, IEEE Trans. Very Large Scale Integr. Syst., Jun. 2001, vol. 9, no. 6, pp [8] Kulkarni.P, Gupta.P, and Ercegovac.M, Trading accuracy for power with an under designed multiplier architecture, in Proc. 24th IEEE Int. Conf. VLSI Design, Jan. 2011, pp