High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications

Transcription

1 J Electron Test (2017) 33: DOI /s High Speed Energy Efficient Static Segment Adder for Approximate Computing Applications R. Jothin 1 & C. Vasanthanayaki 2 Received: 10 September 2016 /Accepted: 19 December 2016 /Published online: 7 January 2017 # Springer ScienceBusiness Media New York 2017 Abstract Real time high quantity digital data computing design needs to achieve high performance with required accuracy range. The constraints involved with high performance are low power consumption, area efficiency and high speed. This paper proposes a design of high speed energy efficient Static Segment Adder (SSA), which improves the overall performance based on static segmentation. Accuracy Adjustment Logic (AAL) is incorporated to improve the accuracy derived from negating lower order bytes of input operands. In this paper, an integration of static segment method and accuracy adjustment logic is used to achieve computational accuracy for error tolerant applications. The proposed adder design enables to provide high speed and energy efficiency through the static segmentation method. Image enhancement operation is carried out using proposed SSA design. In this method, 99.4% overall computational accuracy for 16-bit addition even with 8-bit adder can be achieved. Keywords Static segment adder. Accuracy adjustment logic. Significance probability. Approximate computing. Computational accuracy Responsible Editor: S. Sindia * R. Jothin joejothin@gmail.com C. Vasanthanayaki vasanthi@gct.ac.in 1 Introduction In many Very Large-Scale Integrated (VLSI) systems such as application-specific Digital Signal Processing (DSP), the circuit is implemented for filtering, encryption or time to frequency or frequency to time domain transformations. Most critical functional units of these architectures, which performance is totally depended upon are adders. If adders are too slow or consume more energy, then the performance of the design will be degraded. Approximate addition has been carried out as a means of achieving area, power and speed improvements at the cost of accuracy in the field of digital video and audio signal processor design [1, 2, 5]. In this work, an accuracy improvement static segment approximate addition technique that is based on the significance probability by negating lower order bytes of input information to achieve the required computational accuracy for human perception interfaced applications is proposed. The proposed design is incorporated with spatial domain image enhancement technique, which operates directly on pixels and gives a quantitative measure for human perception. This paper is organised as follows: Section 2 details the related adder theory; Section 3 explains the proposed high speed energy efficient static segment adder (SSA) architecture and algorithm; Section 4 analyzes the simulation results of adders; Section 5 demonstrates the application of proposed SSA in approximate computing and Section 6 concludes this paper. 2 Related Adder Theory 1 2 Department of Electronics and Communication Engineering, KGiSL Institute of Technology, Coimbatore, India Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, India Accurate computation is required for certain applications to provide high accuracy results, but has area overhead, energy inefficiency and speed degradation. In conventional carrylookahead (CLA) and carry select adder (CSLA) designs,

2 126 J Electron Test (2017) 33: the logic depth and area are proportional to log 2 NandNlog 2 N respectively, where N is the bit-size of the adder [15]. A carryselect adder has 40% to 90% faster speed than ripple carry adder by performing additions in parallel and reducing the maximum carry path. Carry skip adder design uses skip propagation carry logic to speed up the addition operation by adding a propagation carry around a portion of entire adder [9]. The area complexity and power dissipation of these adders are high for large N. In different circumstances, the computation accuracy of an application may vary significantly so that an inaccurate computation may meet the required computational quality range. Normally, two types of approximation design methodologies are used to improve energy efficiency and speed [6, 8]. The first design method uses a voltage-over-scaling (VOS) for energy efficient CMOS circuits. The second one is based on redesigning logic architecture into an approximate design. Approximate hardware is used to get a result faster than a conventional unit, and has applications to design for a high performance which might be error tolerant to some threshold for approximate result instead of using more time, energy and area to obtain the accurate result [7, 11]. However, approximate arithmetic can be used in other applications where low latency is important, and small errors can be tolerated in high volume digital data computing devices [3, 4, 12]. Speculative adders are used to reduce the critical path delay but the hardware overhead is high [13]. Variable latency speculative adder (VLSA) improves speed with an error detection and recovery scheme [10]. In a segmentation based error tolerant adder (ETA), the input operands are divided into accurate and inaccurate parts as shown in Fig. 1. The normal addition method is used for the higher order bits (accurate part) of the input operands from right to left (LSB to MSB). Ripple carry adder (RCA) is chosen for accurate part of the circuit since it is simplest, saves most power and requires less hardware circuitry (ETA-I). CLA and RCA logic is used in the accurate part for improving the area and speed (ETA-II). Since there is no carry signal generated, the propagation path will not exist. Hence the inaccurate part is divided into two blocks namely, carry free addition block and control block. The function of carry free addition block is to check every bit position from the MSB to LSB. If both input values are B1^, the checking process will be stopped to set the control signal high at this position. All sum bits to the right of this position are set to B1^. If both the input values are B0^ or different, normal XOR is performed and operation proceeds to the next bit position [14]. The limitation of the design is complexity to generate control signals from the Control Signal Generating Cell (CSGCs) and each cell generates a control signal for the modified XOR gate at the corresponding bit position in carry free addition block in the inaccurate part. Energy efficient low power error tolerant adder (ELAETA-I or ELAETA-II) has error sensitive circuit in the most significant bit position of the inaccurate part, which computes the carry and appropriate addition of carry to the least significant bit position of the accurate part increases the accuracy by 20% when normal OR operation is performed instead of XOR operation in the inaccurate part for area efficiency over the existing ETA-I or ETA-II, respectively [10]. Stability is one of the major design criteria for obtaining the system performance which totally depends upon the worst case accuracy that should be in high range. A limitation of the error tolerant adder family is the difficulty to maintain the worst case accuracy above 70% as it fails to produce 100% accuracy for low contrast images when the input operand values lie only in the inaccurate part range. The proposed SSA design increases the accuracy with Accuracy Adjustment Logic (AAL) circuit for higher order segment selection and maintains 100% accuracy by static segment method when the Fig. 1 General architecture of existing ETA family

3 J Electron Test (2017) 33: Fig. 2 Segmenting in SSM_8 where m = lower order segment is selected. This is to preserve its correctness in the higher order for high contrast images. The following constraints are used to compute the system performance: 1. Overall error (OE) is the difference between conventional adder output (Rc) and approximation adder output (RE). Percentage of error Tolerance = [OE/Rc]*100% (the results are represented in decimal numbers). 2. Accuracy (ACC) of an adder indicates the correctness of the adder output for a particular input. ACC = (1-(OE/ Rc))*100%. 3. Minimum Acceptable Accuracy (MAA) is defined as some errors lower than a threshold value are allowed to exist at the output of adder to meet the requirement of whole system. 4. Acceptance Probability (AP): Acceptance probability is the probability that the accuracy of an adder is higher than the minimum acceptable accuracy. 5. Minimum Accuracy of an adder is higher than the minimum acceptable accuracy. 3 Proposed High Speed Energy Efficient Static Segment Adder Static Segment Method (SSM) of addition is applied on input operands in the proposed SSA design. The algorithm for addition of two n-bit operands using the method of segmentation is given below: 3.1 Algorithm of SSM & Select m-bit (say 8-bit) segment from augend and addend n-bit input (say 16-bit) operands & This Segment must contains the leading one bit & Select the higher order leading one m-bit position (say 8- bit) segment from augend or addend n-bit operands & Select the same m-bit position (say 8-bit) segment from augend or addend n-bit operands & Add these two m-bit segments with accuracy adjustment estimator logic carry & Expand the m-bit addition to n-bit addition 3.2 Static segmentation of SSA In the proposed method four possible combinations of two m- bit segments from two n-bit input operands for addition are used in the m-bit SSM. Fig. 2 explores the SSM_8 in which the segment size (m) is 8 bits. The SSM chooses m-bit segments from n-bit input operands and gives them to the input of m-bit adder with two m-input OR gates and m-bit 2-to-1 multiplexers; if the first m bits starting from the MSB are all zeros, the lower m-bit segment must contain the leading one or zero. Same segment order for each operand is taken from one Fig. 3 Possible selection processes in SSM_8 01xx xxxx xxxx xxxx upper byte 0001 xxxx xxxx xxxx upper byte = C Sum Sum SS xx xxxx xxxx xxxx upper byte xx01 xxxx upper byte = C Sum Sum SS xxx xxxx upper byte 01xx xxxx upper byte = C Sum Sum SS xx xxxx lower byte xx01 xxxx lower byte = C Sum Sum 100% accuracy

4 128 J Electron Test (2017) 33: Fig. 4 Architecture of proposed Static Segment Adder (SSA) of two possible segments in an n-bit input operand as shown in Fig Architecture of proposed static segment adder Fig. 4 shows architecture of proposed SSA. In this architecture (n = 2 m) the bit-wise OR value of A[n 1:n-m] and B[n 1:n-m] is computed to select the two possible same m-bit segments (i.e., (A[n 1:n m] and B[n 1:n m]) or (A[n-m 1:n-2 m] and B[nm 1:n-2 m])). Accuracy adjustment logic is enabled for higher order segment selection of input operands to increase the accuracy by selecting the P1 in the output. When the lower order segment is selected SSA works as a conventional adder to maintain the accuracy as 100%, the propagation carry from the AALiszeroandP2isselectedintheoutput. The segment strategy is chosen to design proposed SSA with minimum acceptable accuracy of 99%. Having considered the above, the 16 bit operands are segmented into 8 bits. If the segment size of proposed SSA has less than 8 bits (i.e., accurate part of existing ETA family), the minimum acceptable accuracy, acceptance probability and area will be decreased. For example, if the segment size (m) is 7, 6, or 5 bits, the area will be 33, 30 or 25 LUTs respectively for 16-bit SSA. Whereas in case of lower order values of input operands, the accuracy will be lower than 100% and for higher order values of input operands, the accuracy will be slightly lower than existing ETA. So the segment size is chosen from the accurate Fig. 5 Worst case accuracy of ETA adder lower byte segment lower byte segment = SSA 100% accuracy ACCURATE INACCURATE = ETA family 50 % accuracy

5 J Electron Test (2017) 33: Table 1 Accuracy Comparision of Adders S. No Input data 1 Input data 2 Sum % of accuracy in existing 16 bit ETA-I Conventional Existing 16 bit CSLA 16 bit ETA-I Sum Proposed 16 bit SSA % of accuracy in proposed 16 bit SSA ,589 11, ,000 10,000 20,000 19, ,654 24,675 37,329 37, , ,684 42, ,000 51,400 51, ,034 32,323 59,357 59, , ,555 61, bit size of existing ETA family to maintain the accuracy for high input operands. If the segment size has more than 8 bits, the minimum acceptable accuracy and the acceptance probability will increase slightly and area will be inefficient. Case 1: If the higher order segment has 0 value and selected lower order segment of input operands which randomly varies from 0 to 255, the proposed SSA works as a conventional adder (100% accuracy) and ETA family produces a variable accuracy. Fig. 5 shows the worst case accuracy of ETA adder family. Case 2: If the higher order segment of input operands is selected and lower order segment has 0 value, SSA and ETA family work as a conventional adder (100% accuracy). Case 3: If the higher order segment of input operands is selected and lower order segment randomly chosen from 0 to 255, SSA and ETA produce a variable accuracy Accuracy Calculation Two 16-bit input operands are: Augend (A) = = Addend (B) = = Addition (conventional sum) = The addition technique used in SSM_8 method is given in steps as follows: Step 1: Segmentation A = B = (8 bit) (8 bit) Table 2 Area, Delay and Power Comparision Word size Adder Area (LUTs) Delay (ns) Power (mw) 16 bit Conventional CSLA Conventional RCA Existing ETA-I Proposed SSA (m = 8-bit)

6 130 J Electron Test (2017) 33: Accuracy in % Step 2: 8-bit Addition Now we have; Aseg ¼ ¼ Bseg ¼ ¼ 1 10 Let Z = Aseg Bseg = (Accuracy adjustment logic) Thus, Z ({C,Sum}) = (9 bit) Step 3: Expanding the addition with AAL output and padding ones Thus, SSA Out = (17 bit) = (34815) 10 OE ¼ ¼ 1 Conventional Adder output OE Tolerance ð% Þ ¼ð1=34814Þ*100% ¼ 0:01% Accuracy ð% Þ ¼ ð1 ð1=34814þþ*100% ¼ 99:99% EXISTING 16-BIT ETA-I PROPOSED 16-BIT SSA Fig. 6 Accuracy graph of existing ETA-I and proposed SSA 4 Simulation Results Xilinx14.2softwareisusedtodesignandanalyzethe performance of existing and proposed adders. The simulation of the adders is carried out and results are tabulated in Tables 1 and 2. From the results it is clear that the accuracy of the proposed SSA adder for all input operands is greatly improved by using AAL and static segment method. The worst case accuracy range can be rising from 50% to 94% as shown in Fig. 6. SSA achieves 13.84%, 50.06%, and 13.13% computational speed improvement when compared to existing conventional CSLA, conventional RCA and existing ETA-I respectively and consumes more area (8 LUTs) than existing ETA-I. Whereas, the proposed SSA consumes slightly less dynamic energy using multiplexer switching when compared to other existing adders. In the proposed SSA design, the full range of input operands from0to could be playing a more important role to represent the low, medium and high contrast digital signal. Therefore all ranges of input operands are considered while calculating the accuracy in SSA. The SSA design can be a potential solution to get the overall high computational accuracy for all error tolerant applications like image blending, defect detection processes of machine vision applications, contrast stretching in image processing, audio and video processing, etc. One of the applications is implemented and presented in the following section. 5 Application of Proposed SSA in Approximate Computing Application Image enhancement operation is performed based on contrast stretching principle, which gives a linear mapping of input to output value by stretching the range of Fig. 7 Architecture of image enhacement using proposed 16- bit SSA

7 J Electron Test (2017) 33: performed in MATLAB simulink using proposed SSA and existing adders by varying the multiplication factor to get the high accuracy images for low contrast and high contrast images. From Fig. 8 (b), it is noted that increase in K value increases the intensity range of the image. 6 Conclusion Fig. 8 Contrast enhancement (a) Low contrast input image F (b)output images G for K = 1.5, 2, 3 and 4 intensity value for computational quality. Pixels of the image are mapped as per the equation below: Gðx; yþ ¼ fðf ðx; yþ CÞg K þ A ð1þ The first step is to determine the lower and upper range (A and B) of output image (G(x,y)) for which the image pixel value has to be extended. Next, lower and upper pixel values (C and D) of the original input image (F(x,y)) are examined. Here K = (B-A)/(D-C) is the multiplication factor which increases the intensity value of input image pixels in the output. The value of each pixel in the output image is a linear combination of the corresponding pixel values in the input image. For better enhancement of the output image, C and D values are selected to fifth and ninety fifth percentile of the input pixel values, respectively. Architecture of image enhancement is shown in Fig. 7. F(x,y) is the input image ( ) given to proposed SSA of the image enhancement module. Every pixel of the input image is processed according to eq. 1. K is the variable multiplication factor which determines the measure of intensity range for output resolution. Image enhancement application is performed using proposed SSA by using the integration of MATLAB simulink and Xilinx softwares, the input and outputs of this application are shown in Fig. 8. Very High Speed Integrated Circuits hardware description language (VHDL) code is used to construct user defined Xilinx blackbox adders and integrated with predefined modules. Contrast stretching operation is Proposed adder design is found to be capable of producing high accuracy response for low contrast and high contrast images. In the proposed adder, accuracy and speed are increased by accuracy adjustment logic and static segment method. For all possible input combinations, performance analysis is carried out and the worst case error is computed. The proposed method of SSA consumes less energy and notably has high speed with average computational error of ~0.6%, when compared to an existing ETA. Thus the proposed approximate adder can lead to better quality in all types of error tolerant applications when compared to other forms of error tolerant approximate adders. References 1. Breuer MA (2004) Intelligible Test Techniques to Support Error- Tolerance. Proc. Asian Test Symposium pp Breuer MA, Haiyang Z (2006) Error-tolerance and Multi- Media. Proc. of the International Conference on Intelligent Information Hiding and Multimedia, Signal Processing pp Du K, Varman P, Mohanram K (2012) High Performance Reliable Variable Latency Carry Select Addition. Proc IEEE/ACM Design, Automation Test in Europe (DATE) pp Gupta V, Mohapatra D, Park SP, Raghunathan A, Roy K (2011) IMPACT: Imprecise Adders for Low-Power Approximate Computing. Proc. IEEE/ACM International Symposium on Low- PowerElectronicsandDesign(ISLPED)pp Lee KJ, Hsieh TY, Breuer MA (2005) A Novel Testing Methodology Based on Error-Rate to Support Error tolerance. Proc. of International Test Conference pp Liu Y, Zhang T, Parhi K (2010) Computation error analysis in digital signal processing systems with Overscaled supply voltage. IEEE Trans VLSI Syst 18(4): Lu SL (2004) Speeding up processing with approximation circuits. IEEE Computer 37(3): Mohapatra D, Chippa V, Raghunathan A, Roy K (2011) Design of Voltage-Scalable Meta-Functions for Approximate Computing. Proc Design, Automation and Test in Europe Symp pp Rawat K, Darwish T, Bayoumi M (2002) A low power and reduced area carry select adder. Proc 45th Midwest Symp Circuit 1: Sakthivel R, Kittur HM (2014) Energy efficient low area error tolerant adder with higher accuracy. Circuits, Systems, and Signal Processing 33(8): Shin D, Gupta SK (2008) A Re-Design Technique for Datapath Modules in Error Tolerant Applications, Proc Asian Test Symp pp

8 132 J Electron Test (2017) 33: Venkatesan R, Agarwal A, Roy K, Raghunathan A (2011) MACACO: Modeling and Analysis of Circuits for Approximate Computing. Proc IEEE/ACM International Conference on Computer-Aided Design (ICCAD) pp Ye R, Wang T, Yuan F, Kumar R, Xu Q (2013) On Reconfiguration- Oriented Approximate Adder Design and its Application. Proc International Conf Computer-Aided Design pp Zhu N, Goh W, Zhang W, Yeo K, Kong Z (2010) Design of Low- Power High-Speed Truncation-Error-Tolerant Adder and its application in digital signal processing. IEEE Trans on VLSI Systems 18(8): Ziegler M and Stan M (2001) Optimal Logarithmic Adder Structures with a Fanout of Two for Minimizing the Area-Delay Product. Proc International Symp Circuits and Systems pp R. Jothin received Diploma in Electronics and Communication Engineering from the Sankar Institute of Polytechnic, Tirunelveli, India and received the B.E. and M.E. (VLSI Design) in Electronics and Communication Engineering from Government College of Technology, Coimbatore, India. He is currently working for a Ph.D. in Anna University, Chennai, India. He has 20 years of industry experience and 3 years of academic experience. His research focuses on high performance VLSI architectures for image processing applications. C. Vasanthanayaki received the B.E. degree in Electronics and Communication Engineering and M.E. degree in Computer Science, from Government College of Engineering, Tirunelveli, India, in 1987 and 1997 respectively. She received the Ph.D. degree in the Information and Communication Engineering. Since 1988, she has been with the Government College of Technology, Coimbatore, India.