APPLICATIO S TYPICAL APPLICATIO. LTC3252 Dual, Low Noise, Inductorless Step-Down DC/DC Converter DESCRIPTIO FEATURES

Transcription

1 FEATRES.V to.v Input Voltage Range No Inductors Typical Efficiency 0% Higher than LDOs Spread Spectrum Operation Low Input and Output Noise Shutdown Disconnects Load from V IN Dual Adjustable Independent Outputs (Range: 0.9V to.v) Output Current: 0mA Each Output Low Operating Current: I IN = 0µA Typ (µa with One Output Enabled) Low Shutdown Current: I IN = 0.0µA Typ Soft-Start Limits Inrush Current at Turn On Short Circuit and Over Temperature Protected Available in mm mm -Pin DFN Package APPLICATIO S Handheld Electronic Devices Cellular Phones Low Voltage Logic Supplies DSP Power Supplies.V to.v Conversion LTC Dual, Low Noise, Inductorless Step-Down DC/DC Converter DESCRIPTIO The LTC is a switched capacitor step-down DC/DC converter that produces two adjustable regulated outputs from a single.v to.v input. The part uses switched capacitor fractional conversion to achieve a typical efficiency increase of 0% over that of a linear regulator. No inductors are required. A unique constant frequency, spread spectrum architecture provides a very low noise regulated output as well as low noise at the input. The part also has Burst Mode operation to provide high efficiency at low output currents, as well as ultralow current shutdown. Low operating currents (0µA with both outputs enabled, µa with one output enabled) and low external parts count make the LTC ideally suited for space-constrained battery-powered applications. The part is shortcircuit and overtemperature protected and is available in a tiny mm mm -pin DFN package., LTC and LT are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. TYPICAL APPLICATIO.V and.v Output Voltages with Shutdown.V/.V Efficiency vs Input Voltage -CELL Li-ION OR -CELL NiMH OFF ON OFF ON EN EN VIN OT FB C + µf LTC C C + OT µf 8 C GND FB 9 0k k k k V OT =.V I OT 0mA V OT =.V I OT 0mA TA0 EFFICIENCY (%) LTC-.V I OT (.V) = 0mA I OT (.V) = 0mA LTC-.V LDO-.V LDO-.V TA0a

2 ABSOLTE AXI RATI GS (Notes, ) W W W V IN to GND... 0.V to.0v EN, EN, FB, FB to GND... 0.V to (V IN + 0.V) I OT, I OT (Note )... 00mA Operating Ambient Temperature Range (Note )... 0 C to 8 C Storage Temperature Range... C to C Lead Temperature (Soldering, sec) C W PACKAGE/ORDER I FOR ATIO FB EN V IN C + OT C TOP VIEW FB EN C + 9 OT 8 C GND DE PACKAGE -LEAD (mm mm) PLASTIC DFN EXPOSED PAD IS GROND (MST BE SOLDERED TO PCB) T JMAX = C, θ JA = 0 C/W, θ JC =. C/W ORDER PART NMBER LTCEDE DE PART MARKING Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = C. V IN =.V, V OT = V OT =.V, C = C = µf, Cin = C OT = C OT = (all capacitors ceramic) unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX NITS V IN Min Operating Voltage (Note ). V Max Operating Voltage. V I VIN Operating Current, I OT = 0mA, V EN = V IN, V EN = V IN, 0 0 µa Both Outputs Enabled.V V IN.V Operating Current, I OT = 0mA, V EN = 0, V EN = V IN or V EN = V IN, 0 µa One Output Enabled V EN = 0,.V V IN.V Shutdown Current V M0 = 0V, V M = 0V,.V V IN.V 0.0 µa V FB, V FB Feedback Voltage I OT = 0mA,.V V IN.V V I OT Output Current V EN = V IN 0 ma I OT Output Current V EN = V IN 0 ma I FB FB, FB Input Current V FB = V FB = 0.8V 0 0 na V RIPPLE Output Ripple (OT or OT) I OT = 0mA mv P-P Spread Spectrum Frequency Range f MIN Switching Frequency MHz f MAX Switching Frequency..0 MHz V IH EN, EN Input High Voltage.V V IN.V. 0.8 V V IL EN, EN Input Low Voltage.V V IN.V V I IH EN, EN Input High Current EN = V IN, EN = V IN µa I IL EN, EN Input Low Current EN = 0V, EN = 0V µa t ON Turn On Time R OT = Ω 0.8 ms OT, OT Load Regulation (Referred to FB pin) 0.08 mv/ma Line Regulation 0 I OT 0mA or 0 I OT 0mA 0. %/V R OL Open Loop Output Impedance, V IN =.0V, I OT = 00mA, V FB = 0.V (Note ). Ω (OT or OT)

3 ELECTRICAL CHARACTERISTICS Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note : The LTCEDE is guaranteed to meet specified performance from 0 C to 0 C. Specifications over the 0 C and 8 C operating temperature range are assured by design characterization and correlation with statistical process control. Note : Based on long-term current density limitations. Note : Minimum operating voltage required for regulation is: V IN > (V OT(MIN) + R OL I OT ) Note : Output not in regulation; R OL = (V IN / V OT )/I OT. Note : This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. TYPICAL PERFOR A CE CHARACTERISTICS W No Load Supply Current vs Supply Voltage (One Output Enabled) No Load Supply Current vs Supply Voltage (Both Outputs Enabled) FB Voltage vs Load Current I IN (µa) C C C I CC (µa) C 0 C C VFB (V) V IN =.V 0 C C 8 C I OT (ma) G0 G0 G0 EN/EN Input Threshold Voltage vs Supply Voltage.V Output Voltage vs Supply Voltage.V Output Efficiency vs Output Current V SHDN (V) C 8 C C VOT (V) T A = C I OT = 0mA I OT = 0mA I OT = 0mA EFFICIENCY (%) T A = C V IN =.V V IN =.V V IN =.V V IN = V V IN = V I OT (ma) G0 G0 G0

4 TYPICAL PERFOR A CE CHARACTERISTICS W Oscillator Max/Min Frequency vs Supply Voltage.V Output Voltage vs Supply Voltage.V Efficiency vs Load Current FREQENCY (MHz) C MAX C MIN C MAX 8 C MAX C MIN 8 C MIN..... VOT (V) T A = C I OT = 0mA I OT = 0mA I OT = 0mA..... EFFICIENCY (%) 0 T A = C V IN =.8V V IN =.V 0 V IN =.V V IN =.V I OT (ma) G0 G08 G09 Output Current Transient Response Line Transient Response 0mA I OT 0mA.V V IN.V V OT 0mV/DIV AC V OT mv/div AC V IN =.V V OT =.V G V OT =.V I OT = ma G PI F CTIO S FB (Pin ): Feedback Input Pin. An output divider should be connected from OT to FB to program the output voltage. EN (Pin ): Input Enable Pin. When EN is high, OT is enabled. When EN is low OT is shut down. V IN (Pin ): Input Supply Voltage. Operating V IN may be between.v and.v. Bypass V IN with a (µf min) low ESR ceramic capacitor to GND (C IN ). C + (Pin ): Flying Capacitor Positive Terminal (C). OT (Pin ): Regulated Output Voltage. OT is disconnected from V IN when in shutdown. Bypass OT with a low ESR ceramic capacitor to GND (C O ). See Output Capacitor Selection section for size requirements. C (Pin ): Flying Capacitor Negative Terminal (C). GND (Pin ): Ground. Connect to a ground plane for best performance.

5 PI F CTIO S C (Pin 8): Flying Capacitor Negative Terminal (C). OT (Pin 9): Regulated Output Voltage. OT is disconnected from V IN when in shutdown. Bypass OT with a low ESR ceramic capacitor to GND (C O ). See Output Capacitor Selection section for size requirements. C + (Pin ): Flying Capacitor Positive Terminal (C). EN (Pin ): Input Enable Pin. When EN is high, OT is enabled. When EN is low OT is shut down. FB (Pin ): Feedback Input Pin. An output divider should be connected from OT to FB to program the output voltage. SI PLIFIED W BLOCK DIGRAM W EN EN OVERTEMPERATRE SWITCH CONTROL SPREAD SPECTRM OSCILLATOR CHARGE PMP V IN C + OT C BRST DETECT CIRCIT + CHARGE PMP FB C + 9 OT 8 C FB + GND SBD

6 OPERATIO (Refer to Simplified Block Diagram) The LTC has two switched capacitor charge pumps to step down V IN to two regulated output voltages. The two charge pumps operate 80 out of phase to reduce input ripple. Regulation is achieved by sensing each output voltage through an external resistor divider and modulating the charge pump output current based on the error signal. A -phase nonoverlapping clock activates the two charge pumps running them out of phase from each other. On the first phase of the clock current is transferred from V IN, through the external flying capacitor, to OT via the switches of charge pump. Not only is current being delivered to OT on the first phase, but the flying capacitor is also being charged up. On the second phase of the clock, flying capacitor is connected from OT to ground, transferring the charge stored during the first phase of the clock to OT via the switches of charge pump. Charge pump operates in the same manner to supply current to OT, but with the phases of the clock reversed relative to charge pump. sing this method of switching, only half of the output current for each output is delivered from V IN, thus achieving a 0% increase in efficiency over a conventional LDO. A spread spectrum oscillator, which utilizes random switching frequencies between MHz and.mhz, sets the rate of charging and discharging of the flying capacitors. This architecture achieves extremely low output noise. Input noise is significantly reduced compared to conventional charge pumps. The outputs also have a low current burst mode to improve efficiency even at light loads. In shutdown mode all circuitry is turned off and the LTC draws only leakage current from the V IN supply. Furthermore, OT and OT are disconnected from V IN. The EN and EN pins are CMOS inputs with threshold voltages of approximately 0.8V to allow regulator control with low voltage logic levels. The LTC is in shutdown when a logic low is applied to both enable pins. Since the mode pins are high impedance CMOS inputs, they should never be allowed to float. Always drive the enable pins with valid logic levels. Short-Circuit/Thermal Protection The LTC has built-in short-circuit current limiting as well as over temperature protection. During short-circuit conditions, internal circuitry automatically limits each output to approximately 00mA of current. If fault conditions (such as shorted outputs) cause excessive self heating on chip such that the junction temperature exceeds approximately 0 C, the thermal shutdown circuitry will disable the charge pumps. The IC resumes operation once the junction temperature drops back to approximately C. The LTC will cycle in and out of thermal shutdown without latchup or damage until the overstress condition is removed. Long term overstress (I OT or I OT > 00mA, and/or T J > C) should be avoided as it can degrade the performance or shorten the life of the part. Soft-Start To prevent excessive current flow at V IN during start-up, the LTC has built-in soft-start circuitry on each output. When an output is enabled, the soft-start circuitry increases the amount of current available from the output linearly over a period of approximately 00µs. The softstart circuitry is disabled shortly after the output achieves regulation. Spread Spectrum Operation Switching regulators can be particularly troublesome where electromagnetic interference (EMI) is concerned. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases, the frequency of operation is either fixed or is a constant based on the output load. This method of conversion creates large components of noise at the frequency of operation (fundamental) and multiples of the operating frequency (harmonics).

7 OPERATIO (Refer to Simplified Block Diagram) nlike conventional buck converters, the LTC s internal oscillator is designed to produce a clock pulse whose period is random on a cycle-by-cycle basis but fixed between MHz and.mhz. This has the benefit of spreading the switching noise over a range of frequencies, thus significantly reducing the peak noise. Figures and show how the spread spectrum feature of the LTC significantly reduces the peak harmonic noise and virtually elliminates harmonics compared to a conventional buck converter. Spread spectrum operation is always enabled but is most effective when the LTC s outputs are out of Burst Mode operation and the oscillator is running continuously (see the Low Current Burst Mode Operation section). Low Current Burst Mode Operation To improve efficiency at low output currents, a Burst Mode operation function is included in the LTC. An output current sense is used to detect when the required output current of both outputs drop below an internally set threshold (0mA typ). When this occurs, the part shuts down the internal oscillator and goes into a low current operating state. The LTC will remain in the low current operating state until either output has dropped enough to require another burst of current. The LTC resumes continuous operation when the load on one or both outputs exceeds the internally set threshold. nlike traditional charge pumps where the burst current is highly dependant on many factors (i.e., supply, switch strength, capacitor selection, etc.), the LTC s burst current is set by the burst threshold and hysteresis. This means that the output ripple voltage in Burst Mode operation is relatively consistent and is typically about mv with a output capacitor on a.v output. The ripple voltage amplitude is a direct function of the output capacitor size. Burst Mode operation ripple voltage does increase slightly at lower output voltages due to the increase in loop gain. sers can counteract output voltage ripple increase through the use of a slightly larger output capacitor. See Recommended Output Capacitance guidelines of Figure. Figure. Conventional Buck Input Noise Figure. LTC Input Noise

8 OPERATIO (Refer to Simplified Block Diagram) 8 C OT (µf) RECOMMENDED CAPACITANCE MINIMM CAPACITANCE V OT (V) F0 Figure. Output Capacitance vs Output Voltage Output Capacitor Selection The style and value of capacitors used with the LTC determine several important parameters such as regulator control loop stability, output ripple and charge pump strength. The switching nature of the LTC minimizes output noise significantly but not completely. What small ripple that exists at an output is controlled by the value of output capacitor directly. Increasing the size of the output capacitor will proportionately reduce the output ripple. The ESR (equivalent series resistance) of the output capacitor plays the dominant role in output noise. When the LTC switches between clock phases there is a period where all switches are turned off. This blanking period shows up as a spike at the output and is a direct function of the output current times the ESR value. To reduce output noise and ripple, it is suggested that a low ESR (<0.08Ω) ceramic capacitor be used for the output capacitor. Tantalum and aluminum capacitors are not recommended because of their high ESR. Both the style and value of the output capacitors can significantly affect the stability of the LTC. As shown in the Simplified Block Diagram, the LTC uses a control loop to adjust the strength of each charge pump to match the current required at the output. The error signal of each loop is stored directly on each output capacitor. Thus the output capacitors also serve to form the dominant pole in each control loop. Figure is a graph of the recommended output capacitance, and minimum capacitance required for good transient response (see the Ceramic Capacitor Selection Guidelines section). Likewise excessive ESR on the output capacitor will tend to degrade the loop stability of the LTC. The closed loop output impedance of the LTC is approximately: R O VOT = 008. Ω 08. V For example, with the output programmed to.v, the R O is 0.Ω, which produces a 8mV output change for a 0mA load current step. For stability and good load transient response it is important for the output capacitor to have 0.Ω or less of ESR. Ceramic capacitors typically have exceptional ESR and combined with a tight board layout should yield excellent stability and load transient performance. Further output noise reduction can be achieved by filtering the LTC outputs through a very small series inductor as shown in Figure. A nh inductor will reject the fast output transients caused by the blanking period, thereby presenting a nearly constant output voltage. For economy the nh inductor can be fabricated on the PC board with about cm (0.") of PC board trace. LTC OT GND nh V OT 0.µF F0 Figure. nh Inductor sed for Additional Output Noise Reduction V IN Capacitor Selection The low noise, dual phase architecture used by the LTC makes input noise filtering much less demanding than conventional charge pump regulators. The LTC input current will transition between I OT / and I OT / for each half cycle of the oscillator. The blanking period described in the V OT section also effects the input. For this reason it is recommended that a low ESR (µf min) or greater ceramic capacitor be used for C IN (see the Ceramic Capacitor Selection Guidelines section). Aluminum and tantalum capacitors can be used but are not recommended because of their high ESR.

9 OPERATIO (Refer to Simplified Block Diagram) Further input noise reduction can be achieved by filtering the input through a very small series inductor as shown in Figure. A nh inductor will reject the fast input transients caused by the blanking period, thereby presenting a nearly constant load to the input supply. For economy the nh inductor can be fabricated on the PC board with about cm (0.") of PC board trace. V IN SPPLY nh Figure. nh Inductor sed for Additional Input Noise Reduction Flying Capacitor Selection LTC F0 Warning: A polarized capacitor such as tantalum or aluminum should never be used for the flying capacitors since their voltages can reverse upon start-up of the LTC. Ceramic capacitors should always be used for the flying capacitors. V IN GND The flying capacitors control the strength of the charge pump. In order to achieve the rated output current it is necessary for the flying capacitor to have at least 0.µF of capacitance over operating temperature with a V bias (see the Ceramic Capacitor Selection Guidelines). If 0mA or less of current is required from an output then its associated flying capacitor minimum can be reduced to 0.µF. Ceramic Capacitor Selection Guidelines Capacitors of different materials lose their capacitance with higher temperature and voltage at different rates. For example, a ceramic capacitor made of XR material will retain most of its capacitance from 0 C to 8 C whereas a Z or YV style capacitor will lose considerable capacitance over that range (0% to 80% loss typical). Z and YV capacitors may also have a very strong voltage coefficient causing them to lose an additional 0% or more of their capacitance when the rated voltage is applied. Therefore, when comparing different capacitors it is often more appropriate to compare the amount of achievable capacitance for a given case size rather than discussing the specified capacitance value. For example, over rated voltage and temperature conditions, a, V, YV ceramic capacitor in a 080 case may not provide any more capacitance than a µf, V, XR available in the same 080 case. In fact, over bias and temperature range, the µf, V, XR will provide more capacitance than the, V, YV. The capacitor manufacturer s data sheet should be consulted to determine what value of capacitor is needed to ensure minimum capacitance values are met over operating temperature and bias voltage. Below is a list of ceramic capacitor manufacturers and how to contact them: AVX Kemet Murata Taiyo Yuden Vishay Layout Considerations Due to the high switching frequency and transient currents produced by the LTC careful board layout is necessary for optimal performance. A true ground plane and short connections to all capacitors will improve performance and ensure proper regulation under all conditions. Figure shows the suggested layout configuration. Note the exposed paddle of the package is ground (GND) and must be soldered to the PCB ground. The flying capacitor pins C +, C, C + and C will have very high edge rate wave forms. The large dv/dt on these pins can couple energy capacitively to adjacent printed circuit board runs. Magnetic fields can also be generated if the flying capacitors are not close to the LTC (i.e., the loop area is large). To decouple capacitive energy transfer, a Faraday shield may be used. This is a grounded PC trace between the sensitive node and the LTC pins. For a high quality AC ground, it should be returned to a solid ground plane that extends all the way to the LTC. Keep the FB traces away from or shielded from the flying capacitor traces or degraded performance could result. 9

10 OPERATIO (Refer to Simplified Block Diagram) Thermal Management To reduce the maximum junction temperature, a good thermal connection to the PC board is recommended. Soldering the exposed paddle of the IC to the PCB and maintaining a solid ground plane under the device on one or more layers of the PC board, the thermal resistance of the package can be as small as 0 C/W. By applying the suggested thermal management techniques the IC junction temperature should never exceed C even under worst case operating conditions. Power Efficiency The power efficiency (η) of the LTC is approximately 0% higher than a conventional linear regulator. This occurs because the input current for a -to- step-down charge pump is approximately half the output current. For an ideal -to- step-down charge pump the power efficiency is given by: POT VOT IOT V η = = PIN V VIN IOT EN V IN C IN C R A R B R B ' R A ' LTC OT IN The switching losses and quiescent current of the LTC are designed to minimize efficiency loss over the entire output current range, causing only a couple % error from the theoretical efficiency. For example with V IN =.V, C EN I OT = ma and OT regulating at.v the measured efficiency is 80.% which is in close agreement with the theoretical 8.% calculation. Programming the LTC Output Voltages (FB and FB Pin) Each output of the LTC is programmed to an arbitrary voltage via an external resistive divider. Figure shows the required voltage divider connection. The voltage divider ratio is given by the expression: R R A B OT = 08. V Typical values for total voltage divider resistance can range from several kωs up to MΩ. The user may want to consider load regulation when setting the desired output voltage. The closed loop output impedance of the LTC is approximately: R O = OT 008. Ω 08. V For a.v output, R O is 0.Ω, which produces a 8mV output change for a 0mA load current step. Thus, the user may want to target an unloaded output voltage slightly higher than desired to compensate for the output load conditions. The output may be programmed for regulation voltages of 0.9V to.v. Since the LTC employs a -to- charge pump architecture, it is not possible to achieve output voltages greater than half the available input voltage. The minimum V IN supply required for regulation can be determined by the following equation: V IN (MIN) (V OT (MIN) + I OT R OL ) OT C O C O OT OT R A OT = R B 0.8V C O R A OT OT LTC FB FB R A ' C O OT R A ' OT = R B ' 0.8V R B R B ' GND (CONNECT DIRECTLY TO GROND PLANE) F0 GND GND F0 Figure. Suggested Layout for the LTC Figure. Programming the LTC

11 TYPICAL APPLICATIO Li-Ion to.v/.v Outputs OT.V 0mA k OFF ON µf V IN EN EN OT OT C + LTC C + C C FB FB GND OFF ON 9 8 µf 0k k OT.V 0mA Li-ION k TA0 PACKAGE DESCRIPTIO DE/E Package -Lead Plastic DFN (mm mm) (Reference LTC DWG # ) 0.8 ±0.0.0 ±0.0. ±0.0.0 ±0.0 ( SIDES) PACKAGE OTLINE 0. ± ±0.0 ( SIDES) 0.0 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS.00 ±0. ( SIDES) R = 0.0 TYP R = 0. TYP 0.8 ± 0. PIN TOP MARK.00 ±0. ( SIDES).0 ± 0. ( SIDES) PIN NOTCH 0.00 REF 0. ± ± ±0. ( SIDES) BOTTOM VIEW EXPOSED PAD NOTE:. DRAWING PROPOSED TO BE A VARIATION OF VERSION (WGED) IN JEDEC PACKAGE OTLINE M0-9. ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 0.0 BSC (E/DE) DFN 080

12 TYPICAL APPLICATIO S Fixed.V IN to.v OT at 00mA -Cell NiMH with Digitally Selectable.V/.V Output.V OFF ON µf V IN EN EN OT OT C + LTC C + C C FB FB GND 9 8 µf 0k k OT.V 00mA µf TA0 -CELL NiMH EN µf k V IN EN EN OT OT C + LTC C + C C FB FB GND EN 9 8 µf 0k k I OT 0mA EN EN OT OFF OFF 0V OFF ON.V ON OFF.V ON ON.V TA0 RELATED PARTS PART NMBER DESCRIPTION COMMENTS LTC 0mA, 0kHz, Step-p/Down Charge Pump V IN =.V to V, V OT = V or V, Regulated Output, I Q = 0µA, with Low Battery Comparator I SHDN = µa, S8 LTC 0mA, 0kHz, Step-p/Down Charge Pump V IN =.V to V, V OT =.V or V, Regulated Output, I Q = 0µA, with Power-On Reset I SHDN = <µa, S8 LT 00mA (I OT ), 00kHz, High Efficiency 90% Efficiency, V IN =.V to 0V, V OT Min =.V, Step-Down DC/DC Converter I Q =.ma, I SHDN = 0µA, N8, S8 LTC9-. 0mA,.MHz, High Efficiency % Efficiency, V IN =.V to.v, V OT =.V, Regulated Output, Step-Down Charge Pump I Q = 80µA, I SHDN = µa, MS8 LTC9-.8 0mA,.MHz, High Efficiency % Efficiency, V IN =.V to.v, V OT =.8V, Regulated Output, Step-Down Charge Pump I Q = 80µA, I SHDN = µa, MS8 LTC0-. 0mA,.MHz, High Efficiency 8% Efficiency, V IN =.V to.v, V OT =.V, Regulated Output, Step-Down Charge Pump I Q = µa, I SHDN = <µa, ThinSOT LTC 00mA, Spread Spectrum, High Efficiency p to 8% Efficiency, V IN =.V to.v, V OT = 0.9V to.v, Step-Down Charge Pump I Q = 8µA, I SHDN = <µa, MS LTC0 00mA (I OT ),.MHz, Synchronous 9% Efficiency, V IN =.V to V, V OT Min = 0.8V, Step-Down DC/DC Converter I Q = µa, I SHDN = <µa, MS8 LTC0/LTC0A 00mA (I OT ),.MHz, Synchronous 9% Efficiency, V IN =.V to V, V OT Min = 0.8V, Step-Down DC/DC Converter I Q = 0µA, I SHDN = <µa, ThinSOT LTC0/LTC0B 00mA (I OT ),.MHz, Synchronous 9% Efficiency, V IN =.V to.v, V OT Min = 0.V, Step-Down DC/DC Converter I Q = 0µA, I SHDN = <µa, ThinSOT LTC.A (I OT ), MHz, Synchronous Step-Down 9% Efficiency, V IN =.V to.v, V OT Min = 0.8V, DC/DC Converter I Q = 0µA, I SHDN = <µa, MS LTC.A (I OT ), MHz, Synchronous Step-Down 9% Efficiency, V IN =.V to.v, V OT Min = 0.8V, DC/DC Converter I Q = 0µA, I SHDN = <µa, TSSOP-E LTC0 00mA (I OT ), MHz, Synchronous 9% Efficiency, V IN =.V to.v, V OT Min =.V, Buck-Boost DC/DC Converter I Q = <µa, I SHDN = µa, MS LT/TP 00 K PRINTED IN SA Linear Technology Corporation 0 McCarthy Blvd., Milpitas, CA 90- (08) -900 FAX: (08) LINEAR TECHNOLOGY CORPORATION 00