Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation

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1 666 PAPER Special Section on Low-Power, High-Speed LSIs and Related Technologies Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation Masaaki IIJIMA, Masayuki KITAMURA, Student Members, Masahiro NUMA a),akiratada, Members, Takashi IPPOSHI, and Shigeto MAEGAWA, Nonmembers SUMMARY In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (V DD ) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than V DD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption. key words: low power design, PD-SOI, body-bias, pass-transistor logic, circuit simulation, SRAM 1. Introduction In order to pursue ultra low power operation, lowering the supply voltage (V DD ) has been one of the most effective approaches since the dynamic power consumption drops in proportion to the square of V DD. Lowering the V DD,however, causes serious performance degradation. In addition, simply scaling the threshold voltage (V th ) down to improve the operational speed as the lowered V DD results in a drastic increase in the leakage power. Then, we focus on the ABC (Active Body-biasing Control) technique for PD-SOI, where the threshold voltage of each transistor can be dynamically controlled by providing a body-bias through the body contact. In fact, PD-SOI has been requiring the T-type or H-type gate configuration for V th control so far, which causes an increase of parasitic gate capacitance and area penalty. On the other hand, the HTI (Hybrid Trench Isolation) technology [1], [2] has brought a breakthrough in V th control employing the direct body contact as shown in Fig. 1, where the area penalty and parasitic gate capacitance are drastically reduced to almost the same level as bulk MOSFETs. We address a novel low power technique with ABC- SOI to solve the issue of speed degradation even in such low voltage as 0.5 V-V DD operation. The rest of this paper is organized as follows. Section 2 discusses the Pass-Transistor Logic and its probrem in low voltage operation. Then, we propose an ABC-Bootstrap PTL and apply it to logic circuits in Sect. 3. Section 4 also presents an SOI-SRAM with boosted voltage scheme. Section 5 provides the circuit simulation results. Finally, we summarizes the key results in Sect Pass-Transistor Logic with Lower V DD The Pass-Transistor Logic (PTL), such as LEAP (LEAn integration with Pass-transistors) [3], is suitable for low power design since PTL circuits are generally synthesized with fewer transistors than CMOS logic. In addition, the lower parasitic junction capacitance between the silicon substrate and source/drain in the SOI process contributes to higher operational speed for PTL circuits, where plural nmosfets are connected in series. The single-rail type pass-transistor logic using nmos has a disadvantage of voltage loss at highlevel output. Even though the output voltage V o is expected to be V o = V DD, it actually rises only up to V o = (V DD V th ), which causes an increase in the short circuit current and degradation of driving power. The use of Bootstrap PTL [4] at low supply voltage has been discussed to overcome the issue of speed degradation and output voltage loss. The Booststrap configuration is reportedly superior to CMOS-TG circuits from the point of both the speed and power consumption even in sub-1 V operation [4]. The feature of Bootstrap PTL is that the drain voltage of nmos pass-transistor rises up to V DD without the pull-up pmos by boosting the gate voltage up higher than V DD. In a Bootstrap PTL configuration, it consists of two nmoss T1 and T2 as shown in Fig. 2(a). Here, T1 propagates data as a pass-transistor, and T2, called the isolation transistor, activates the capacitive coupling in T1 between the gate and source/drain, so that the gate voltage of T1 rises up higher than V DD. The capacitances C GS and C GD between the gate and source/drain of T1 help to boost the gate voltage during a pull-up transition as shown in Fig. 3. The con- Manuscript received August 10, Manuscript revised November 10, The authors are with the Graduate School of Science and Technology, Kobe University, Kobe-shi, Japan. The authors are with Renesas Technology Corp., Itami-shi, Japan. a) numa@kobe-u.ac.jp DOI: /ietele/e90 c Fig. 1 Schematic diagram of ABC-SOI MOSFET. Copyright c 2007 The Institute of Electronics, Information and Communication Engineers

2 IIJIMA et al.: BOOSTED VOLTAGE SCHEME WITH ABC-SOI 667 ventional Bootstrap PTL, however, still has difficulty in an operation due to a lack of driving power especially in the case pass-transistors are connected long in series. 3. ABC-Bootstrap PTL and Its Application We propose an ABC-Bootstrap PTL shown in Fig. 2(b) to improve the conventional Bootstrap PTL from the point of the speed and driving power [5]. Here, the body voltages of these nmoss can be controlled through the direct body contact, as already shown in Fig. 1, which originally connects the body and ground in the same way as the well contact in bulk process. Since the body contacts are connected to the gate or source instead of the ground, we can avoid any area penalty. The features of the ABC-Bootstrap PTL employing two kinds of body-biases are the following two points: i) Reduce the voltage loss at the isolation transistor. ii) Make use of the body capacitance C body between the source/drain and body to boost the gate voltage higher. First, the body-bias indicated by (i) in Fig. 2(b) allows the gate voltage (V gate ) rise up to the higher level as shown in Fig. 3 owing to a lowerd threshold voltage of the isolation transistor. Second, the body-bias at the pass-transistor represented by (ii) in Fig. 2(b) enhances a boosting effect of the gate voltage as shown in Fig. 3 due to the body capacitance C body which consists of the capacitances between the source/drain and body (C S-body, C D-body). In the conventional approach, only the overlap capacitances between the gate and source/drain (C GS, C GD ) were the main factor for boosting the gate voltage up. On the other hand, the body capacitance C body also affects a boost of the gate voltage in the ABC-Bootstrap PTL. In addition, the higher V gate in our approach than the conventional one strongly accelerate the pull-up transition since the V th of the pass-transistor is much lowered by the higher V gate. 3.1 Boosting Effect of the Gate Voltage Here, we discuss the boosting effect of the gate voltage (V gate ) based on a capacitance model shown in Fig. 4. In the conventional approach, the capacitive coupling boosts the V gate up to where V gate = ( 1 + C GS + C GD C ptr + C iso + C wire ) V DD V th(iso), (1) C ptr = C GS + C GD + C GB, (2) C iso = C GD(iso) + C D-body(iso). (3) Here, V th(iso) denotes the threshold voltage of the isolation transistor. Thus, the strength of capacitive coupling depends upon the ratio of (C GS + C GD ) to the total capacitance. In the ABC-Bootstrap PTL, the V gate rises up to where V gate = 1 + C GS + C GD + C body C ptr + C iso + C wire V DD V th(iso), (4) C body = C S-body + C D-body, (5) C ptr = C GS + C GD + C body. (6) The additional capacitances (C S-body, C D-body) enable the V gate to rise higher than the conventional approach. Here, we discuss the value of capacitance and estimate the boosting effect through the SPICE simulation with a BSIM-SOI transitor model. We have calculated the capacitance between the channels and the overlap capacitance under the condition that the precharge operation is completed. The results shows that C ptr = 2.5 ff, C body = 1.0 ff, C iso = 0.35 ff, and C wire = 0.67 ff in the ABC-Bootstrap PTL when the gate width of the pass-transistor W ptr = 2.0 µm andthat of the isolation transistor W iso = 0.5 µm. Hence, the capacitive coupling can boost the gate voltage up to 0.69 V if we assume that V DD = 0.5 V and V th = 0.2 V. (a) Bootstrap structure (conventional). (b) ABC-Bootstrap (proposed). Fig. 2 Bootstrap PTL. Fig. 3 The gate voltage in ABC-Bootstrap PTL. (a) Bootstrap PTL (conv.). (b) ABC-Bootstrap PTL (prop.). Fig. 4 Capacitance model.

3 Application of ABC-Bootstrap PTL The ABC-Bootstrap PTL has been implemented on two kinds of circuits. One is a two-input XOR as shown in Fig. 5. The XOR gate consists of two bootstrap-type pass-transistor units. A classical nmos-type PTL logic and ABC-nMOS PTL have also been applied to an XOR gate. Here, the body voltages of nmoss and pmoss in the conventional approaches are tied to the ground and V DD, respectively. The other application is a MCC (Manchester Carry Chain) adder [6] which is widely known for its fast propagation of carry signal. The MCC adder with the ABC-Bootstrap PTL shown in Fig. 6 is expected to be an appropriate application for our approach since the pass-transitor has enough time to complete the precharge operation before the souce signal begins to rise. The generation signal g i, kill signal k i, and propagation signal p i are first determined by the input signals a i and b i with each bit i as g i = a i b i, k i = ā i b i, and p i = a i b i. Then, a carry signal C i+1 from bit i is calculated as C i+1 = k i (g i + C i p i ). Here, the p i is obtained as soon as input signals come in even though the C i is derived from the carry signal propagating serially over all bits. Therefore, the difference in arrival time between the gate and source signals in the pass-transistor surely enables to finish the precharge operation and accelerates the carry (a) nmos PTL. (b) ABC-nMOS PTL. propagation by the boosted V gate. 4. SOI-SRAM with Boosted Voltage Scheme The difficulty of SRAMs operating at low supply voltage comes from the degradation of the access speed due to a lack of driving current. This is based on the fact that the transistor delay increases exponentially as the lowered supply voltage. The other obstacles to low voltage operation include instability of SRAM cells such as an increase in softerror rate (SER) and reduction in static-noise-margin (SNM) [7]. Although the conventional approach boosting the supply voltage in memory cells improves the deteriorated SNM [8], it cannot avoid the issue of exponential increase in the read/write access time in low voltage operation. The use of 8T-SRAM [9] with a separated read-port as shown in Fig. 7 has been discussed to enhance the stability by eliminating cell disturbs during a read access even when V DD is scaled down to sub-1 V. However, additional transistors M1 and M2 unfortunately deteriorate the write access time for 8T- SRAM as lowered supply voltage. Hence, it is important to accelerate the read/write access time even in low voltage operation while maintaining the SNM. Then, boosting the word line voltages of access transistors for larger on-current is a key idea to accelerate the read/write speed, which suppresses the speed degradation in low voltage operation. In SRAM memory cells, bit lines and a cross-coupled inverter latch are connected each other through access transistors while the word line activates the access transistors. Then, the read/write operation can be performed by draining on-current at the access transistors. Thus, enhancing the current from bit lines to memory cells helps shorten the delay time in the write mode. In addition, an increase in the discharge current from the precharged bit line is also effective for fast read operation. Therefore, boosting the word line voltage is expected to shorten both the write and read access time. In this section, we describe a boosted voltage scheme employing a capacitive coupling by an ABC-SOI capacitor. 4.1 ABC-SOI Capacitor (c) Bootstrap PTL. (d) ABC-Bootstrap PTL (proposed). Fig. 5 Configuration of XOR gate. The Active Body-biasing Controlled (ABC)-SOI capacitor utilizing the PD-SOI process with the Hybrid Trench Isolation technology [1], [2] provides a strong capacitive coupling. Fig. 6 PTL. 4-bit Manchester carry chain type adder with the ABC-Bootstrap Fig. 7 8T-SRAM memory cell.

4 IIJIMA et al.: BOOSTED VOLTAGE SCHEME WITH ABC-SOI 669 The strength of capacitive coupling is dependent upon a transistor size and gate voltage. For an nmos FET with thegatelengthl = 0.18 µm, we have calculated the capacitance between the gate and source/drain when the gate voltage changes from 0.3 V to 0.6 V. According to the SPICE simulation results shown in Fig. 8, the capacitance is proportional to the gate voltage since the capacitances in the channel of transistor increases in accordance with the gate voltage while the overlap capacitance becomes a constant value. In addition, even though the capacitance in body-tied SOI mainly derives from the overlap capacitances between the gate and source/drain (C GS, C GD ), the ABC-SOI capacitor, where the body is directly connected to the gate, provides the enhanced capacitance owing to the additional capacitances (C S-body, C D-body) between the source/drain and body. We take the advantage of strong capacitive coupling by the ABC-SOI. 4.2 WL Driver with ABC-SOI Capacitor The proposed approach, boosted voltage scheme with the ABC-SOI capacitor, is shown in Fig. 9. We describe the features in detail. First, during a low to high transition of the word line, the pmos in the transmission gate helps finish the pull-up transition perfectly since the pmos keeps on-state until the input signal WL via delay circuits cuts off the pmos. Thus, the word line voltage V WL is allowed to rise up to V DD immediately. Second, the capacitance C BS of the boost transistor starts to boost V WL higher than V DD as soon as the pmos turns off in the driver circuit with the single boost transistor shown in Fig. 9(a). In addition, the driver with double stages of the boost transistor, shown in Fig. 9(b), divides the capacitance C BS into two boost transistors. The second stage of the boost transistor driven by the second delay circuit prevents V WL from dropping when V WL is boosted by the first stage of the boost transistor. In Fig. 9(a), V WL actually drops a little due to the current passing through the pmos before turning off perfectly. Hence, employing double stages of the boost transistor enhances the capacitive coupling and ensures boosting V WL higher than V DD. The higher gate voltage results in an enhanced on-current of the access transistors. 4.3 Boosting Effect of Word Line Voltage Here, we discuss the boosting effect of the word line voltage. In fact, the capacitive coupling by the boost transistors dominates the maximum voltage level of the word line, which boosts the word line voltage V WL up to V WL = ( 1 + C BS C total ) V DD, (7) where C BS denotes the capacitance between the gate and source/drain of the boost transistors, and C total denotes the total capacitance including the wire capacitance of the word line C WL. Thus, the strength of capacitive coupling depends upon the ratio of C BS to C total. Here, C BS is proportional to the gate width W BS of the boost transistor, and C WL is proportional to the length of the word line, thus, the number of memory cells in each row. Then, Fig. 10 shows the ratio of the word line voltage V WL to V DD (V WL /V DD ) calculated by Eq. (1) when the number of memory cells arrayed in each row varies. For simplicity, we treat C total as C total = C BS + C WL. The capacitance of the boost transistors for capacitive coupling has been set to C BS = 14 ff, 28 ff when the gate width W BS = 10 µm, 20 µm, respectively. We have assumed that the wire capacitance of the word line per memory cell is C WL = 1.25 ff/cell, where we assume that the capacitance Fig. 8 Capacitance of boost transistor. Fig. 10 Boosting effect of the word line voltage. (a) Driver with single boost transistor. (b) Driver with double stages of boost transistor. Fig. 9 Boosted word line voltage scheme with ABC-SOI capacitor.

5 670 in the read port is twice as large as that in the write port. In Fig. 10, in the case memory cells of 32-bit are arrayed in each row, for example, the ratio V WL /V DD = 1.4 when the gate width W BS = 20 µm, while the maximum voltage level of the word line decreases as the number of bit increases. Hence, an adequate ratio of V WL /V DD ensures low voltage operation and shortens the access time. 5. Simulationl Results 5.1 Simulation Setup We have performed SPICE simulation with BSIM-SOI transistor model for 0.18 µm PD-SOI process in order to compare our approach with the conventional body-tied SOI. The threshold voltages with nmos and pmos are set to V th-n = 0.24 V, V th-p = 0.34 V, respectively. We define these threshold voltages V th-n, V th-p as the gate voltage which makes the drain current I ds per width W to be 1 µa/µm when the drain voltage V ds is set to 1.8 V. We have calculated them based on the I d -V g characteristics as shown in Fig. 11. First, we have evaluated the ABC-Bootstrap PTL with respect to the critical path delay, active power, and leakage power at 0.5 V and room temperature for an XOR gate and MCC adder. The delay time represents the period from the point of V DD /2 in input signals to that of V DD /2 in output signals under the condition that buffer gates are inserted to before all inputs and after output terminals. Second, we have also calculated the access time of a 6T-SRAM memory cell in the write and read operation modes for the supply voltage from 0.35 V to 0.6 V in order to evaluate an impact of the boosted voltage scheme on the access time. The threshold voltages of memory cells are set to V th-n = 0.34 V, V th-p = 0.42 V. The boosted voltage scheme has been compared to the SRAM configuration with the normal word line driver. Regarding the application of our technique, we extracted the resistance and capacitance of the wire after designing the cell layout. We have decided that the channel widths of the pass-transistors in an XOR gate and MCC adder are 2.0 µm and 1.0 µm, respectively, and that of the isolation transistor is 0.5µm. The transis- tor sizes of memory cell are set to W = 0.5 µm. We have also determined the gate width of W = 5 µm for the word line drivers and transmission gate and that of W = 10 µmfor the boost transistors. With respect to the whole layout area of 8 Kb memory array, for example, our boosted voltage scheme has an area overhead of 10% due to the additional area of word line drivers. Here, the use of ABC-SOI capacitor in word line drivers reduces 1% of the area of memory array with the body-tied SOI capacitor. On the other hand, if we consider a boosted voltage scheme employing a charge pump circuit, the ratio of area overhead decreases for memories with larger capacity. For instance, the area overhead of the charge pump circuit with decoupling capacitors can be reduced to 5% at most in the case of memories with a capacity of 16 Mb. However, the charge pump circuit requires an additional design methodology for placing appropriate decoupling capacitors in order to stabilize the boosted voltage. In addition, even if we insert the decoupling capacitance which is 10 times as large as the boosted capacitance, a bounce of 10% in the power rail still remains. In contrast to the charge pump circuit, our approach does not need any decoupling capacitors even for memories with larger capacity as long as the number of memory cells in each row is constant, since we boost only the selected single word line. 5.2 Results for XOR Gate Table 1 shows the comparison with the results for an XOR gate between the conventional Bootstrap PTL and the ABC- Bootstrap PTL. We have confirmed the result that the ABC- Bootstrap PTL shortens the delay time by 52% compared with the conventional approach. Even though the number of pass-transistor stages in a 2-input XOR gate is only one, the body-biasing control seems enough to accelerate the speed of data propagation and to shorten the delay time. With respect to the power consumption, both the dynamic and standby leakage power dissipated at almost the same power in spite of extra power dissipation for charging body voltage in the ABC-Bootstrap. This is because a quick transition of the drain voltage of the pass-transistor effectively affects a reduction in the short-circuit power. Then, we consider the correlation between delay and standby leakage power. Although lowering the V th generally attains higher operational speed, it also causes an increase in the standby leakage power at the same time. In Fig. 12, we characterize the trade-off relation between the delay and standby leakage power when the V th changes from 240 mv to 310 mv in 10 mv step. According to the SPICE simulation result, all circuit configurations dissipated at almost the same standby Fig. 11 I d -V g characteristics of BSIM-SOI model. Table 1 Evaluation for XOR gate. item Bootstrap ABC-Bootstrap (conv.) (prop.) Delay [ns] (0.48) Active Power [nw] (0.99) Standby Power [nw] (0.96) ( ): prop./conv.

6 IIJIMA et al.: BOOSTED VOLTAGE SCHEME WITH ABC-SOI 671 leakage power as long as the V th is constant. In terms of the delay time, it increases exponetially as the V th rises. For example, the delay time in the conventional Bootstrap PTL becomes 3.3x compared to the nmos PTL when V th = 310 mv even though the Bootstrap PTL operates faster when V th = 240 mv. On the other hand, the ABC-Bootstrap PTL shows only a half delay time of the ABC-nMOS PTL even when V th = 310 mv. 5.3 Results for 4-Bit MCC Adder We discuss an operation of the pass-transistor in the MCC adder in terms of the waveforms shown in Fig. 13. Figure 13(a) illustrates the waveform of the gate and drain signals at the first stage of pass-transistor, and Fig. 13(b) shows those at the fourth stage of pass-transistor. Both the gate voltages in the conventional Bootstrap PTL and the ABC-Bootstrap PTL rise up higher than V DD as shown in Fig. 13(a). Here, the drain voltage of proposed technique, represented by a carry signal C 1, is going up to V DD quickly. According to Fig. 13(b), in the case of the fourth stage of pass-transistor, the drain voltage in the conventional approach shows the longer transition time and is not able to reach to V DD. The transition time of the drain signal during a low to high transition becomes longer as the signal propagates serially over the pass-transistors, which degrades the boosting effect of the gate voltage especially at the final stage of pass-transistor. On the other hand, the drain voltage even at the fourth stage of pass-transistor, denoted by a carry signal C 4, reaches to the vicinity of V DD in a shorter transition time in the ABC-Bootstrap PTL owing to a strong boosting effect by the capacitive coupling and lowering the V th. 5.4 Power Saving Effect Here, we discuss the power saving effect owing to shortening the delay time by the ABC-Bootstrap PTL. We compare the power consumption of both the conventional Bootstrap PTL and ABC-Bootstrap PTL after adjusting the proper supply voltages in order to achieve the same operational speed. First, we assume the delay time in the ABC-Bootstrap PTL at 0.5 V-V DD as the standard. Then the supply voltage can be scaled up until the conventional Bootstrap PTL operates at the same speed as the ABC-Bootstrap PTL. As shown in Table 2, the proper supply voltage for the conventional Bootstrap PTL to obtain the same speed are V DD = 0.56 V, V DD = 0.63 V for the XOR gate and 4-bit MCC Adder, respectively. The higher supply voltage is required in the case of 4-bit MCC Adder. At these proper supply voltages, we have evaluated the power consumption of XOR gate and 4- bit MCC Adder. According to Table 2, both the active and standby leakage power have been decreased effectively. The ABC-Bootstrap PTL reduces the active power by 21% for XOR gate, and 40% for 4-bit MCC Adder. Moreover, the standby leakage power has also been saved by 19%, 36%, respectively. Figure 14 also shows the active and leakage power consumption of the MCC adder in different temperature Fig. 12 Variation of delay and standby power for several V th. Table 2 Power saving effect by the ABC-Bootstrap PTL. Delay Active Standby circuit V DD [ns] Power [nw] Power [nw] XOR conv V prop V (0.79) 0.82 (0.81) MCC conv V Adder prop V (0.60) 8.14 (0.64) (): prop./conv. (a) At the 1st pass-transistor. (b) At the 4th pass-transistor. Fig. 13 Comparison based on waveform for MCC adder.

7 672 conditions. ABC-CMOS circuit includes the CMOS-TG type carry propagation block employing the active bodybias through the gate to body connection. The supply voltage is set to 0.5 V for ABC-CMOS and our approach. In the conventional approach, the supply voltage is set to 0.63 V, where we assume that all approches operate at the same speed. The area of ABC-Bootstrap PTL is reduced by 26% compared to ABC-CMOS in terms of total gate widths. Although the leakage power increases exponentially due to the subthreshold leakage current in accordance with the temperature, our ABC-Bootstrap PTL results in the lowest power consumption owing to the following reasons. The leakage power consumption at high temperature mainly depends on the sub-threshold leakage current due to the lowered threshold voltage rather than the PN junction current caused by the forward body-bias. The actual body voltage at forward bias in the proposed scheme is limited to 0.42 V even when the supply voltage is 0.5 V, which is derived from the voltage loss at the high-level output of the isolation transistor. In addition, the leakage power consumption of the forward body-bias applied for pass-transistors occupies only 3% of the total leakage power consumption. 5.5 Access Times of SRAM in Write/Read Mode First, we discuss the write operation speed to memory cells based on the results shown in Fig. 15. We also consider the waveforms of the clock CK, word line WL, and dataretention node in Fig. 16(a). Here, we define the write time as the period from the point of V DD /2inCKduringalow to high transition to that in the date retention node of memory cells during the data inverting operation. We reduces the write time by 10% and 38% at V DD = 0.5 V and V DD = 0.35 V, respectively. The data retention node of memory cell in our approach completes charging quickly owing to the boosted word line voltage as shown in Fig. 16(a). Here, the ratio of the word line voltage V WL to V DD in Fig. 16 becomes V WL /V DD = 1.25 that approximates the value calculated by Eq. (1) as shown in Fig. 10. Next, we show the simulation results with the read time. We also consider the waveforms of the clock CK, word line WL, bit line BL, and output data signal from sense amplifier BL out as illustrated in Fig. 16(b). Here, we define the read time as the period from the point of V DD /2in CK during a low to high transition to that in BL out, while the sense amplifier detects the difference of bit line voltages between BL and BLB and outputs the data stored in memory cells. According to Fig. 15, the lower supply voltage increases the read time exponentially. Our proposed approach shortens the read time by 15% at V DD = 0.5 V and 30% at V DD = 0.35 V compared to the conventional ap- Fig. 14 Power consumption vs. temperature. Fig. 15 SRAM access time. (a) Write mode. (b) Read mode. Fig. 16 Waveforms.

8 IIJIMA et al.: BOOSTED VOLTAGE SCHEME WITH ABC-SOI 673 proach. Since the read time is dependent on the discharging speed of the bit line, enhancing the on-current of the access transistors by the boosted word line voltage higher than V DD achieves quick discharging operation of the bit line as shown in Fig. 16(b). As a result, the bit line voltage in the proposed approach drops in shorter transition time than the conventional one. Therefore, the output data in the proposed approach appears first by the quick response of the sense amplifier. 5.6 V th Dependence of Access Time Here, we analyze the dependence of access time derived from a variation in the threshold voltage (V th ). In the low voltage operation such as 0.5 V-V DD, transistors come into the linear or sub-threshold operation since the supply voltage almost reaches the threshold voltage. Especially for SRAM memory cells, their performance is directly dependent upon the on current of access transistors which varies due to V th variation. Then, we have evaluated the difference in access time derived from V th variation between the conventional approach and proposed one through SPICE simulation. We have decided that the mean of the threshold voltage V th0 = 346 mv and assume a variation of ±10% as the best and worst cases. Figure 17 shows the access time of memory cell when V th0 changes from 0.9V th0 to 1.1V th0. With respect to the difference in access time between the fastest and slowest cases, the maximum difference results in 2.54x in the read mode for the conventional approach. On the other hand, the difference is suppressed down to 1.99x in our approach since the enhanced on current of access transistors by the boosted gate voltage avoids a larger impact of V th variation. The difference in write time is likewise reduced from 1.53x to 1.21x. Therefore, a smaller variation in the access time due to V th variation is expected in our approach. 6. Conclusion In this paper, we have proposed an ABC (Active Bodybiasing Controlled)-Bootstrap PTL (Pass-Transistor Logic) with PD-SOI in order to achieve high-speed operation even at low supply voltage. Our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI utilizes the body capacitance C body between the source/drain and body. We have applied our proposed technique to an XOR gate and 4-bit MCC (Manchester Carry Chain) adder and designed an SOI-SRAM, where the boosted word line voltage enhances the on-current of the access transistors and shortens the access time. The proposed scheme seems to be appropriate for such memory cell as 8T-SRAM which improves the deteriorated SNM in low voltage operation. According to the SPICE simulation results, we confirm that the ABC- Bootstrap PTL improves the speed by 52% in the XOR gate. In addition, our technique has succeeded in the operation of no less than 4 pass-transistors connected in series at 0.5 V- V DD. Moreover, the ABC-Bootstrap PTL achieves 40% of the power consumption in the 4-bit MCC Adder while maintaining the operational speed. Simulation results also have shown improvement in the access time of SRAM and operation in sub-1 V operation. References [1] Y. Hirano, T. Matsumoto, S. Maeda, T. Iwamatsu, T. Kunikiyo, K. Nii, K. Yamamoto, Y. Yamaguchi, T. Ipposhi, S. Maegawa, and M. Inuishi, Impact of 0.10 m SOI CMOS with body-tied hybrid trench isolation structure to break through the scaling crisis of silicon technology, IEDM Tech. Dig., pp , [2] Y. Hirano, T. Ipposhi, H. Dang, T. Matsumoto, T. Iwamatsu, K. Nii, Y. Tsukamoto, H. Kato, S. Maegawa, K. Arimoto, Y. Inoue, M. Inuishi, and Y. Ohji, Impact of actively body-bias controlled (ABC) SOI SRAM by using direct body contact technology for low-voltage application, IEDM, Tech. Dig., Dec [3] K. Yano, Y. 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9 674 Masaaki Iijima received the B.E. and M.E. degrees in Electrical and Electronics Engineering from Kobe University, Kobe Japan, in 2003, and 2005, respectively. Since 2005, he has been in Graduate School of Science and Technology, Kobe University, and is currently a doctoral candidate. His research interest includes low power and high speed circuits design. He is a member of the IEEE and IPSJ. Masayuki Kitamura received the B.E. degree in Electrical and Electronics Engineering from Kobe University, Kobe Japan in He is currently a master course student in Graduate School of Science and Technology, Kobe University. His research interest includes low power circuit design for SOI LSIs. He is a member of the IEEE. Shigeto Maegawa received the B.S., M.S., and Ph.D. degrees in electronic engineering from Kobe University, Kobe, Japan in 1980, 1982, and 1996, respectively. He joined the Mitsubishi Electric Corporation in 1982, and now, work with Renesas Technology Corp. He was engaged in the R&D of dopants diffusion technology, CCD imaging devices, advanced SRAMs and SOI devices. Currently, he is in charge of the department in R&D of yield analyzing technology. Dr. Maegawa received the 2000 R&D 100 Award for the development of the SOI communication LSI. He is a member of the Japan Society of Applied Physics. Masahiro Numa received the B.E., M.E., and Dr.Eng. degrees in Precision Engineering from the University of Tokyo, Japan, in 1983, 1985, and 1988, respectively. From 1986 to 1989, he was a Research Associate in the Department of Precision Engineering at the University of Tokyo, where he became a Lecturer in After moving to Kobe University in 1990, he became an Associate Professor of the Department of Electrical and Electronics Engineering in 1995, and a Professor in His research interests include VLSI CAD and design, and image processing. He is a member of the IEEE, ACM, IPSJ. Akira Tada received the B.E. and M.E. degrees in electrical and electronics engineering from Kobe University, Hyogo, Japan, in 1995 and 1997, respectively. In 1997 he joined Mitsubishi Electric Corporation, Hyogo, Japan. Since then, he has been engaged in the development of CAD for LSI design. Since 2003, he has been with Renesas Technology Corporation, Hyogo, Japan. He is a member of the IEEE and IPSJ. Takashi Ipposhi received the B.S., M.S. and Ph.D. degrees in material science from the University of Tsukuba, Ibaraki, Japan, in 1983, 1985 and 1988, respectively. In 1988, he joined the LSI Laboratory, Mitsubishi Electric Corporation. He moved his affiliation from Mitsubishi Electric Corporation to Renesas Technology Corp. in Currently, he is engaged in the research and development of SOI device/process technologies. Dr. Ipposhi is a member of the Japan Society of Applied Physics.