Hybrid CMOS Rectifier Based on Synergistic RF-Piezoelectric Energy Scavenging

Transcription

1 3330 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 61, NO. 12, DECEMBER 2014 Hybrid CMOS Rectifier Based on Synergistic RF-Piezoelectric Energy Scavenging Thanh Trung Nguyen, Member, IEEE, TaoFeng, Member, IEEE, Philipp Häfliger, Senior Member, IEEE, and Shantanu Chakrabartty, Senior Member, IEEE Abstract This paper presents a novel CMOS hybrid rectifier that can simultaneously and efficiently scavenge energy from a low-amplitude radio-frequency (RF) signal and a low-frequency, low-energy signal from a piezoelectric (PZT) transducer. The piezoelectric signal is used for biasing a complimentary, cross-coupled rectifier (CCCR) chain to an operating point such that the RF signal energy can be efficiently harvested, even if its amplitude is well below the threshold voltage of the rectifier transistors. Thedevicesizesfortheproposed design have been optimized to achieve the maximum DC output voltage and the proposed design is shown to effectively eliminate dead-zones in the rectifier response. The measurement results show that a 6-stage hybrid rectifier (HR) can generate up to 1 V DC output voltage at a load current of 3 when a 300 mv peak-to-peak, MHz RF signal is applied in conjunction with a 10 KHz, 2 V piezoelectric signal. Using measured results from prototypes fabricated in a 90 nm CMOS process, the proposed HR is shown to yield a significant improvement in power conversion efficiency (PCE) for low levels of input power when compared to a conventional CCCR that has been implemented on the same die. Index Terms Energy scavenging, piezoelectric (PZT) sensor, power harvesting, radio frequency (RF), rectifier, voltage multiplier. I. INTRODUCTION SCAVENGING energy from the surrounding environment is attractive powering micro-sensor systems that have to conduct measurements while being permanently embedded or implanted inside a structure. Examples include implants inside a human body or smart-pebble type sensors inside concrete structures, where these sensors can no longer be physically accessed [1] [3]. In such systems, wireless power transmission (either using near-field or far-field) is a popular method to provide energy to the device. Far-field power transmission utilizes the plane-wave propagation between antennas, whereas nearfield power transmission relies on magnetic-field between two coils. In both cases, the induced RF signal on the coil(antenna) attached to the micro-sensor side is dependent on the RF frequency, communication distance and coil size [4] [6]. Manuscript received March 06, 2014; revised May 02, 2014; accepted May 27, Date of publication July 11, 2014; date of current version November 21, This paper was recommended by Associate Editor K.-H. Chen. T. T. Nguyen and P. Häfliger are with the Department of Informatics, Oslo University, Blindern, 0316, Oslo, Norway ( nttrung@ifi.uio.no; hafliger@ifi.uio.no). T. Feng and S. Chakrabartty are with the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI USA ( fengtao@egr.msu.edu; shantanu@egr.msu.edu). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TCSI Fig. 1. Model of one stage rectifier. In wireless energy-scavenging sensors such as in RF identification(rfid)sensors,arectifierisusedtoharvestenergyfrom an incident RF signal and to generate a DC source capable of driving the sensor circuitry. While the input power level is the most important factor in the far-field power transmission, the induced RF amplitudeisamorecriticalissuein the near-fieldpowertransmission. In this regard, a key parameter that affects the performance of any rectifier is the threshold voltage of the rectifying devices (e.g., diodes or MOSFETs). sets the lower-limit on the amplitude of the input RF signal (i.e., dead-zone) at which the rectifier can start harvesting energy. This limit in turn determines the communication distance and the size of the receiver coil(antenna). Also, the PCE of the rectifier deteriorates as the amplitude of the RF signal is reduced towards. In this paper, we propose a hybrid rectifying technique as a solution to overcome the threshold-voltage limitation and in the process extract power from more than one energy source. The hybrid rectifier uses a purely capacitive, high-amplitude, low-frequency piezo signal to boost the DC component of the AC signal controlling gate voltage of the rectifying transistors. This DC boosting level is purposely clamped within an optimal range allowing threshold compensation of the devices, and thus enabling the rectifier to effectively operate at ultra-low RF input signal levels. To the best of our knowledge, the proposed topology will be the first published rectifier that can rectify input RF voltages with amplitudes well below the nominal of the devices. The paper is organized as follows: Section II investigates the threshold compensation effect, Section III describes the analysis and design of the proposed HR, Section IV shows the measurement results and discussion, and Section V presents the conclusion. II. THEORETICAL ANALYSIS AND PROPOSED SOLUTION Fig. 1 shows the schematic of a simple energy harvesting system in which a diode-connected MOSFET serves as a rec IEEE. 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2 NGUYEN et al.: HYBRID CMOS RECTIFIER BASED ON SYNERGISTIC RF-PIEZOELECTRIC ENERGY SCAVENGING 3331 tifier. The rectifier is modeled by a series resistance and a parasitic parallel capacitance. These quantities consist of both linear and non-linear components and their values are dependent on the input voltage at the terminals of the rectifier. The parameters and represent the input reflection coefficient and the input impedance looking into the rectifier from the source. Typically, an impedance matching network is inserted between the power source and rectifier to maximize the intrinsic power delivered to the rectifier i.e.,. The power from the source needs to be greater than or equal to the threshold power-up level at which the rectifier starts conducting. Once this threshold is exceeded, the rectifier circuitry can effectively provide power to the load. Thus, the rectifier works as a non-linear device, and its operation shifts from a transient mode at the startup to a steady state condition. To avoid mathematical complications due to the non-linear operation, the following steady-state assumptions have made to facilitate intuitive analysis: 1) The power loss due to the reverse current of the rectifier is negligible. This implies that 2) and are constant at a given. 3) The rectifier operates over a low frequency range such that the impedance of the parasitic can be neglected. 4) An ideal impedance matching network is present between thesourceandtherectifier, i.e., all power from the source is absorbed completely by the rectifier The first three assumptions are valid when the input power level is approximately equal to the threshold power-up level of the rectifier [7]. We will examine how affects the performance of the system. From assumption (4), we have The power conversion efficiency of the rectifier PCE is calculated as (1) Fig. 2. Topologies for power harvesting from different power sources ((a) rectifiers connected in series in voltage domain (b) rectifier connected in series in current domain (c) hybrid rectifiers. In practice, most energy-scavenging sensors operate in an environment where multiple power sources could be available. The energy from each signal source could be harvested using separate rectifiers that operate independently. Their outputs can then be combined in series either in voltage domain as shown in Fig. 2(a) or in the current domain as shown in Fig. 2(b). In each case, the two rectifiers contribute to the total output power. Assuming that each rectifier has a different, the power delivered to the load can be estimated as (4) From (1) and (2), we have two important conclusions. First, if and are fixed, sets the minimum power required from the source or the sensitivity of the rectifier. Eq. (1) also implies that a very low power input source (e.g., a power source with a capacitive output impedance) can only provide a minimal to the load at a given, indicating that the load must also be capacitive. Second, the PCE of the rectifier can be increased by decreasing. These conclusions form the basis for recent designs reported in literature [8], [3], [4], [9] [11] where the goal is to reduce the effective of the rectifier. The expression of PCE in (2) can be rewritten as This equation also implies that the rectifier can achieve a higher PCE as the input voltage/power increases. This intuitive observation has been mathematically and experimentally confirmed in [4], [12], [13] (2) (3) For the configuration 2(a), we have and for the configuration 2(b), we also have where and denote the power transfer efficiencies of the overall energy harvesting system. Equations (4) (9) are valid only when both sources have power levels higher than the power-up threshold level. If one of the sources, for example, has a power level smaller than the power-up threshold level of the associated rectifier, that power source will not deliver any useful power to the load. For this case, the output power is generated entirely by the other source and the PCE of the system converges with that of a (5) (6) (7) (8) (9)

3 3332 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 61, NO. 12, DECEMBER 2014 Fig. 3. The concept of a hybrid voltage-multiplier and its potential application to a structural health monitoring sensor [3] that scavenges RF and vibration energy. single power source topology. If we can utilize the small power source in this case to reduce the of the rectifier that is associated with the other power source, we can achieve a higher PCE for the power source. This motivates the use of the hybrid configuration as shown in Fig. 2(c). An example of a sensor with multiple power sources is an RF identification (RFID) sensor that is attached to a mechanical structure [3]. One of the sources of energy could be ambient vibrations while the RF signal is used for powering and interrogation of the sensor as shown in Fig. 3. The energy that may be harvested from the ambient vibrations might be much lower than the energy that could be harvested from the RF source. In addition, a piezoelectric transducer used for vibrational energy scavenging is purely capacitive and exhibits a very limited current-driving capability [14], [15]. However, a near-field electromagnetic transducer (for scavenging RF signals) is purely inductive and has a high energy density. In such cases, a hybrid rectifier design as shown in Fig. 2(b) offers a solution that can exploit the different electrical properties of these sources in a manner that allows them to function in conjunction with each other and not independent of each other. Fig. 4. DC boosting effect simulation setup (,,, ). III. THRESHOLD COMPENSATION INVESTIGATION At low input RF signal level, a complimentary cross-coupled rectifier(cccr) cell [4] is preferred because it can achieve the highest power conversion efficiency due to a differential dynamic bias scheme. However, the gate-to-source voltage of the PMOS(NMOS) devices must be larger than to turn on the devices in the rectifier. Several stages can be cascaded to generate a sufficiently high DC output voltage ( ). If is output voltage generated by one stage, the number of stages (N) is determined as (10) To overcome the threshold limit of the MOS transistors, in particular when the amplitude of the input RF signal is relatively low, the DC component of their respective gate voltages need to be compensated - that is by providing a positive DC bias level for the NMOS devices and a negative DC bias level for the PMOS transistors. The effect of DC biasing is illustrated for a CCCR configuration as shown in Fig. 4(a). Fig. 4(b) shows an example of the DC output voltage plotted with respect to different DC bias levels when and.theresult shows that an optimal DC biasing voltage pair for NMOSs Fig. 5. Optimal bias voltages versus input RF signal. and PMOSs (, ) for a peak DC output voltage of 180 mv. When the DC biasing levels exceed the optimal values, the DC output voltage decreases gradually. This is because as the biasing level increases, the reverse drain current increases at a faster rate than the forward drain current. Note that when large DC bias levels are present, the transistors turn into the triode region. In this regime, the reverse current dominates and leads to a degradation in the rectifying properties. This degradation in rectifier performance has been analyzed and reported in literature [7], [10]. A set of simulations has been performed for a wide range of to find the optimal biasing levels, and the results are shown in Fig. 5. It is clear that the absolute DC bias voltage decreases as the RF amplitude increases. IV. PROPOSED HYBRID RECTIFIER STRUCTURE To generate the DC bias, the piezoelectric signal can be used since the signal frequency range is below 10 KHz, which can

4 NGUYEN et al.: HYBRID CMOS RECTIFIER BASED ON SYNERGISTIC RF-PIEZOELECTRIC ENERGY SCAVENGING 3333 Fig. 7. Simulated waveform of critical nodes in bias voltage generators on the Fig. 6.,,,. Fig. 6. Proposed HR: (a) main rectifier; (b) DC bias generator for NMOS gate terminals and (c) for PMOS gate terminals. be considered to be a DC signal with respect to the high-frequency RF signal. Another consideration of using the piezoelectric signal is that while the voltage levels of the signal could be high the current driving capability is very limited (due to low energy density of ambient vibrations). Thus, only capacitive loads like the gate of the rectifying devices can be driven by a piezoelectric transducer. Therefore, based on the different physical properties of the piezoelectric signal and the RF signal, we propose a HR in which the gates of the rectifier device are not biased by the RF signal but by the clamped piezoelectric signals. The CCCR structure has been extended here by adding an appropriate DC bias, enabling it to work at extremely low input RF signal levels. A. Circuit Topology As shown in Fig. 6, a pair of voltage generators is used for biasing the gates of the NMOS and the PMOS transistors respectively. The NMOS bias generator (Fig. 6(b)) consists of two symmetrical branches that generate two 180 phase-shifted voltages and each driving the gates of the crosscoupled NMOS transistors. The operation of the circuit can be understood by considering only the upper branch. The RF input provides the AC component similar to the main rectifier circuit (Fig. 6(a)). The amplitude of the piezoelectric signal is first bounded to the gate-to-source voltage of the vertical diode-connected PMOS transistor and the PN junction between the bulk and the lower S/D terminal that forms a bipolar diode. This is a PMOS configuration known as Tobi-element [16], whereby it is noted that the diode points in away direction opposite that of P1N. The resultant voltage is rectified by the horizontal diode-connected PMOS transistor to provide the DC bias level to. Thus, the low frequency clipped PZT signal is superimposed onto the RF signal. This DC boosted RF signal is subsequently used to synchronously drive the gates of the CCCR, instead of directly using the incident RF signals. This implies that the RF amplitude no longer need to exceed as in the CCCR case. The lower symmetrical branch and the branches in Fig. 6(d) that generate the biasing voltages and for the rectifying PMOSs operate similarly. Fig. 7 shows some of the simulated waveforms relevant to the biasing generators. As expected, the extremes of and are bounded due to the Tobi-elements deployed in the first stage of bias generators. The of the and the of the bulk-s/d P-N diode determines the positive and negative bounding limits, respectively. This depends on the size of the and can be adjusted to an optimal value, permitting the rectifier to efficiently harvest RF energy at ultra-low amplitude of RF signals. The width (W) and length (L) of the MOS devices serve as the optimization parameters that determine the PCE and the size of the rectifier is determined by the value of the coupling capacitor. The number of stages (N) in the rectifier is needed to be kept to a minimum value to achieve a higher PCE since the body effect in multistage topology increases of NMOSs in the last stages [13]. Therefore, the output voltage is maximized throughout by virtue of the following optimized sizing analysis. To ensure drain current matching between the NMOS and the PMOS, the aspect ratio is chosen. In our design optimization we will assume that the target output voltage is 1 V DC at a load current of 10 for an associated RF input of and a 10 KHz piezoelectric input. B. Choosing Device Sizes for the Main Rectifier For, the DC output voltage of a one-stage rectifier as a function of device size is shown in Fig. 8. When the transistor size increases, the ON resistance of the transistor decreases with the increase of which reduces the effective and. Therefore, there exists an maximal at an optimal. C. Choosing Device Sizes for the Bias Generator In this section, we present the procedure to optimize the size of the devices for the bias generator. Let us analyze the upper

5 3334 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 61, NO. 12, DECEMBER 2014 Fig. 8. versus device size of the main rectifier (,, and ). Fig. 9. Equivalent circuit of the upper branch of NMOS bias generator. branch of a NMOS bias generator as shown in Fig. 9. is the total parasitic capacitance at note, which is the total parasitic capacitance of and the NMOS transistor in the main rectifier. In the initial state, part of the current from the PZT signal is rectified through and charges the parasitic capacitor to increase the DC component of.under steady-state conditions, when the DC component of approaches the positive clipped PZT voltage, most of the current from PZT signal flows into the diode-connected i.e. The current is modeled as [17] (11) where is the subthreshold unit current, is the subthreshold region swing parameter, is the thermal voltage(typically 26 mv at 27 )and a is process constant and is mobility. Since is connected as a diode, and exhibits an amplitude in the range of mv, which is much larger than. Therefore, (11) is rewritten as Since the PZT current is calculated as (12) (13) where and represent the voltage amplitude and frequency of the PZT signal. From (12) and (13), since, the amplitude of can be solved using (14) It can be seen from (13) and (14) that the amplitude of is dependent on PZT electrical properties (voltage amplitude and frequency), PZT coupling capacitor and the size of transistor. Fig. 11 shows the dependency of on the size of and at several PZT electrical properties, and a comparison between the model given by (14) and simulation results obtained from Spectra simulator. This voltage amplitude determines the DC bias level of NMOS gate voltage, thereby affecting the output voltage generated by the main rectifier analyzed in part II. Since the current is very small, the voltage drop across the diode can be neglected. If is the optimal DC bias voltage for NMOSs transistors, the optimal amplitude of. Since the mobility has a positive temperature constant and the threshold voltage has a negative temperature constant [18], the decreases with the the increase of the temperature. Simulation results as showninfig.11whenthepiezoelectric source is set at and shows that the maximum change in is around 50 mv when temperature increases to 80 or decrease to if the nominal working temperature is set at 27. At the vicinity of the optimal bias voltage for both NMOS and PMOS transistors, the profile of the DC output voltage from rectifier is flat, as shown in Fig. 4(b), the temperature variation does not affect too much on the performance of the hybrid rectifier. Therefore from (14), we can find the optimal value pair ( and ) for each bias generator branch for a given PZT source. For example, at 0.3 V RF voltage, as investigated in part II, and with a PZT source ( and ), the optimal value pairs are found as, or. The diode connected serves as a rectifier for the clipped piezoelectric signals and can be chosen with a small size. Due to the capacitive voltage divider effect, the RF coupling capacitor needs to be large compared with the parasitic capacitance of to maximize the amplitude of. The device size for and are selected. V. MEASUREMENT RESULTS Prototypes of the proposed hybrid rectifier have been fabricated in a 90 nm CMOS process and for the sake of comparison, an equivalent CCCR topology has also been integrated on the same die. Note that the results corresponding to other rectifier topologies that have been reported in literature can not be used for comparison since the operating regime for the proposed topology is well below the threshold of the transistors. Both the rectifiers use a six-stage topology and were designed with a target specification of and.fig.12 shows the micrograph for both the rectifiers each of which occupy an active silicon area of approximately. Because the test chip was integrated with ESD protection diodes, the performance of the rectifiers degraded in comparison to the isolated topology. However, both rectifiers were equally affected, and therefore the comparison is still valid and unbiased. An impedance matching network can be designed to improve the total performance of both rectifiers, but designing a matching network is beyond the scope of this paper.

6 NGUYEN et al.: HYBRID CMOS RECTIFIER BASED ON SYNERGISTIC RF-PIEZOELECTRIC ENERGY SCAVENGING 3335 Fig. 10. versus at different PZT properties and values; (a) at, ;(b)at (c) at,. Fig. 11. versus temperature (, and. Fig. 13. Measurement setup of the test chip. Fig. 12. Micrograph of the designed rectifiers (a) Layout (b) Silicon chip. A. Hybrid Rectifier Characterization The test setup is shown in Fig. 13. These output signals are connected in series using large resistors of to both limit and indirectly measure the input current flowing into the circuit. To measure the input current of the RF signals, two small resistors of 100 are connected in series with the balun, and the input current is calculated by measuring differential voltage at two points X and Y [19]. Since the measuring probe has a loading capacitance of 15 pf, the intrinsic current flowing into the chip is calculated as To validate the performance of the rectifiers, two series of tests were conducted. The first test characterized the intrinsic performance of the HR. To make the experimental conditions more controllable, the differential piezoelectric signal is emulated using two signals, which are synchronized with a phase shift of 180 from two channels of a TGA1421 signal generator. The second test was performed using a real lead-zirconium-titanate (PZT-5H) based transducer which was configured as a bending cantilever. In both the setups, a MHz single-ended RF signal from a signal generator is converted into differential signals by using a transformer balun CX2147 with insertion loss of 0.3 db at the MHz frequency. (15) where is the intrinsic input current flowing into the chip and is the RF frequency. The input power is calculated using the intrinsic input current and input voltage. The input RF power and PZT power are calculated as (16) (17)

7 3336 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 61, NO. 12, DECEMBER 2014 Fig. 14. DC output voltage vesus input RF voltage. where isthenumberofstagesoftherectifier. The output power is calculated using the DC output voltage and loading resistance. The PCE is determined as (18) 1) Measured DC Output Voltage: Fig. 14 shows the DC output voltage versus input RF voltage at various loading conditions. It should be noted that the parasitic inductance and capacitance of the package and bonding wire distort the input RF voltage and the DC output voltage. Therefore, a better intrinsic performance can be expected when these parasitic effects are not present. In this measurement setup, the pseudo PZT signals are maintained at an amplitude of 2 V and a frequency of 10 KHz. The intrinsic input power of the pseudo PZT signal is calculated at. It is clear that the HR is nearly dead-zone free and is able to harvest power at ultra-low input voltages as low as 100 mv. On the other hand, a deadzone exists in the CCCR that only permits the circuit to harvest power when the RF input voltage amplitudes exceed (around 0.5 V) of the CMOS devices. For example, at a 300 mv input voltage and a load of,thehbr can generate a DC voltage of 1 V while the CCCR is almost silent and can only generate the same DC voltage level when the input voltage is 650 mv. This output power level can be sufficient for some sub-threshold mixed signal blocks that are widely used in sensor applications. The target DC output(1 V DC voltage and 1 DC current) is achieved at the input RF amplitude of 350 mv which is slightly larger than the simulation value. This is possibly due to the voltage drop across the bonding wire and the parasitic packaging elements. When the CCCR turns on, its DC output voltage increases at a faster rate than the HR and it surpasses the HR at large input voltage levels. The explanation for this behavior is that because DC bias levels in bias generator are constant with the RF amplitude while higher RF input voltage level requires lower optimal DC bias levels for maximal output voltage as analyzed in Part. II. However this performance degradation at high input RF levels is less significant because a sensor only needs a supply voltage of 1.2 V for normal operations (in a 90 nm CMOS technology). In addition, providing too large of a DC supply voltage at large RF input signal will decrease the power efficiency of the telemetry sensor system. 2) Measured PCE: Fig. 15 shows the PCE of the two rectifiers at different loads when the RF frequency and pseudo PZT signal are kept constant. We can see that the HR outperforms the CCCR in the low input power range. At loading resistor and input power, the PCE of the CCCR is only 9.7% while it is for HR four times larger with 40.3%. The PCE of the HR achieves a peak value before it decreases at higher input power levels. The peak value of PCEs increases with decreasing load resistor values. This means that the HR works more effectively at larger loading current condition. This is because the rectifying transistors are sized at high aspect ratio (W/L). Hence, they are more effective in generating larger currents. However, compared with the CCCR, the peak PCE of the HR becomes higher than the peak PCE of CCCR when gets larger. If is 680 K, for instance, the peak PCE of the HR is 14.36% at input power while the peak PCE of the CCCR is 13.67% at input power. It is also noted that when increases, the PCE curve of the HBR moves toward the small input power region and the HR can begin harvesting power at lower input power level. 3) Measured DC Output Voltage With Varying PZT Properties: Another set of experiments with a fixed RF signal but using a PZT signal with varying amplitude and frequency are conducted. Fig. 16 shows the DC output voltage as a function of the PZT voltage and PZT frequency. The DC bias of the hybrid VM may not be properly generated if the PZT amplitude is too small. The DC output voltage increases with voltage up to an optimal value. This optimal value decreases as the PZT frequency increases. Thereafter, it decreases gradually with the increase of the PZT s amplitude. This phenomenon was predicted by the analysis presented in part III.3 and is due to the DC boosting level of the gate control signals that increase with the PZT amplitude. This, in turn, increases the reverse current and lowers the DC output voltage. Another behavior of the HR is that the maximal DC output voltage of the HR decreases with the frequency of PZT. This is because lower PZT frequencies produces larger the drifts of the DC level of the gate controlling voltages due to charge leakage into the substrate. This effect lowers the maximal DC output voltage. B. Hybrid Rectifier in a Realistic Condition This section shows an example of the complete energy harvesting system that utilizes the proposed hybrid rectifier to harvest energy from the conjunction of a PZT electrical signal from a commercial piezoelectric bending cantilever and a MHz RF signal. The measurement setup is shown in Fig. 17. The standard double-qm Bending Motor D220-A4-303YB that has resonant frequency of 160 Hz is mounted on a Tira S5110 shaker controlled by a TIRA BAA 120 power amplifier. The piezoelectric cantilever is excited at a harmonic resonant frequency of 4890 Hz. The DC output voltage as a function of the acceleration amplitude is shown in Fig. 18. The DC output voltage increases monotonically with increasing the acceleration amplitude and reaches to the maximum value of 950 mv at an acceleration of 4.43 g. Thereafter, the DC output voltage starts decreasing. This

8 NGUYEN et al.: HYBRID CMOS RECTIFIER BASED ON SYNERGISTIC RF-PIEZOELECTRIC ENERGY SCAVENGING 3337 Fig. 15. Comparison of measured PCE versus input power (, and ). Fig. 18. DC output voltage versus RMS acceleration amplitude (, and ). Fig. 16. DC output voltage of the HR verse PZT input amplitude at different PZT frequency (, and ). Fig. 17. Measurement setup with a piezoelectric bending cantilever. behavior is consistent with the results from our analysis and the measurement results using the pseudo PZT signals. VI. CONCLUSION AND DISCUSSION We present a novel HR that generates a DC supply voltage from a subthreshold amplitude RF input signal. Its performance is boosted by using a secondary PZT power source to generate a DC bias/offset voltage for the cross-coupled rectifying transistors, thereby effectively reducing their. A detailed analysis was performed to obtain an optimal design for given signal source properties and loading conditions. The power conversion efficiency is significantly increased at low input power levels compared to the CCCR implemented on the same die. The measurement results validate the proposed idea and confirm the performance improvement for the HR for various amplitudes of a MHz RF signal. It is also shown that there is an optimal region of PZT amplitude that is required for the HR to operate efficiently. This novel rectifier is an excellent choice for energy harvesting applications where multiple low power energy sources

9 3338 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 61, NO. 12, DECEMBER 2014 coexist. This circuit also accommodate increased distances between the energy sources and the harvester and/or it may be used to miniaturize the antenna for the energy harvesting front-end. In fact, the proposed structure can be applied for a system with more than two energy sources with more than one hybrid rectifier. For example, if a system have one PZT energy source and two RF signal source: a MHz RF signal source from a tag reader and a 450 MHz/900 MHz RF signal source from a telecom mobile network. Two these RF energy source can be harvested by using two separate hybrid rectifiers with assistance from the PZT energy source to generate proper bias voltages for each rectifier. The harvested output energy from different hybrid rectifiers can be combined in parallel or serial as depicted in Fig. 2. REFERENCES [1] D. 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I: Reg. Papers, vol. 58, no. 8, pp , Thanh Trung Nguyen (M 10) received B.Eng degree in electronics and telecommunication engineering from Hanoi University of Science and Technology, Hanoi, Vietnam in 2005 and M.S degree in electrical engineering from Korea University, Seoul, Korea in He is currently working toward the Ph.D. degree at Oslo University, Oslo, Norway. From 2008 to 2010, he worked as an Analog IC designer in Doestek Ltd., Seoul. His research interests include low power mixed-signal IC design and energy harvesting for biomedical applications. Mr. Nguyen has served as reviewer for the IEEE TRANSACTIONS ON BIOMEDICAL COMPUTER-AIDED CIRCUITS AND SYSTEMS. Tao Feng (M 10) received the B.S. and the M.S. degrees in microelectronics from Tsinghua University, Beijing, China, in 2006 and 2008, respectively. He is currently working towards the Ph.D. degree at Department of Electrical and Computer Engineering from Michigan State University, East Lansing, MI, USA. His research interests include low poer analog IC, hybrid energy harvesting, RF circuit and antenna design. Philipp Häfliger (M 03 SM 10) received the Ph.D. degree from the Institute of Neuroinformatics at ETH, Zurich, Switzerland, in He then accepted a postdoctoral position in the Nanoelectronics group at the Institute of Informatics at the University of Oslo, Norway, where he is currently an Associate Professor. His research has focused on neuromorphic electronics and ultra-low-power ASIC design for biomedical devices and wireless microimplants. Dr. Häfliger has been the Chairman of the Biomedical and Life Science CAS (BioCAS) Technical Committee of the IEEE Circuits and Systems (CAS) Society, has contributed to in the organization of the IEEE ISCAS and BioCAS conferences, and has been a Guest Associate Editor for the IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS. Shantanu Chakrabartty (S 99 M 04 SM 09) received the B.Tech degree from the Indian Institute of Technology, Delhi, India in 1996, the M.S. and Ph.D degrees in electrical engineering from The Johns Hopkins University, Baltimore, MD, USA, in 2002 and 2004 respectively. He is currently an Associate Professor in the Department of Electrical and Computer Engineering at Michigan State University (MSU), East Lansing, MI, USA. From he was with Qualcomm Incorporated, San Diego, CA,USA,andduring2002 he was a visiting researcher at The University of Tokyo, Tokyo, Japan. His work covers different aspects of analog computing, in particular non-volatile circuits, and his current research interests include energy harvesting sensors and neuromorphic and hybrid circuits and systems. Dr. Chakrabartty was a Catalyst foundation fellow from and is a recipient of National Science Foundation s CAREER award, University Teacher-Scholar Award from MSU and the 2012 Technology of the Year Award from MSU Technologies. He is currently serving as the Associate Editor for IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, Associate Editor for the Advances in Artificial Neural Systems journal and a Review Editor for Frontiers of Neuromorphic Engineering journal.