THE BOUNDARY-SCAN HANDBOOK SECOND EDITION Analog and Digital

Transcription

1 THE BOUNDARY-SCAN HANDBOOK SECOND EDITION Analog and Digital

2 THE BOUNDARY-SCAN HANDBOOK SECOND EDITION Analog and Digital by Kenneth P. Parker Hewlett-Packard Company KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

3 ebook ISBN: Print ISBN: Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 1998 Kluwer Academic Publishers Dordrecht All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's ebookstore at:

4 Dedication This book is dedicated to the memory of an Uncle for whom I was namesake. Kenneth Fredric Parker,

5 TABLE OF CONTENTS List of Figures xiii List of Tables xviii List of Design-for-Test Rules xix Preface to the First Edition xxi Preface to the Second Edition xxiii Acknowledgement xxv 1 Boundary-Scan Basics and Vocabulary Digital Test Before Boundary-Scan Edge-Connector Functional Testing In-Circuit Testing The Philosophy of Basic Architecture The TAP Controller The Instruction Register Data Registers The Boundary Register Optimizing a Boundary Register Cell Design Architecture Summary Field-Programmable IC Devices Boundary-Scan Chains Non-Invasive Operational Modes BYPASS IDCODE USERCODE SAMPLE PRELOAD Pin-Permission Operational Modes EXTEST INTEST RUNBIST HIGHZ CLAMP Exceptions Due to Clocking Extensibility Subordination of IEEE Costs and Benefits Costs Benefits Trends Other Testability Standards 46

6 2 Boundary-Scan Description Language (BSDL) The Scope of BSDL Testing Compliance Assurance Synthesis Structure of BSDL Entity Descriptions 61 Generic Parameter 62 Logical Port Description 62 Standard USE Statement 63 Use Statements 64 Component Conformance Statement Device Package Pin Mappings Grouped Port Identification TAP Port Identification Compliance Enable Description Instruction Register Description Optional Register Description Register Access Description Boundary-Scan Register Description RUNBIST Execution Description INTEST Execution Description User Extensions to BSDL Design Warnings 2.4 Some advanced BSDL Topics Merged Cells Asymmetrical Drivers BSDL Description of 74BCT8374 Packages and Package Bodies STD_1149_1_ Cell Description Constants Basic Cell Definitions BC_0 to BC_7 User-Defined Boundary Cells Definition of BSDL Extensions Writing BSDL Summary Boundary-Scan Testing Basic Boundary-Scan Testing The Scanning Sequence Basic Test Algorithm The Personal Tester Versus ATE In-Circuit Boundary-Scan IC Test IC BIST 118 viii

7 3.2 Testing with Boundary-Scan Chains Chain Integrity Interconnect Test Connection Tests Interaction Tests BIST and Custom Tests Porting Boundary-Scan Tests Summary 4 Advanced Boundary-Scan Topics DC Parametric IC Tests Sample Mode Tests Concurrent Monitoring Non-Scan IC Testing Non-Digital Device Testing Mixed Digital/Analog Testing Multi-Chip Module Testing Firmware Development Support In-System Configuration Hardware Fault Insertion Design for Boundary-Scan Test Integrated Circuit Level DFT TAP Pin Placement Power and Ground Distribution Instruction Capture Pattern Damage Resistant Drivers Output Pins Bidirectional Pins Post-Lobotomy Behavior IDCODEs User-Defined Instructions Creation and Verification of BSDL Board-Level DFT Chain Configurations TCK/TMS Distribution Mixed Logic Families Board Level Conflicts Control of Critical Nodes Power Distribution Boundary-Scan Masters Post-Lobotomy Board Behavior System-Level DFT The MultiDrop Problem Coordination with Other Standards Summary ix

8 6 Analog Measurement Basics Analog In-Circuit Testing Analog Failures Measuring an Impedance Errors and Corrections Measurement Hardware Limited Access Testing Node Voltage Analysis Testing With Node Voltages Limited Access Node Voltage Testing The Mixed-Signal Test Environment Summary IEEE Analog Boundary-Scan Vocabulary and Basics The Target Fault Spectrum Extended Interconnect Digital Pins Analog Pins General Architecture of an IC Silicon Switches The Analog Test Access Port (ATAP) The Test Bus Interface Circuit (TBIC) The Analog Boundary Module (ABM) The Digital Boundary Module (DBM) The Instruction Set The EXTEST Instruction The CLAMP Instruction The HIGHZ Instruction The PROBE Instruction The RUNBIST Instruction The INTEST Instruction Other Provisions of Differential ATAP Port Differential I/O Partitioned Internal Test Buses Specifications and Limits Design for Testability Integrated Circuit Level Board Level System Level Summary 261 Epilog: What Next for /1149.4? 262 x

9 APPENDIX A: BSDL Syntax Specifications 263 A.1 Conventions 263 A.2 A.3 A.4 A.5 Lexical elements of BSDL Notes on syntax definition BSDL Syntax User Package Syntax Bibliography Index xi

10 List of Figures Figure 1-1: In-Circuit test setup with full nodal access. The component under test may be embedded within a board and connected to other components. 5 Figure 1-2: Cutaway drawing of a board resting on top of an In-Circuit, vacuumactuated test fixture: the bed of nails. The module interface pins are the mechanical interface to the ATE pin electronics, which are placed very close to reduce path lengths. 6 Figure 1-3: General, simplified architecture of an compliant Integrated Circuit. 9 Figure 1-4: State transition diagram of the sixteen-state TAP controller. 11 Figure 1-5: Architecture detail of a typical Boundary-Scan register with shift and parallel hold ranks. 17 Figure 1-6: Example of an instruction register cell design. The expanded cell shows several control signals generated by the TAP state machine. 19 Figure 1-7: A Typical Boundary Register Cell. 22 Figure 1-8: A Bidirectional pin with separate input and output Boundary Register cells. 23 Figure 1-9: A Bidirectional pin served by a reversible Boundary Register cell. 25 Figure 1-10: Compensating inversions in an input Boundary Register cell that monitors an inverting input buffer. 26 Figure 1-11: Compensating inversion in an output Boundary Register cell connected to an inverting output buffer. 26 Figure 1-12: Two logical symbols for typical boundary cells, one with an Update (UPD) flip-flop (A) and one without (B). 27 Figure 1-13: An example (adapted from [Whet95]) of an output cell design that eliminates both a discrete register stage and a multiplexer delay. 28 Figure 1-14: Block Diagram of a Boundary-Scan IC. 29 Figure 1-15: A field-programmable component with Boundary-Scan hard-wired into its I/O Blocks (IOBs). Each IOB starts out with bidirectional support for a component pin, but subsequent programming may reduce each to supporting input or output only. 31 Figure 1-16: A simple chain of Boundary-Scan ICs. 32 Figure 1-17: Code bit allocation in a Device Identification Register accessed by IDCODE. 34 Figure 1-18: Observe-Only Boundary Register cell for inputs. 40 Figure 1-19: Product introductions by Companies X and Y, and their relative performance. 44 Figure 2-1: BSDL use model within or outside of a VHDL environment. 51 Figure 2-2: BSDL used as a test driver. 53 Figure 2-3: A process for checking the compliance of an IC with the Standard. 54 Figure 2-4: An synthesis system that both creates and uses BSDL. 56 Figure 2-5: The relationship of a BSDL entity to the standard package and package body. 59 Figure 2-6: Candidate for merged cell design. 78 Figure 2-7: Design with input and control cells merged. 79 Figure 2-8: A design illustrating several merged cell situations. 81 Figure 2-9: Texas Instruments 74BCT8374 Octal D Flip-Flop with Boundary-Scan. 82

11 Figure 2-10: An abstraction of a Boundary Register cell showing capture data sources. 90 Figure 2-11: Cell architecture BC_1, a basic but very flexible design. 92 Figure 2-12: Cell architecture BC_2. This cell can capture its own Update latch content. 93 Figure 2-13: Cell architecture BC_3, an input cell with no Update latch. 94 Figure 2-14: Cell architecture BC_4, a cell with no Update latch and no series multiplexer. 95 Figure 2-15: Cell architecture BC_5, a control cell that can support HIGHZ-type behavior. 95 Figure 2-16: Cell architecture BC_7 (see the circuitry in the dotted line box) which supports bidirectional data flow. 97 Figure 2-17: A cell that captures a constant 1 during EXTEST. 99 Figure 3-1: Side view of a Surface-Mount IC soldered to a board. An open and a short are pictured. The poor quality joint will be invisible to electrical test methods, including Boundary-Scan. 106 Figure 3-2: TAP Controller state diagram showing path taken to shift an N-bit instruction into the Instruction Register. 108 Figure 3-3: The newly loaded instruction is activated when UPDATE-IR is passed, selecting a new data register targeted between TDI and TDO when we enter the Data Column of the state diagram. 109 Figure 3-4: Sequence of states traversed to capture data and shift it out while at the same time entering new data. 110 Figure 3-5: Completing a data shifting operation and updating the parallel hold portion of a data register. 111 Figure 3-6: An IC undergoing an INTEST function while loaded on a board. 117 Figure 3-7: A chain that has just passed CAPTURE-IR, loading all Instruction Registers with Figure 3-8: A Boundary-Scan chain of ICs with four interconnect nodes. 123 Figure 3-9: Interconnect test drives unique patterns assigned to each node from drivers to receivers. A short is shown that creates a Wired-OR result. 124 Figure 3-10: An interconnect open that prevents driven data from reaching one of two receivers on a node. This fact can help a diagnostic isolate the location of the open. 125 Figure 3-11: Simple interconnect test showing STVs (horizontal patterns) for 4 nodes. The columns are PTVs and represent the data as transmitted at each UPDATE-DR state. Note two nodes are bussed. 126 Figure 3-12: Three examples of bus wire driver opens not detected by interconnect shorts test. 132 Figure 3-13: Control cell fanout combined with board topology that results in undetected opens. 133 Figure 3-14: Parallel testing of two bussed nodes. 134 Figure 3-15: A case where four buses containing different numbers of drivers are tested in parallel. 135 Figure 3-16: A circuit where not all Boundary-Scan pins can be tested via interconnect test. 137 Figure 3-17: Example of potential interactions between a Boundary-Scan node and two non-scanned nodes. 138 xiv

12 Figure 3-18: Boundary-Scan nodes B and C that can interact (by shorting) with nodes A, D or F. 139 Figure 3-19: Two cooperating components provide stimulus vectors and capture a signature response for data path logic. 141 Figure 3-20: Developing and porting a manually generated test for similar applications. 142 Figure 3-21: Developing a Boundary-Scan test for similar applications. 143 Figure 4-1: The analog testing subsystem of an IC tester is used to switch load and test resources to measure analog parametric properties of an IC. 147 Figure 4-2: A simple circuit and its timing diagram showing setup and hold times, and the effects of system clock skew. 148 Figure 4-3: Simple circuit showing the relationships between the system clock and TCK during SAMPLE operation. 149 Figure 4-4: Concurrent sampling of component I/Os during system diagnostics, with sampled data compressed in a multiple-input signature analysis register (MISR). 151 Figure 4-5: Testing a non-scan IC U7 with a combination of physical nails and Boundary-Scan pins. 152 Figure 4-6: A timing diagram that shows how Boundary-Scan resources must be coordinated with the resources of a host ATE system. 153 Figure 4-7: Shorted inputs on a NAND gate that may not be detectable when tested by ordinary Boundary-Scan drivers. 154 Figure 4-8: A Boundary-Scan testable node that has a termination resistor to eliminate noise. 154 Figure 4-9: A mixed digital/analog IC with the Boundary Register partitioning the digital from the analog. 155 Figure 4-10: Two digital ICs that communicate by differential signaling, an analog technique. 156 Figure 4-11: Three examples of unusual differential signaling applications. 157 Figure 4-12: Multi-Chip Module shown in cross section. This example shows a multilayer ceramic PGA made of multiple dielectric and metalization layers. Bare IC die and other discrete components are mounted on the top surface. 158 Figure 4-13: Four macro states an FPGA/CPLD can be in and the transitions between them. 162 Figure 4-14: A BC_1 Boundary Register cell modified to support fault insertion. 164 Figure 5-1: Three pin layouts for TDI and TDO. 169 Figure 5-2: An oscillograph of a Ground-Bounce induced clock cycle on TCK during UPDATE-DR, measured at the package TCK pin referenced to component ground. 170 Figure 5-3: A high pincount IC with two 32-bit buses. 172 Figure 5-4: The transition timing for activities on the two buses in Figure Figure 5-5: Deliberately inserted delays in the Boundary Register control signal paths can be used to distribute driver edge placements in time. 173 Figure 5-6: A Boundary Register output cell design with the capability of monitoring its driver output pad during EXTEST. 176 Figure 5-7: A Siamese chain pair with common TCK and TMS signals, but independent data paths. Any number of chains could be linked in parallel this way. 183 xv

13 Figure 5-8: A Siamese chain pair with separate TMS lines, common TCK, and shared board-level TDI and TDO signals. 184 Figure 5-9: A simple chain with buffered TCK and TMS signals needed to avoid overloading. 185 Figure 5-10: A low-skew clock buffer with 50% duty cycle preserved by utilizing inversion. 186 Figure 5-11: A simple Boundary-Scan chain containing ICs from different logic families. Logic level conversion must be made between them. 186 Figure 5-12: A simple Boundary-Scan chain with a scanned level conversion interface for the parallel signals. Note the TCK and TMS lines must not have a scanned conversion. 187 Figure 5-13: A Boundary-Scan IC during test can set two normally complementary outputs to the same state, exciting conflicts in conventional ICs downstream. 188 Figure 5-14: Two Boundary-Scan nodes A and B need additional support from tester resources to enable proper testing. 189 Figure 5-15: A Boundary-Scan master interfaces between a microprocessor on one side and on the other. (The directions of TDI and TDO are reversed, reflecting mastership.) 190 Figure 5-16: The 74ACT8997 Scan-Path linker IC linking simple chains A, B and C. Extra shift stages (marked with * ) are inserted in the linked chain. These stages are actually resident in the 8997, which itself appears in a normal form at the end of the chain. 192 Figure 5-17: A system of several boards where each slot may accept several board types, or not contain a board at all. A simple chain through these boards would be broken at an empty slot. 194 Figure 6-1: A simple filter circuit and the actual circuit when parasitic capacitance is included. 198 Figure 6-2: Distribution of resistance values for a 4.7 Kohm resistors with a tolerance of ±5%. 199 Figure 6-3: Measuring impedance with current source stimulus (A) and with voltage source stimulus (B). 201 Figure 6-4: Measuring the impedance of a device on a board, connected to a silicon device (A), and as seen by an ATE system (B). 202 Figure 6-5: Devices may be connected into networks providing parallel pathways for currents. 203 Figure 6-6: Some sources of error in an ATE setup for measuring a simple impedance. 205 Figure 6-7: Error impedances for a delta measurement (A) and a 6-wire measurement configuration (B). 206 Figure 6-8: An operational amplifier with feedback resistor used as a current meter. 207 Figure 6-9: An operational amplifier setup to integrate a DC voltage V over time.207 Figure 6-10: An operational amplifier setup for DC Dual Slope Integration. 208 Figure 6-11: A dual slope integrator modified for AC measurements. 209 Figure 6-12: A dual slope integrator used to measure a reactive component. 210 Figure 6-13: Imaginary voltage waveform seen when measuring a capacitor. 211 Figure 6-14: A simple network containing four resistors with full nodal access. 212 Figure 6-15: Three-dimensional coordinates for graphing voltage differences. 213 xvi

14 Figure 6-16: Three-dimensional plots where only some components are potentially faulty at any one time. 214 Figure 6-17: Example circuit with access to node B removed. 215 Figure 6-18: Projecting the shadow of a three-dimensional object onto a plane. 215 Figure 6-19: Projections of failure spaces for R2 and R3 onto two of the voltage planes. 216 Figure 6-20: A mixed-signal printed circuit board. 217 Figure 6-21: Key to the color photograph appearing on the cover of this book. 219 Figure 6-22: Comparison of relative sizes of various features. 220 Figure 7-1: A mixed-signal circuit with some possible defects. 223 Figure 7-2: Examples of interconnections seen in mixed-signal circuits. 224 Figure 7-3: General (minimal) architecture of an compliant IC. 227 Figure 7-4: Detail of data register structure. 228 Figure 7-5: Symbols used for opened and closed switches. 230 Figure 7-6: Two or more ICs chained together. Note AT1 and AT2 are not required to be connected in parallel as shown here. 231 Figure 7-7: A TBIC switching structure inserted between AT1/AT2 and AB1/AB2. Note one-bit digitized values of the AT1/AT2 signals are generated. 232 Figure 7-8: Control structure for the switches shown in Figure Figure 7-9: ABM design detail for a generalized analog function pin. 237 Figure 7-10: Control structure for the switches shown in Figure Figure 7-11: ESD protection circuit for a typical pin (A) and an pin (B). 242 Figure 7-12: Alternative forms for the Boundary Register depending on whether INTEST and/or RUNBIST are supported. 243 Figure 7-13: An ATE system set up to utilize resources in an IC to measure an externally connected impedance. 244 Figure 7-14: Two measurements (A) and (B) used to find the voltage across Z for a known current. 245 Figure 7-15: Testing the digital core using INTEST. The analog core is not directly tested. 249 Figure 7-16: The analog core can be tested by patterns supplied at the D/A interface and by signals supplied or controlled by the ABMs. 250 Figure 7-17: An example implementation for differential inputs and outputs. 252 Figure 7-18: Example of a TBIC structure with one extension (k=2). 253 Figure 7-19: Control structure for the extended TBIC switches in Figure Figure 7-20: A conventional transmission gate switch and a shunting T switch structure that reduces coupling when the switch is off. 258 Figure 7-21: Degrees of guarding between two ATn signals. 260 xvii

15 List of Tables Table 1-1: Instruction Register operation during each TAP Controller state. 18 Table 2-1: Pin types in a BSDL logical port description. 63 Table 2-2: Function symbols and their meanings. 74 Table 2-3: Definition of Disable Result field symbols. 75 Table 2-4: Definitions of allowable CELL_TYPE symbols. 89 Table 2-5: Definitions of CAP_DATA symbols. 90 Table 2-6: Mode signal assignment for cell BC_1 used in any context. 92 Table 2-7: Mode signal assignments for cell BC_2 in the context of use. See text for an exception regarding INTEST. 93 Table 2-8: Mode signal assignment for cell BC_3. 94 Table 2-9: Mode signal assignments for cell BC_5. 96 Table 2-10: Mode signal assignments for BC_7 and its related BC_5 control cell. 98 Table 3-1: Example data bits for chains shown in Figure 3-7. The bits for IC7 are the first to appear at TDO. 120 Table 3-2: Data streams from chains shown in Figure 3-7 with IC4 TDI and TDO shorted together, producing a Wired-AND. 122 Table 3-3: Sequential Test Vectors for a set of nodes. The rows are STVs and the columns are PTVs. 129 Table 3-4: A set of test PTVs (the columns) for interconnect test. (The Notes are explained in the text.) 131 Table 3-5: Parallel test data for two bussed nodes. 134 Table 3-6: Test data required for bus wires with different numbers of drivers. 136 Table 6-1: Node voltages for the circuit in Figure 6-14 when the component values vary from nominal. 212 Table 7-1: Comparison of parameters of various switches. 229 Table 7-2: TBIC switching patterns (P0 through P9) for the switches shown in Figure Table 7-3: Assignment of TAP instructions to mode signal values for the TBIC. 234 Table 7-4: Selection of TBIC switch patterns versus Boundary Register cell content. 235 Table 7-5: Logic equations for TBIC switch control. 236 Table 7-6: ABM switching patterns (P0 through P19) for the switches shown in Figure Table 7-7: Selection of ABM switch patterns versus Boundary Register cell content. 240 Table 7-8: Logic equations for ABM switch control. 241 Table 7-9: TBIC extension switching patterns for the switches in Figure 7-18 for extension k. 254 Table 7-10: Selection of TBIC extension switch patterns versus Boundary Register cell content. 255 Table 7-11: Logic equations for TBIC extension switch control. 256 xviii

16 List of Design-for-Test Rules DFT-l: Place TDI and TDO pins on the end or the corner of a package to reduce their likelihood of being bridged by solder. 170 DFT-2: When possible, place power pins between TDI and TDO pins and other signal pins. 170 DFT-3: Ensure that worst-case switching of all IC drivers will not cause power/ground transients that disrupt the operation of the TAP controller. 174 DFT-4: Use higher-order bits of the Instruction Register capture pattern to implement an informal ID code. The bits captured must be predictable 0 s and l s. 174 DFT-5: If design-dependent bits are captured in the Instruction Register, then any combination of these bits should decode to the same operation. 175 DFT-6: Specify a tolerance period that drivers can withstand shorts to each other or to Power/Ground voltages. 176 DFT-7: Use self-monitoring output cells in the Boundary Register to improve Boundary-Scan diagnosis of shorts and opens. 177 DFT-8: For bidirectional pins, utilize a single-cell bidirectional design with a selfmonitoring capability (such as cell BC_7). 178 DFT-9: When the logic executes a pin-permission instruction, the system logic should be forced into a state that prevents internal conflicts. 178 DFT-10: When the logic returns to non-invasive mode, the system logic should stay in a state that will not conflict with board level signals. 178 DFT-l1: Use formal or informal ID codes to differentiate similar components or revisions of components. 179 DFT-l2: Consider board-level testing problems that will require user-defined instructions for their solutions, before final implementation of the logic. 180 DFT-13: Verify that a BSDL description matches the silicon implementation of on every component. 181 DFT-14: Before designing a board-level chain configuration, be sure that the software that will be used during testing will support it. 184 DFT-15: If there are field-programmable components in a chain of devices, group them together in the chain order and place the group at either end of the chain. 184 DFT-l6: Utilize simple buffering (where possible) of the broadcast TCK/TMS signals. Document the enabling and initialization requirements needed to preserve the protocol through TCK/TMS distribution. 185 DFT-17: Do not allow logical inversion in the TCK or TMS pathways. 186 DFT-l8: When mixed logic families are used on a board, use scanned level converters for the parallel signals and a non-scanned level conversion for TCK/TMS distribution. 187 DFT-l9: Check conventional portions of board circuitry that may be affected by Boundary-Scan test data for damaging conflicts that may be induced. Design disable methods into these portions that will make them insensitive to this testing activity. 188 DFT-20: Provide for the ability of a tester to disable conventional ICs whose outputs would otherwise conflict with nodes involved in Boundary-Scan tests. 189 xix

17 DFT-21: Provide for the ability of a tester to create strong drive values on weak nodes. 189 DFT-22: Make sure you locate and condition all Test Reset (TRST*) pins and all compliance enable pins before executing any Boundary-Scan tests. 189 DFT-23: Design analog and digital subsystems such that the analog power can be shut off while Boundary-Scan testing is being done. 190 DFT-24: If a Boundary-Scan master is used in a board design, provide for test equipment access and control of the side of the master s interface. 191 DFT-25: Ensure that a board, after any operation completes, will have safe states on all components and nodes. 193 DFT-26: Restrict implementations for system tests to simple system architectures not containing a multidrop scheme. 195 DFT-27: Eliminate all common conductive paths between a system pin pad and the ATn switches (SB1 and SB2). 258 DFT-28: Partition internal analog test buses (per section 7.4.3) to control on-chip cross talk, leakage, and capacitance. 258 DFT-29: Examine the location of switches for places where the circuit may be sensitive to parasitic coupling and leakage. Use enhanced switch designs in these areas to reduce these effects. 258 DFT-30: Analyse the layout of the ATn pins with respect to leakage and parasitic effects between them and other signals. 259 DFT-31: Group compatible ATAPs together on common ATn buses. Be prepared to accommodate more ATAP buses than there are TAP chains. 259 DFT-32: For ATn ports expected to be used in measurements of very high impedances, place a board-level guard wire between the ATn signals. 260 DFT-33: Consider which of all ATn ports in a system will be needed for system test and provide access to them. 260 DFT-34: Consider if noise-immunity testing of differential signaling is required in the system. 261 xx

18 Preface to the First Edition In February of 1990, the balloting process for the IEEE proposed standard P was completed creating IEEE Std Later that summer, in record time, the standard won ratification as an ANSI standard as well. This completed over six years of intensive cooperative effort by a diverse group of people who share a vision on solving some of the severe testing problems that exist now and are steadily getting worse. Early in this process, someone asked me if I thought that the P effort would ever bear fruit. I responded somewhat glibly that it was anyone s guess. Well, it wasn t anyone s guess, but rather the faith of a few individuals in the proposition that many testing problems could be solved if a multifaceted industry could agree on a standard for all to follow. Four of these individuals stand out; they are Harry Bleeker, Colin Maunder, Rodham Tulloss, and Lee Whetsel. In that I am convinced that the standard is the most significant testing development in the last 20 years, I personally feel a debt of gratitude to them and all the people who labored on the various Working Groups in its creation. Why do I feel that is more significant than, say, In-Circuit testing (mid 1970 s) or the various scan design approaches (mid 70 s again) such as LSSD? Surely these were very significant. However, the In-Circuit test technique, while the basis of several trillion dollars worth of electronics production, is basically an Ad-Hoc technique where the creation of a board test is only partially automatable and subject to potentially severe debugging problems. In short, every new board is an adventure. The various scan approaches were very significant in their ability to lead to the automation of test development. However, they were most successful when carried out within large, vertically integrated electronics companies. As such, they did not contribute to testing problem solutions of the electronics industry at large. A major contribution of is that it provides a standard mechanism for dissimilar segments of the electronics industry to provide support for testing problems without requiring them to understand all those various problems. As an example, members of the IC Merchant community have virtually no concept of the problems of board level testing; nor should they have to if they will provide the capability in their devices. Another major contribution of is revealed in the first half of its formal name, Standard Test Access Port. This Port is an I/O and control protocol as surely as RS-232 and Ethernet are. Combined with the open-ended extensibility of the standard, the standard is a gateway to new testing approaches. Built-In-Self-Test (BIST) immediately comes to mind. It is this particular focus that suddenly makes the standard attractive to IC designers. They say, well, I am being forced to add these four pins and some overhead, but, look at the neat things I could then do with it. These things are not limited to the field of testing. This book is aimed at professionals in the electronics industry who are concerned with the practical problems of competing successfully in the face of rapid-fire technological change. Since many of these changes affect our ability to do testing and hence cost-effective production, the advent of the standard is rightly looked upon as a major breakthrough. However, there is a great deal of misunderstanding about

19 what to expect of and how to use it. Because of this, this book is not a re-hash of the standard nor does it intend to be a tutorial on the basics of its workings. The standard itself should always be consulted for this, being careful to follow supplements issued by the IEEE that clarify and correct it. Rather, this book attempts to motivate proper expectations and explain how to use the standard successfully. xxii

20 Preface to the Second Edition I was delighted when Carl Harris of Kluwer asked me to consider producing this second edition. This indicated that he believed and the newly emerging standards are of continuing interest to the engineering profession. IEEE standards, when embraced by practicing engineers, are living entities that grow and change quickly. That justifies this edition, but also should serve as a warning that the material in this book may be superceded by upcoming changes in the standards. Always consult the most recent editions of the standards themselves for information needed for implementation. This book is intended to describe these standards in simple English rather than the strict and pedantic legalese encountered in the standards. After reading this book, it is my hope the reader will find it easier to follow the course of the standards themselves. Since the first edition of this book became available, the IEEE has formalized the Boundary-Scan Description Language (BSDL) and made it a part of the standard. Indeed, to be compliant, devices must now be documented in BSDL so that computer applications can use their features. The standard is now over eight years old and has a large infrastructure of support in the electronics industry. Today, the majority of custom ICs and programmable devices contain New applications for the protocol have been introduced, most notably the In-System Configuration (ISC) capability for Field Programmable Gate Arrays (FPGAs). This book also introduces the very recently balloted standard, IEEE Mixed-Signal Test Bus. This standard builds upon the base created by In 1990, it was not at all clear how analog pins in mixed-signal devices should be treated by a testability standard. Now that exists, the two Working Groups have begun the process of reconciling the two, with the possibility that the two documents will be merged together. Be alert for this event since it will mean more change in the future. Finally, the cover of this book shows a picture of what is driving our industry today. (See Figure 6-21 on page 219 for a key and discussion of this photograph.) Miniaturization is rampant in many sectors of our industry. Two examples are cellular telephones and handheld video cameras. A trend in our industry is that miniaturized components are becoming the low-cost alternative because of the volumes that consumer applications demand. Thus, those portions of industry that don t need these components for reasons of density will still find it attractive to adopt them. This portends an increase in testing problems that and are meant to solve. It is my sincere hope that this book will be of some use in solving these problems.

21 Acknowledgment I d like to acknowledge those who contributed to this effort. Significant technical contributions have been made over several years by Stig Oresjo, Ken Posse, John McDermid and Rod Browen. Beth Eikenbary made management support happen. Others who influenced this work were Colin Maunder, Rod Tulloss, Chi Yau, Najmi Jarwala, Lee Whetsel, Gordon Robinson, Peter Hansen, Tom Williams, Luke Girard, Dick Chiles, Larry Saunders, David Simpson, Grady Giles, Tom Langford, Markus Robinson, C. J. Clark, Carl Thatcher, Adam Cron, Steve Sunter, Mani Soma, Keith Lofstrom, Steve Dolens, Brian Wilkins and Ramaswami Dandapani. Special mention goes to my friends at Matsushita Electric Industries in Osaka, Japan who worked incredibly quickly to produce working silicon containing structures. They are Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa, Atsushi Kukutsu and Ren Franse. Reviews of various manuscripts were conducted by Anne Dudfield and John McDermid of Hewlett-Packard, Ben Bennetts of Bennetts Associates, Colin Maunder of British Telecom and Keith Lofstrom of KLIC Incorporated, directed by Carl Harris of Kluwer Academic Publishers. All errors and omissions that survived their careful efforts are my own. I am indebted to my wife Jana, and my eight and six-year-old daughters Katherine and Lisa who missed paternal contact while their father spent all those hours in the basement. Without their support, I could not have completed this work. I thank them. Now that this is finished, I look forward to making it up to them. Fort Collins, Colorado