CHAPTER 2 PWM AND PSM DC/DC BUCK CONVERTERS

Transcription

1 8 CHAPTER 2 PWM AND PSM DC/DC BUCK CONVERTERS PWM (Erickson 997) and PSM (Ping Luo et al 26) DC DC converters are categories of switching-mode voltage regulators. In these types of converters, transistors are operated as switches in saturation or cut-off regions, which dissipate much less power than that of linear regulators. The controllers suitably driving the switches based on the error between feedback and reference values effect voltage regulation. This chapter includes modeling and simulation of PWM and PSM buck converters. Circuit operation, modeling and simulation of PWM converter is included in section 2. and that of PSM converter in section 2.2. Results of observations on the non-linear phenomena of respective converters are included at the end of each section. 2. PWM DC DC BUCK CONVERTER A PWM dc dc buck converter circuit in Figure 2. consists of a controllable switch S, a freewheeling diode, an inductor L, and a filter capacitor C. Resistor R represents a dc load. Power MOSFETs are preferred as controllable switches due to their high switching speeds. DC power source at the input is often an unregulated varying voltage source. Switch is driven from a PWM controller designed to modify the switching duration to control the output voltage. Diode is chosen to be a fast recovery or Schottky type.

2 9 MOSFET L + Vin - C R PWM CONTROLLER Figure 2. PWM Buck converter 2.. Circuit Operation MOSFET switch, which is controlled by a PWM controller, is turned ON and OFF at a predetermined frequency. This results in the DC input voltage chopped and presented as a rectangular wave to the filter stage. LC filter smoothes out the ripple and the average output voltage v at steady state is given by v =dv in. Output voltage is controlled by suitably modulating the pulse width or TON duration in PWM control. Sample of the output voltage is compared with reference voltage and the error voltage after due compensation is compared with a switching frequency saw tooth wave. The comparator output

3 2 drives the switch and controls the output by suitably modifying the pulse width or TON. Voltage fed to the LC filter due to switching operation is as shown in Figure 2.2. Voltage in V Time in ms Figure 2.2 Input voltage presented to LC filter due to switch action An ideal filter results in ripple free output voltage with % efficient converter assuming that the switches are also ideal. LC filter is so designed that its cut-off frequency is well below the switching frequency so that the switching frequency components are not passed to the output with significant amplitude. Voltage across C and inductor current are shown in Figure 2.3. A practical switching converter, even though superior in efficiency to linear converters, has output voltage with ripple and poor in response.

4 2 il in A and vc in V il in A and vc in V Time in ms Figure 2.3 Typical waveforms of inductor current i L and capacitor voltage v C 2..2 Operating Modes of Converter The converter can operate in two distinct modes namely Continuous Conduction Mode (CCM) and DCM (Erickson and Maksimovic 2). Under CCM the inductor current i L is always greater than zero and is never discontinuous. Hence every cycle starts with a nonzero inductor current. In the case of DCM the inductor current becomes zero before the switch is closed for next cycle. Hence in the case of DCM operation every cycle starts from a zero inductor current after a brief period over which the inductor current was zero within the previous cycle. The converter can also operate in critical mode at the border with inductor current zero just becoming zero for an instant of time and this duration over which the current was zero can be taken to be zero. This mode is also known as Border Conduction Mode or Boundary Conduction Mode (Basso 28).

5 22 Figure 2.4(a) shows a buck converter circuit. An ideal switch represents the transistor and the diode has no forward voltage drop. Referring to Figure 2.4 (b) with the switch ON, voltage V d is equal to V in and as V in is greater than V o the current through the diode rises linearly. From Figure 2.4 (c) with the switch OFF, voltage across the inductor reverses and the voltage V d is equal to zero. The diode conducts the inductor current. Inductor voltage is now -V o. The inductor current I L decreases and till the end of OFF period if the current is above zero this mode is continuous conduction mode. The inductor voltage and inductor current corresponding to continuous conduction mode is shown in Figure 2.5. (a) (b) Figure 2.4 Continuous conduction mode (a) Buck converter circuit (b) Switch open and voltage across inductor is (v in -v ) (c) Switch closed and voltage across inductor is (-v )

6 23 (c) Figure 2.4 (Continued) Figure 2.5 Inductor voltage and current-continuous conduction mode With the converter operating in continuous conduction mode at steady state with input and output voltages fixed, load current and frequency constant, the duty ratio is constant at D and the output voltage is given by Equation (2.) Vo = D V in (2.)

7 24 where, V Output voltage V in Input voltage D Duty cycle TON D (2.2) T T T ON T OFF f sw (2.3) T ON ON state duration (S) T OFF OFF state duration (S) T Total duration (S) f sw Switching frequency (Hz) During the T OFF period if the inductor current falls to zero for a portion of the switching cycle as shown in Figure 2.6 the converter is said to be in discontinuous conduction mode. The current starts at zero, reaches a peak value, and returns to zero during each switching cycle. The circuit takes up a third configuration as shown in Figure 2.7. Figure 2.6 Inductor current - Discontinuous conduction mode

8 25 Figure 2.7 Third circuit configuration- Discontinuous conduction mode With the converter operating in continuous conduction mode at steady state with input and output voltages fixed, load current and frequency constant, the duty ratio is constant at D and the output voltage is given by Equation (2.4) V V LI 2 D TV in 2 in (2.4) where I output current Modeling of voltage mode controlled buck converter A switching converter model is useful to study how the input voltage, load current, or the duty cycle variations affect the output voltage. The switching buck converter switching between two time-invariant systems during each switching period under continuous conduction mode is actually a time- variant system due to the switching action. It is possible to approximate this time-variant system with a linear time-invariant continuous-time system using State-space averaging technique (Middlebrook and Cuk 977). A buck converter is modelled using state space averaging (Forsyth and Mollov 998) and simulated using MATLAB/SIMULINK. Model

9 26 considers the ESR of the capacitor and diode forward drop and neglects the inductor series resistance. Regulation is effected through voltage mode control and analysed for performance and exhibition of nonlinear phenomena with input voltage as parameter. State space averaged model for buck converter: When two or more than two sets of state equations each describing a state of the circuit due to action of switches are available then these state equations can be averaged over the switching period by dividing the weighted sum with the period. In the converter studied under continuous conduction mode there are two sets of equations available, with one set for switch closed and one set for the switch open. These state equations are averaged over the switching period. A buck converter is modelled with diode forward drop and ESR of filter capacitor considered. State equations are developed by applying KVL and KCL to each of the two circuits and averaged. Figure 2.8 Buck converter circuit

10 27 L L Vin C R C R rc rc (a) (b) Figure 2.9 Equivalent Circuit with (a) switch closed (b) switch open for developing the state equations When the switch is ON: Applying KVL and KCL for the first configuration dil rc rc il vc vin i (2.5) dt L L L L dvc il i (2.6) dt C C v rc i v r (2.7) L C Ci i in i L (2.8) These equations can be written in the form x y A x C x B u Du from t= to Ton (2.9)

11 28 When the switch is OFF: Applying KVL and KCL for the second configuration di L dt rc i L L v L C v L d rc i L (2.) dv dt C i C L i C (2.) v rc i v r (2.2) L C Ci i in (2.3) x y A x 2 C x 2 B u 2 D u 2 from t = Ton to T, over a duration of (-d)t ( 2.4) Averaged state space equations with duty ratio d are dil rc d d rc il vc vin vd i (2.5) dt L L L L L dvc il i (2.6) dt C C v rc i v r (2.7) L C Ci i in di L (2.8) The averaged state space equations are x y Ax Cx Bu Du (2.9)

12 29 where A da d A 2 (2.2) B db d B 2 (2.2) By linearising the above equations, the small signal representation can be got. In the state space form xˆ Axˆ Bû (2.22) ŷ Cxˆ Dû (2.23) T xˆ î L vˆc (2.24) T û vˆ in î (2.25) dˆ T ŷ î in vˆ (2.26) A rc L C - L (2.27) B D L rc L C V in V L d (2.28) C D r (2.29) C il D (2.3) r C

13 3 xˆ î L vˆc T and T û vˆ î dˆ are inductor current, capacitor voltage, input voltage, output current and duty cycle perturbations. in The actual and average models in MATLAB / SIMULINK are given below in Figures 2. to 2.2 for the converter. v /L s il il 2 d R L R 3 i_ou t /C s Vc 2 V Figure 2. SIMULINK actual model of the buck converter 2 Vino Vino IL D Do Delta _Vin Do Delta_Vin Delta_D Vo Output Voltage Inductor Current 2 Delta _D I Io Ic Capacitor Current Scope Io Delta_Io 3 Delta _Io Buck Converter State Space Averaged Model Figure 2. State space averaged model of buck converter

14 3 D duty ratio d c g PWM block D S i v Scope Diode Figure 2.2 Simulink PSB model of converter 2..3 Voltage Mode Controlled Buck Converter Voltage-mode controller is a type of fixed-frequency PWM controller. It consists of a clock generator corresponding to the switching frequency, a voltage error amplifier with compensator that generates control voltage, a ramp generator operating in synchronism with the clock, and a comparator to compare the control voltage with the sawtooth signal. The output of the comparator is used to drive the controlled switch. Buck converter with PWM voltage mode control is shown in Fig.2.3. Output voltage is sensed with a voltage sensor, with a sensor gain, which may be a voltage divider consisting of precision resistors suitably selected for the available reference voltage. The output voltage signal is compared with the reference voltage. If the output voltage is lower than the desired value, a positive error voltage is produced. The compensator processes the error voltage and the control voltage is produced with a d, which is positive in this case, and the duty cycle is increased. This increases the output voltage.

15 32 The stability and transient response depend on the compensator circuit. Figure 2.4 shows the overall transfer function block diagram with input voltage and load current as disturbances. MOSFET L gain + Vin - D C R Comp Vcon GAIN & Gc gain Comp V 5/8V + Vref - 4kHz Figure 2.3 Voltage mode controlled PWM Buck converter Figure 2.4 Closed loop with compensator

16 33 The transfer function of the PWM generator is basically /V M, where V M is the peak to peak voltage of ramp given by (V U -V L ) where V U is the peak value and V L is the valley as shown. Figure 2.5 PWM generation The transfer function of the buck converter and PWM is: G( s ) V M rccs Vin 2 L s LC s rc C R (2.3) A compensator can be designed that improves phase margin and static gains to better the performance. For voltage mode control feedback the compensator gain is Gc. For a closed loop system: The loop gain T(s) = H(s)G c (s)g vd (s)/v m (2.32) Then input voltage disturbance to output transfer function is

17 34 vˆ s vˆ s in G v vˆ ref in T s s (2.33) î o Load current disturbance to output voltage transfer function is vˆ s î s vˆ ref vˆin Z s T s (2.34) with vˆ s G s dˆ s G s vˆ s Z s iˆ in o ( s) v v d in where G vd (s) is converter control to output transfer function with line and load disturbances assumed zero. G vin (s) is converter line to output transfer function with control input and load disturbance assumed zero. Z o (s) is converter output impedance with control input and line disturbance assumed zero. Hence the feedback reduces the impact of disturbances affecting the output due to large gain. vˆ s vˆ ref H T T G s vin T vˆ in s Z s T iˆ ( s) o with T s H ( s) Gc ( s) Gvd ( s) V M Loop Gain (2.35)

18 35 For the converter with L=56 H, C=47 F with rc=25m and R=5 o = 3.693krad/S z = 4.84krad/S =.88 G(s) = (538) (s+72)(s s+3.64X 6 ) - Transfer function: s.9637e s^2 389 s.364e 7 The step response of the uncompensated system is in Figure 2.6. For the Uncompensated unity feedback system, sensor gain and gain of PWM are assumed to be one..4 Step Response.2 Sys tem: gv d Peak amplitude:.23 Overshoot (%): 3.8 At time (sec):.8 Sys tem: gv d Settling Time (sec):.528 Sys tem: gv d Final Value: Amplitude Time (sec) x -3 Figure 2.6 Step response of uncompensated system

19 36 The peak response is 3% and it is desirable to decrease it to be within 25%. The settling time is.53 ms and there is steady state error. The Bode plot of the same system is shown in Figure Bode Diagram Magnitude (db) Phase (deg) Frequency (rad/sec) System: gvd Phase Margin (deg): 6 Delay Margin (sec): 9.58e-5 At frequency (rad/sec):.93e+4 Closed Loop Stable? Yes Figure 2.7 Bode plot of uncompensated system A tuned PID controller ( /s +.76e -5 ) using Zeigler Nichols Method is considered for simulation. The step response is shown in Figure 2.8. The steady state error is not present. The overshoot is around 25% and the settling time is.7ms. Bode plot of the compensated system is shown in Figure 2.9 and SIMULINK model with PID control shown in Figure 2.2.

20 37.4 Step Response From: Input To: Out().2 System: Gvdc I/O: Input to Out() Peak amplitude:.26 Overshoot (%): 25.5 At time (sec):.34 System: Gvdc I/O: Input to Out() Settling Time (sec):.7 System: Gvdc I/O: Input to Out() Final Value:.8 Amplitude Time (sec) x -3 Figure 2.8 Step response of compensated system 5 Bode Diagram From: Input To: System: Out() Gvdc I/O: Input to Out() Frequency (rad/sec):.3e+4 Magnitude (db):.848 Magnitude (db) Phase (deg) Frequency (rad/sec) System: Gvdc Phase Margin (deg): 94.4 Delay Margin (sec):.59 At frequency (rad/sec):.4e+4 Closed Loop Stable? Yes Figure 2.9 Bode plot of compensated system

21 38 Figure 2.2 SIMULINK Model of PWM Buck converter with PID control 2..4 Simulation of Voltage Mode Controlled Converter under CCM The actual model and average model of the PWM buck converter are simulated using MATLAB/SIMULINK and the schematic using PSIM for input voltage disturbance and load disturbance. A buck DC/DC power stage is designed for the specifications in Table 2.. Table 2. Specifications of power stage Item Symbol Min Typ Max Unit Input Voltage V in V Output voltage V 5 V Output Current I 2 ma Output Voltage Ripple V ripple 5 mv

22 39 The following parameters in Table 2.2 are considered in the simulation of the voltage mode controlled buck converter. Load resistance is typically 5 Ohms corresponding to a load current of A and the load is varied down to ma at light load. Table 2.2 Parameter values considered for simulation L 56uH C 47uF R 5 to 5 Ohms, 5 Ohms Typ V ref T 5V 25uS v d.4 r C.25Ohms Results. Input voltage at 2V, ref. voltage at 5V and the load current A The output voltage is controlled to be constant at 5V when a voltage of 2 V is applied as input. Load resistance R is chosen to be 5. The load current is A. The inductor current and output voltage of the converter are shown in Figure 2.2. The output voltage v o,max = 5.2 V and v o,min = 4.97V and the ripple is 5mV p-p (approx).the inductor current ripple is.4a (approx).

23 4 Figure 2.2 Inductor current and output voltage of converter The PSIM simulation results are shown in Figure 2.22 for the same converter parameters. Output voltage is controlled to be 5V with an input voltage of 2V. The load resistance of 5 resulted in a load current of A. The output voltage v o,max = 5.27V and v,min = 4.974V and the ripple voltage is 53mVp-p. The inductor current ripple is.4a (approx). The phase plot in Figure 2.23 indicates that both the inductor current ripple frequency and the capacitor voltage frequency are equal and is equal to the switching frequency and the operation is period I.

24 4 5.4 Output Voltage in V [.24587, 5.272] [.24628, ] Ripple.58%.3 Ind Current in A Time (s) Figure 2.22 Output voltage ripple for VM controlled buck converter vc in mv 54.m 52.m 5.m 498.m 496.m I2 Figure 2.23 Phase plot between v C and i L showing period I operation

25 Observations with Variation in Input Voltage/load Response of the converter to the following transients are studied. The input voltage is varied from 2 to 2V in step keeping load current constant at A. Output response to a step change in input is plotted and is as shown. Input voltage increases by 8 volts in single step at time instant.2 msec. This results in a transient, which decays and settles in.5 ms as shown in Figure 2.24 SIMULINK and Figure 2.25 PSIM. The peak overshoot is.3v and the transient settles in.5ms. PWM Converter Average Model - Response to Step Input Voltage Disturbance vo (v) Time (S) Vin(V) Time(S) Figure 2.24 Response to a step change in input voltage PWM control

26 43 v (V) vin(v) Time (ms) Figure 2.25 Response to a step change in input voltage PWM control 2V. The load is varied from.5a to A at nominal input voltage of vo (V) io (A) Time (S) Figure 2.26 Response to a step change in Load PWM control

27 44 6. io (A) vo (V) Time (ms) Figure 2.27 Response to a step change in Load PWM control simulated with PSIM 2..6 Bifurcation and Chaos in PWM DC DC Converter Bifurcation is the qualitative change in the dynamics of a system that occurs when a system parameter is changed (Di Bernado et al 998, Dean and Hamill 99). It is a nonlinear phenomenon, which can be studied through bifurcation diagrams, which is the most commonly used tool for capturing bifurcation behavior. follows: The procedure for construction of the bifurcation diagram is as. Let µ be the parameter that is varied. Start with an initial value of µ. 2. Generate a large number of say consecutive values of a state variable x, from the iterative map of the form x n+ =f(x n ). 3. Discard the initial transient, say, the rst 5 values. The remaining 5 values of x form one data set.

28 45 4. With an increment in µ, repeat steps 2 and 3 for another data set. 5. Repeat 4 over a chosen range of µ. 6. Plot each data set against µ. The parameter, which is varied, is plotted along the x-axis and the state variable is plotted along the y-axis. If the system were operating under period I, for a particular parameter value, there would be one point along the y-axis against that parameter value. If the system were operating at period II at some other value of the parameter, then there would be two points against that value. If the system were chaotic there would be a large number of points against that value A Method to generate stepped input voltage variation A method to obtain the bifurcation plot is described below. The input voltage is taken as the parameter and is varied from a minimum voltage to a maximum voltage up to which, the bifurcation plot is required. Every level of the input voltage is maintained over a duration equal to that of cycles and data corresponding to the first 5 cycles in each level are not considered to avoid data during transients that may be involved due to step increase from one level to another. Input voltage is increased in steps with the help of the following circuit in Fig for bifurcation plot.

29 46 PE P C/ P U/D R Figure 2.28 Schematic to generate a stepped input voltage variation The up/down counter is set to count up and the square wave oscillator frequency is selected suitably to include some cycles of clock frequency. A voltage dependant voltage source accepts input from the counter output and the source voltage increases in steps as the counter counts up. Each voltage level stays constant over cycles of clock frequency. At the end of cycles of clock the source voltage increases by volt. It is possible to alter the step size by adjusting the gain of the source. For example if the gain is set to be. the voltage increases in steps of. and so on. V5 V Time (s) Figure 2.29 Stepped input voltage variation and sampling pulses

30 47 Figure 2.29 shows a typical source voltage waveform and the state variable sampler pulses. Each burst of pulses represent 5 sampling pulses, which sample the variable to be plotted. On every step increase in source voltage, the sampling clock generates pulses but initial 5 pulses are blanked out and are not present to avoid the transients due to step increase in voltage. But in fact to determine the period doubling, sampling at two successive clock cycles should be sufficient. For the converter under study, for different input voltages the state variable v C, is plotted against input voltage. Characteristic to be observed is the periodicity of the operation and changes if any. Period I operation would be observed when ripple frequency equals the switching frequency or the frequency at which the system is driven. Stable converters exhibit periodic steady state behavior. State variables repeat cyclically with period T. Stroboscopic Poincar'e map, an important tool for studying stability of periodic orbit replaces the continuous time system with an equivalent discrete time system. The Poincar'e map of equivalent discrete time system P ( x ) : R n R n P ( x x with ( t) t T a periodic solution with ) t T, t, period I, has an attracting fixed point to which the state converges after transients die down. If the converter is not stable the fixed point is not an attractor and there would be divergence away from the fixed point. Therefore stability of the fixed point of the map determines the local stability and attracting fixed point corresponds to periodic steady state of continuous time system. A fixed

31 48 point of a mapping is stable if and only if its characteristic multipliers or Floquet multipliers all lie in the unit circle in the complex plane (Hamill D C et al 992). These multipliers are similar to gradient of the mapping in one-dimensional case and are eigen values of the Jacobian evaluated at the fixed point. In the converter under study input voltage is varied from 2V to 2V for which it is designed. Stroboscopic map, plotted for i L, the inductor current and v C, the capacitor voltage is observed using MATLAB/ SIMULINK. The voltage is varied in small steps from 2V. In every step the capacitor voltage, which is the state variable, during a particular instant in each switching cycle is obtained. Due to this the map can be called as stroboscopic switching map. Since there may be transient in each step voltage for several initial cycles are discarded and after sufficient switching cycles elapse the values are obtained and stored. During the same instants of time inductor current is also obtained and stored. These may be plotted with time instants to obtain the bifurcation diagram. If the steps are close enough the diagram would be smooth. These two state variables can be plotted with one as a function of other. The section can be moved over the switching period wherein time is the third variable for a particular input voltage. The strange attractor at a particular input voltage and time instant within cycle is also obtained. Period I operation is observed throughout and there was no nonlinear phenomenon (Banerjee and Verghese 2) exhibited over the entire operating range which can also be studied using bifurcation diagram. The fixed point on the phase plane, indicating period I operation for normal

32 49 input of 2V, is shown in Figure 2.3. State trajectory in state space indicating period I operation is shown in Figure 2.3. As the voltage is increased the operation changes to period II as indicated by the phase plane plot in Figure 2.32 and the control voltage in Figure Bifurcation diagram with input voltage as the parameter for the PWM converter is shown in Figure In the converter under study, chaos, which is a bounded, aperiodic, apparently random operation (Deane and Hamill 99), sets in at a voltage of about 23V. This is beyond the range at which the converter would normally be operated and hence the converter is chaos free within normal range of operation. il (A) v C (V) Figure 2.3 Phase portrait - Switching map PWM converter

33 5 52.m 5.m vc (V) 5.m 499.m 498.m I L (A) Figure 2.3 State trajectory PWM converter period I operation VC vc(v) I2 i L (A) Figure 2.32 State trajectory in state space PWM converter period II operation

34 5 Vcon Vramp Time (ms) Figure 2.33 Control voltage and ramp during period II operation Figure 2.34 Bifurcation diagram for PWM converter input voltage in V is parameter Stroboscopic map with input voltage at 22.6V in Figure 2.34 shows period-2 operation. The route to chaos is period doubling bifurcation, which is characteristic of voltage mode controlled buck converter (Fossas and Olivar 996). Period doubling in the converter operation occurs at a voltage a little above 2V. The stroboscopic switching map is shown in Figure 2.35 for period II operation V i n ( V ) Strange attractor at 24V is shown in Figure This is the region just after the chaos sets in or just after the enlargement.

35 52 vc(v) i L (A) Figure 2.35 Stroboscopic map for PWM converter, at 22.6V v C ( V ) Figure 2.36 Strange attractor at V in = 24V PWM converter 2.2 PSM DC DC BUCK CONVERTER Figure 2.37 shows the power stage with a PSM controller feedback (Luo Ping et al 26). It consists of a MOSFET switch, a diode, an inductor L, a capacitor C, and a load resistance R. Converter is controlled by the PSM control logic using a clock with a fixed period and duty ratio.

36 53 MOSFET L + Vin - C R PSM CONTROL LOGIC SIG V /V GATE/ INHIBIT f SW REF + Vref - 4kHz Figure 2.37 PSM DC/DC buck converter The clock pulses fed to the converter are at constant frequency and the pulse width is set to be the maximum possible in a basic converter control. The component values are selected for operation at clock frequency. The frequency of operation is generally high enabling reduction in volume and weight. V in can be from a battery or rectified DC from mains that has double the power frequency ripple Circuit Operation While the converter output is less than the reference value, the pulses are applied to the converter switch. When the converter output crosses the reference, to go above the reference the next pulse is skipped. Hence output is maintained at a value close to the reference. Pulse density decreases after the output value goes above the reference or as load decreases and increases when it goes below, or as the load decreases.

37 54 MOSFET switch is ON when the clock pulse is applied over a xed duration of time equal to duty cycle of the clock and the inductor current rises linearly. The switch is OFF for the remaining period of the cycle and the current drops to a lower value. It drops to a value lower than the initial value if the next pulse is skipped and so on. Thus by alternately permitting p pulses and skipping q pulses the output voltage is maintained at a value very close to reference value. The waveforms are shown in Figure The duration pdt is known as charging duration and the duration qdt is known as skipping duration. A cycle consists of (p+q) clock cycles each of duration T where T is the switching period of the clock. il 8 vo (V) & il(a) vo Pulses Applied Pulses skipped Time (s) Figure 2.38 Waveforms of output voltage, inductor current and gate pulses for a PSM converter D is the fixed duty ratio in each cycle and is the maximum duty ratio possible and is less than.

38 55 Gate pulses Q Q D Vo vref clk Figure 2.39 PSM control logic As shown in Figure 2.39(a) comparator compares v and v ref and ts output is given as D input to a D ip op. Q output of D ip op is ANDed with CLK and the AND gate output s applied to the MOSFET switch. On v ref > v comparator output is HIGH and D is HIGH, which will also be the output of the ip op as long as D is high throughout the clock cycle. This makes the output of AND gate to equal the CLK and hence clock cycles are applied to the switch. This duration is known as charging interval or active interval. On v ref < v comparator output is LOW and D ip op output goes LOW at the rising edge of the CLK. This makes Q output of the ip op turn LOW and hence the AND gate output is LOW irrespective of the CLK. The clock pulses are not applied to the switch and are skipped. This duration is known as skipping interval Operating Modes Continuous conduction mode I The converter is said to be working in continuous conduction mode if the inductor current is greater than zero through out the cycle (Kapat et al 28). In each cycle when the switch is ON the inductor current rises and

39 56 when the switch is OFF the current drops to a value equal to or higher than the initial value of the cycle at steady state. The current reaches a maximum value at the end of the charging cycle. During the skipping cycle the pulses are skipped and the current drops to a value higher than zero and the charging cycle starts again. Typical waveforms of a converter working in continuous conduction mode are shown in Figure 2.4. I Charging Skipping V Time (s) Figure 2.4 Inductor current waveform in CCM I Continuous conduction mode II Converter operates in continuous conduction mode with nonzero inductor current except the initial value at the start of each charging cycle (Angkititrakul and Hu 28). In this mode the duration of skipping cycle is long enough for inductor to dry out. The waveform shown in Figure 2.4 has charging duration consisting of p cycles, skipping duration consisting of (q+r) cycles where r is the number of cycles over which the inductor current is zero. Here the inductor current is forced to become discontinuous by prolonging the skipping period.

40 Ind Current in A V Charging Skipping Time (s) Figure 2.4 Inductor current waveform in CCM II Discontinuous conduction mode Under discontinuous conduction mode on application of pulse the inductor current rises during ON time and when the switch is OFF the current reaches zero before the end of the cycle and hence each cycle starts from zero inductor current. The energy stored in the inductor is zero at the end of each switching period. During the skipping period the load resistor discharges the capacitor. Typical Inductor current waveform is shown in Figure The current flows for a duration, which is less than that of a switching cycle. Figure 2.42 also shows a charging pulse and clock cycles. In this case a charging pulse is applied and two pulses are skipped. Inductor current rises during the charging period ON time and during the OFF time it falls to zero before the beginning of the next clock cycle.

41 58 il(a) I2 V Cond time less than switching period Charging Skipping V Time (s) Figure 2.42 Inductor current waveform in DCM When the load resistance is high or the switching frequency f is low, the converter may enter the DCM. Discontinuous conduction mode will result if the load resistance is greater than the critical resistance, which can be calculated from R cr = 2L / D Ts (2.36) For a given load the minimum inductance required for continuous conduction in a switching cycle or L corresponding to mode boundary can be determined from L min = (-D) R/2f (2.37) Critical mode Under critical conduction mode the inductor current starts from zero and rises on application of pulse and ends with zero at the end of each switching cycle. Condition favouring critical mode is the load resistance exactly equalling the critical resistance given by R=R cr = 2fsL/D.

42 59 Figure 2.43 Inductor current waveform in critical mode Critical conduction mode is also known as Boundary Conduction Mode or Border Conduction Mode. It is possible to derive the inductance for a particular load that would result in critical conduction mode by taking the inductor current ripple is twice the average value of the load current. This inductance is known as critical inductance and for continuous conduction for a particular load current the actual circuit inductance must be greater than this. The conversion ratio calculated for continuous conduction is valid only till this operation after which if the load current reduces or the inductance reduces the conversion ratio drastically changes Modeling of Converter under Continuous Conduction Mode Let charging period consists of p cycles and skipping period consists of q cycles for a particular load resistance R and input voltage V in. The duration of charging period is pt and the duration of skipping period is qt. During the charging period, in each cycle the switch is ON for duration equal to DT where D < and during the skipping period the switch is OFF throughout T as the pulses are not applied and skipped. The converter is

43 6 modelled (Ping Luo et al 26) using State Space Averaging (SSA) method and the state space equations, assuming CCM, are obtained as shown below. x A x Bv in for t DT (2.38) y C x (2.39) x A2 x B2v in for DT t T (2.4) y C2 x (2.4) During skipping period x A2 x B2v in for t T (2.42) y C2 x (2.43) where A A A L 2 (2.44) C RC i L x (2.45) v C y v (2.46) B L (2.47)

44 6 B (2.48) 2 C (2.49) Equations (2.38) to (2.4) are valid for p cycles and Equations (2.42) and (2.43) are valid for q cycles. After State Space Averaging, p x Ax BDv in (2.5) p q Defining Modulation Factor M, M f a (2.5) f where f a -Actual frequency of switch and f Switching frequency Then Equation (2.5) becomes x Ax ( M ) DBv in (2.52) Hence the average output voltage is given by v ( M ) o Dv in (2.53) Modulation factor M is proportional to the number of skipping. If v in increases with v and D fixed, M increases. The number of pulses skipped increases to maintain the voltage constant. A similar response is true for increase in load. When load decreases M increases increasing the number of skipping.

45 Simulation of PSM Buck Converter under CCM The average model of the PSM buck converter is simulated using MATLAB/SIMULINK and the schematic using PSIM. A buck DC/DC power stage with the following parameters is considered. Parameter values for power circuit are retained for comparison. Table 2.3 Parameter values considered for simulation S.No Parameter Value Unit L 56 uh 2 C 47 uf 3 5 to 5 Ohms R 5 Ohms Typical 4 Vref 5 V 5 T 25 us 6 vd.4 V 7 r C.25 Ohms The actual topology model is simulated with SIMULINK PSB as in Figure 2.44 with parameters as in Table 2.. A load resistance of 5 Ohm is considered.. Input voltage is fixed at 2V; with reference voltage at 5V and the load current is set to be A. The output voltage is controlled to be constant at 5V when a voltage of 2 V is applied as input. The output voltage and inductor current are as shown in Figure 2.45.

46 63 Continuous powergui input To Workspace i + - Current Measurement g D Mosfet m S psmtest.mat To File i + - Series RLC Branch Current Measurement Diode Series RLC Branch 2 Series RLC Branch + v - Voltage Measurement Scope Scope DC Voltage Source + v - Voltage Measurement Terminator D Latch Q D < 5 Compare To Constant!Q C AND Logical Operator Pulse Generator Figure 2.44 PSM buck converter SIMULINK PSB vo (V) il(i) Figure 2.45 Inductor current for continuous conduction and output voltage. Ripple is observed to be slightly greater than %

47 64 The PSIM simulation results are shown in Figure 2.46 below for the same converter parameters Output Voltag e v in V Inductor Current in A Pulses applied to S witch Time (s) Figure 2.46 PSIM Simulation output showing the ripple in v, Inductor current and pulses applied and skipped. Ripple is slightly above % The state space averaged model is simulated with MATLAB/SIMULINK and the response is shown below in Figure Pulse widths correspond to charging cycle consisting of a number of clock cycles with constant pulse width with duty cycle of 8%. It is possible to note that the width decreases as voltage increases and vice versa indicating the regulating action. Figure 2.47 Average model simulated with input voltage = 2V and D=.8

48 Observations with Variation in Input Voltage/Load For the converter under study the input voltage is changed in step from 2V to 2V at. S. The output voltage settles in around.2ms with higher ripple. The result indicates that the PSM converter has better response to transients. Response to load current and input voltage is shown in Figure Output Voltage v in V 8 [.6, ] 6 4 [.2563, 5.238] 2 step increase in Input Voltage Time (s) (a) 6 V I Time (s) (b) Figure 2.48 Output voltage response to step change in (a) input and (b) load current

49 Bifurcation and Chaos in PSM DC DC Converter Input voltage is fixed at 2 V and the phase plane plot between il, the inductor current and v C, the capacitor voltage is plotted as shown in Figure vc (V) i L (A) Figure 2.49 State trajectory in state space - plot between i L and v C with PSM control for V in =2V The poincar e section as S-Switching map is drawn after the initial transients subside completely and is shown in Figure 2.5. Period I operation in which the ripple frequency equals the switching frequency is not observed in this case, since the average frequency is less than the switching frequency due to pulse skipping. Output voltage ripple is observed to be high, demanding attention.

50 67 vc (mv) il (A) Figure 2.5 Phase Portrait - Stroboscopic map PSM converter for V in =2V Bifurcation diagram with input voltage as the parameter for the PSM converter is shown in Figure 2.5. The plot enlarged over the input voltage range of V to 2V is shown in Figure In the diagram rt regions in the form of windows interleave chaotic regions throughout from the start. The stroboscopic map at an input voltage corresponding to operation within the operating range is shown in Figure The plot includes 6 date points and exhibits rt periodicity with r = 23. vc(v) v in (V) Figure 2.5 Bifurcation diagram for PSM converter

51 68 vc(v) v in (V) Figure 2.52 Bifurcation diagram for PSM converter enlarged over V to 2V range Figure 2.53 Stroboscopic map for PSM converter at V in = 7.6 V For the same converter the voltage is changed in steps of 2V from 2V to 2 to observe the response for onset of chaos if any and the converter responded to be non chaotic as shown in Figure 2.54.

52 Time (s) Figure 2.54 Inductor current in A with change in input voltage in 2V steps from 2V to 2V of input voltage. The Table 2.4 shows the pulses applied and skipped over the range Table 2.4 Pulses applied and skipped over the range of input voltage from 2V to 2V Input Voltage Number of pulses Applied Skipped

53 7 2.3 CONCLUSION A DC to Dc converter is designed and controlled with PWM and PSM controllers under continuous conduction node. The converters are model studied for their performance under varying input voltage and load conditions. It is found that PSM converter that better response, but suffers from higher ripple. The converters are studied for exhibition of bifurcation and chaos. A method to generate stepped input voltage variation is discussed and the bifurcation diagrams and stroboscopic maps are obtained for both the converters with supply voltage as parameter.