Variation in Delays and Power Dissipation in 3-8 line Decoder with Respect to Frequency

Transcription

1 MIT International Journal of Electronics and Communication Engineering, Vol. 5, No. 1, January 2015, pp Variation in Delays and Power Dissipation in 3-8 line Decoder with Respect to Frequency Anshika Sharma Anshikasharma.ece@gmail.com Alok Pandey Alok.pandey.eei@gmail.com Abhinav Vishnoi School of Electronics Engineering Lovely Professional University, Jalandhar, Punjab, India abhinav.15929@lpu.co.in Pankaj Bhardwaj april5pankaj@gmail.com ABSTRACT Discrete quantities of information can be represented in digital systems with binary codes. A binary code of n bits is capable of representing it up to 2n distinct elements of given information. A decoder is a combinational circuit that transforms binary information from n input lines to a maximum of 2n unique output ways. If the n-bit decoded information has unused or don t care combinations, the decoder output will have less than 2n outputs. I. INTRODUCTION The major objective is to design all the necessary components required to form a 3 8 bit Decoder using NOR and NAND logic at 180 nm & 350 nm technologies and comparative analysis for delays and power dissipation variation of the decoders implemented below, with respect to frequency. Most important aspect is to size the basic component of decoder (i.e., transistor) for a particular load. Discrete quantities of information can be represented in digital systems with binary codes. A binary code of n bits is capable of representing it up to 2 n distinct elements of given information. A decoder is a combinational circuit that transforms binary information from n input lines to a maximum of 2 n unique output ways. If the n-bit decoded information has unused or don t care combinations, the decoder output will have less than 2 n outputs. II. NOR LOGIC BASED DESIGNS 3-8 decoders can be implemented by using NAND logic. Designer can calculate the size of the transistor of a NOR gate to drive a particular load. For example Suppose we want to drive a 15 ff load from a 3-8 decoder, so the size of transistor to drive the particular load can be calculated as follows: (a) At 180 nm Technology : Channel Length L = 180 nm = 4.1 nm Cg = * (7/3) = ff Hence we can calculate the size of transistor: Cg = C OX * W L W= Cg T OX / OX L W= µm

2 MIT International Journal of Electronics and Communication Engineering, Vol. 5, No. 1, January 2015, pp (b) At 350nm Technology : Channel Length L = 350 nm = 7.8 nm Cg = * (7/3) = ff Hence we can calculate the size of transistor- Cg = C OX *W L W= Cg T OX / OX L W= µm Table 1: Truth Table of 3-8 Decoder based on NOR logic S. No. INPUTS A B C OUTPUT Y Y Y Y Y Y Y Y8 Waveform (Transient Result): Fig. 2: Output Waveform of 3-8 Decoder based on NOR logic Waveform shown in figure verifies the truth table shown in the table, as When all the inputs are low the output goes low the Y1 When all the inputs are high the output goes high the Y8 Fig. 1: Schematic of 3-8 Decoder based on NOR logic So now the size of transistor for each gate to be used in 3-8 decoders is known, so a 3-8 decoder can now easily implement. Truth table and schematics of 3-8 decoders based on NOR logic is shown in figure: III. NAND LOGIC BASED DESIGNS 3-8 decoder can be implemented by using NAND logic. Designer can calculate the size of the transistor of a NAND gate to drive a particular load. For example Suppose we want to drive a 15 ff load from a 3-8 decoder, so the size of transistor to drive the particular load can be calculated[1][4] as follows[2]: (a) At 180 nm Technology :

3 MIT International Journal of Electronics and Communication Engineering, Vol. 5, No. 1, January 2015, pp Channel Length L = 180 nm = 4.1 nm at the gate Cg = (5/3) = Ff Hence we can calculate the size of transistor [4] W= µm (b) At 350nm Technology : Channel Length L = 350 nm = 7.8 nm Cg = (5/3) = ff Hence we can calculate the size of transistor- W= µm So now the size of transistor for each gate to be used in 3-8 decoder is known, so a 3-8 decoder can now easily implemented. Truth table and schematics of 3-8 decoder based on NAND logic is shown in Fig. 3. Table 2: Truth Table of 3-8 Decoder based on NAND logic INPUTS OUTPUT A B C Y Y Y Y Y Y Y Y8 Fig. 3: Schematic of 3-8 Decoder based on NAND logic Waveform (Transient Result): Fig. 4: Output Waveform of 3-8 Decoder based on NAND logic

4 MIT International Journal of Electronics and Communication Engineering, Vol. 5, No. 1, January 2015, pp Waveform shown in figure verifies the truth table shown in the table, as: When all the inputs are low the output goes low the Y1 When all the inputs are high the output goes high the Y8 IV. FREQUENCY ANALYSIS Frequency analysis gives the power dissipation of the circuit at different frequencies. Power dissipation variation of the decoders implemented above, with respect to frequency is given as follows: (a) NAND based design Power dissipation variation of the 3-8 decoders based on NAND logic implemented above, with respect to frequency is given in the following table. analysis shown in the above table, a designer can make a graph for the readings of a particular technology as follows- (a) At 180 nm Technology Table 3: Frequency Vs Power Dissipation of 3-8 NAND Decoder Type Frequency (MHz.) Nand Logic Power Dissipation (nw) 180 nm 350 nm Fig. 5: Frequency Vs Power Dissipation of 3-8 Decoder At 180 nm Technology (b) At 350 nm Technology Decoder (b) NOR based design Power dissipation variation of the 3-8 decoders based on NOR logic implemented above, with respect to frequency is given in the following table. Table 4: Frequency Vs Power Dissipation of 3-8 NOR Decoder 1. Type Frequency (MHz) Nor Logic Power Dissipation (nw) 180 nm 350 nm Decoder (c) Comparative analysis For comparative analysis of the design implemented using both NAND and NOR logic, a graph can be generated for the readings on a particular technology. To compare the results of frequency Fig. 6: Frequency Vs Power Dissipation of 3-8 Decoder At 350 nm Technology Average Power dissipation is proportional to the frequency, by formula P= CV 2 f. It is clear from the above graph that the power dissipation increases as the frequency increases, but the power dissipation in 3-8 decoder based on NOR logic is very large than the 3-8 decoder based on NAND logic incase of 180nm technology. Similarly at 350nm technology the power dissipation in 3-8 decoder based on NOR logic is very large than the 3-8 decoder based on NAND logic, in 350 nm technology the power dissipation increases with the frequency.

5 MIT International Journal of Electronics and Communication Engineering, Vol. 5, No. 1, January 2015, pp V. CONCLUSION In this Paper 3-8 decoder designed by using NAND and NOR logic. These implementations are designed on two technologies TSMC 180 nm and 350 nm. Comparative results are taken out by doing frequency and delay analysis. Power dissipation variations with respect to frequency is calculated for the decoders implemented using both NAND and NOR logic. It is very much clear from the results for the power dissipation and delay for both the logics that NAND logic based decoders are much useful than the NOR logic based decoders because of less power dissipation and fast switching. NOR based decoders are having more power dissipation and slow switching in comparison with NAND based decoders. REFERENCES 1. Ivan E. Sutherland, BOB F. Sproul and David L. Harris, Logical Effort: Designing fast CMOS Circuits, Morgan Kaufmann Publishers, Rabey, Digital Integrated Circuits Design, Pearson Education Second edition Michael A. Turi and José G. Delgado-Frias, Reducing Power in Memory Decode by means of Selective Precharge Schemes, IEEE Journal, dated 9/07/ Kang &Leblebigi, CMOS Digital IC Circuit Design and Analysis, McGraw Hill Bharadwaj, S. Amrutur and Mark A., Horowitz, Fast Low-Power Decoders for RAMs, IEEE Journal of Solid-State Circuits, Volume 36, Issue 10 in Oct