AnadigmFilter1 Evaluation Board Quick Start User Guide

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Theodore Green
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1 AnadigmFilter Evaluation board Quick start Guide AnadigmFilter Evaluation Board Quick Start User Guide PLEASE read all of this minimal document before starting. It may save you a lot of time. Figure below shows a photo of the AnadigmFilter Evaluation Board. Figure.

2 Quick start instructions: AnadigmFilter Evaluation board Quick start Guide. Power up the board by connecting it to a +.V power supply.. Connect a ground referenced differential signal to INA+ and INA-. If the signal is single-ended, connect it to INA+ and connect INA- to ground.. Set configuration bits C and C high. This will enable input port A and set the gain to 0dB (x).. Monitor the differential output on OUT+ and OUT-. The output signal will be filtered by a lowpass Butterworth filter with corner frequency 00kHz. See below for details of how to calculate corner frequency for different configuration settings and different master clock frequencies. To calculate the corner or center frequency of any filter use the following equation CORNER FREQUENCY = ( F(aclk) / Divisor_B ) * Divisor_A * Divisor_C F(aclk) is the external clock frequency applied to the ANE0 device ACLK pin. Divisor A, B and C, see table below. AnadigmFilter (lower 8 bits of the 6 Bit Configuration Word) Divisor_B Internal Clock divider settings, (divider to scale Fc in octave steps) Divisor_A Filter Fc settings (9% steps across octave) Divisor_C Filter topology max Fc factor B B B B A A A C6 C5 C C C C C0 Pin Pin Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 B,B,B,B DivisorB A,A,A DivisorA low pass High Pass Bandpass Bandstop The board comes with an 8MHz oscillator module. This can be replaced by another or disabled and an external clock applied to the CLK IN pin. The oscillator module can be disabled by applying a jumper or short to J. Note: stopping the external clock makes the filter go into deep sleep mode (~0uW) regardless of control word setting. 6. The filter clock is output on pin CLK OUT. The filter clock is the master clock divided by Divisor_B. 7. Set C low and C high. The input signal can now be applied to input port B. If both C and C are high then signals on both port A and port B will be summed. 8. Configuration bits C 5 allow adjustment of the gain from 0dB to 8dB in db steps. 9. If jumpers are applied to J and J then the output capacitors will be shorted. This means that the differential output signal will have a common mode voltage level of +.5V. 0. See the table called AnadigmFilter Control Interface later in this document for details on how to set the different filter types and the limiting frequency for each type.. The input stages (see fig and also schematic) consist of through hole capacitors (C0-7) and resistors (R9-6) combined with the input opamp of the dpasp. This input stage can be configured by the user to provide fixed filtering, gain and voltage step-up. The dpasp uses +.5V centered signals but the input stages allow the user to drive the board with ground referenced signals. The through-hole resistors provided are ohm and give a gain of x. Note that the dpasp cannot be driven by a signal whose differential amplitude is greater than +/-V (because signals on its pins IxP & IxN must be between 0 and +V) so if the signal to the board is greater than +/-V then the input stage should be configured to give a gain of < x (e.g. i/p +/-6V, make gain x0.5). The capacitors are not populated but can be added by the user to provide the desired (fixed) filtering on the input stage e.g. adding feedback caps to C, or C6,7 will make a lowpass input filter (formula for Rs & Cs is standard).

3 AnadigmFilter Evaluation board Quick start Guide Figure, Pictorial Pin description Figure, Block Diagram

4 AnadigmFilter Evaluation board Quick start Guide FPAA Power Pin Decoupling C5 n INA- INA+ P INB+ INB- P5 R R C n C0 n R0 R9 C n C C06 u Power PIC Program Interface P pin 0 pin 5 pin 6 C C5 C6 C7 C8 C9 0n 00n 0n 00n 0n 00n C7 n R5 R6 C6 n C n R R C n P6 P7 OUTCLK OUT- OUT+ P6 J 00n C8 00n C9 J IN ON OP IO5P IO5N IO6P IO6N IO7P IO7N OP ON IP IN ON OP AVSS OP ON IN IP A IP U Apex_sm_v QFP RESETb SO MEMCLK ACTIVATE ERRb 0 LCCb 9 SI 8 DVSS 7 D 6 MODE 5 ACLK R7 R8 C0 00n U PIC6F689_FM DIL VSS 0 C5 C0 9 C C 8 C C 7 5 C C 6 6 C C 5 7 C0 C5 8 CLK C6 9 DAT C7 0 C9 C8 SCLK CSb CSb CFGFLGb 0 BVSS 9 VREFN 8 VMR 7 VREFP 6 B 5 IP IN C 00n P CSb R7 C 00n X J Vdd En Out Vss X J Vdd En Out Vss C 00p P ACLK P0 R R P 6way dip switch R R R5 R6 R7 R8 R9 R0 R R R R R5 R6 E D C B A Drn Drn Drn Drn Project Drawn Check Projection Do Not Scale Client Anadigm FilterMaster Board v.0 Chk Chk Chk Chk Title Filename Drawing No. Sheet Dave Lovell Oct nd 009 of OTL A

5 AnadigmFilter Evaluation board Quick start Guide Gain Settings Analog Input Pin settings ANADIGM AnadigmFilter Control Interface (6 Bit Configuration Word) Filter Topology Filter approximation DivisorB Internal Clock divider settings, (divider to scale Fc in octave steps) DivisorA Filter Fc settings (9% steps across octave) LSB MSB G G G I I T T T T B B B B A A A C5 C C C C C0 C9 C8 C7 C6 C5 C C C C C0 Pin Pin Pin Pin 5 Pin 6 Pin 7 Pin 0 Pin Pin Pin Pin Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 G,G,G Gain (dbs) I,I Active input(s) T,T Filter topology B,B,B,B DivisorB A,A,A DivisorA infinity (Mute) None Input A 00 0 Lowpass Highpass The Filter Approximation applied depends Input B 0 Bandpass upon the Filter topology selected A & B Bandstop Note See Table insert to the lower left Filter Approximation Applied T,T T,T Commen Width Limits (FCLK = ACLK / DivisorB) Lowpass Butterworth n/a Max Fc = FCLK(max) = 8MHz Lowpass Chebyshev 00 0 n/a Max Fc = FCLK(max) = 0MHz Lowpass Bessel 00 0 n/a Max Fc = FCLK(max) = 5MHz Lowpass Bypass 00 n/a Max Fc = FCLK(max) = 0MHz Highpass Butterworth 0 00 n/a Max Fc = FCLK(max) = 6MHz Highpass Chebyshev 0 0 n/a Max Fc = FCLK(max) = 0MHz Highpass Bessel 0 0 n/a Max Fc = FCLK(max) = 5MHz Highpass Bypass 0 n/a Max Fc = FCLK(max) = 0MHz Bandpass Inverse Chebyshev 0 00 narrow 0% Max Fc = FCLK(max) = 0MHz Bandpass Bessel 0 0 narrow 0% Max Fc = FCLK(max) = MHz Bandpass Inverse Chebyshev 0 0 wider 0% Max Fc = FCLK(max) = 0MHz Bandpass Bessel 0 wider 0% Max Fc = FCLK(max) = MHz Bandstop Inverse Chebyshev 00 narrow 0% Max Fc = FCLK(max) = MHz Bandstop Bessel 0 narrow 0% Max Fc = FCLK(max) = MHz Bandstop Inverse Chebyshev 0 wider 80% Max Fc = FCLK(max) = MHz Bandstop Bessel wider 80% Max Fc = FCLK(max) = MHz Notes ) If inputs A and B are selected then the two active input signals will be summed. ) Setting of five 0 s for the control bits C[5:] (zero gain and no inputs selected) makes AnadigmFilter go into standby (approx 0mW). Stopping the external clock makes dpasp go into deep sleep (< 0uW). ) Max Fc, or maximum Filter Corner or Center Frequency limits have been determined for better than % accurate filter parameters, exceeding these limits will result in loss of filter accuracy. ) Bypass filter approximation provides a flat response from d.c. to FCLK * 0.. (FCLK = ACLK / Divisor_B ). Divisor_A inputs have no effect in this mode, gain and input select still apply. 5) Divisor_A step size is mathematically equal to (8thsqrt() or (()^^(/8). 6) FCLK (= ACLK / DivisorB) is provided on an output pin from the ANE0, the primary purpose of this signal is to enable synchronization of any subsequent ADC 5

RangeMaster2 Datasheet. Programmable Analog Signal Processor for a Universal RFID tag reader system

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