Figure 2a (b) Compare series diode clipper and shunt diode clipper. [8+8]

Transcription

1 Code No: 07A30401 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Explain the response of RC low pass circuit for exponestial input signal (b) Derive the expression for percentage till for a square wave output of Rc high pass circuit. [8+8] 2. (a) Design a diode clamper to restore a d.c level of +3 Volts to an input sinusoidal signal of peak value 10Volts. Assume drop across diode is 0.6 volts as shown in the figure 2a. Figure 2a (b) Compare series diode clipper and shunt diode clipper. [8+8] 3. (a) Explain the phenomenon of latching in a transistor (b) Define the following for a transistor switch i. Rise time ii. Fall time iii. Storage time iv. Delay time. [8+8] 4. (a) Explain different triggering methods of binary circuits. (b) A collector coupled Fixed bias binary uses NPN transistors with h FE = 100. The circuit parameters are V CC = 12v, V BB = -3v, R C = 1k Ω, R 1 = 5k Ω, and R 2 = 10 k Ω. Verify that when one transistor is cut-off the other is in saturation. Find the stable state currents and voltages for the circuit. Assume for transistors V CE(sat) = 0.3V and V BE(sat) = 0.7V. [8+8] 5. (a) In a current sweep circuit, explain how linearity correction is made through adjustment of driving waveform. (b) Write the basic mechanism of transistor television sweep circuit. [16] 6. (a) What is the condition to be met for pulse synchronization? 1 of 2

2 Code No: 07A30401 Set No. 1 (b) Describe synchronization with 2:1 frequency division with neat waveforms. (c) Define the terms phase delay and phase jitter. [4+8+4] 7. (a) What is a sampling gate. (b) Illustrate the principle of sampling gates with series and parallel switches and compare them. (c) Draw the circuit diagram of unidirectional diode gate and explain its operation. [16] 8. (a) Draw the circuit diagram of diode - resistor logic AND gate and explain its operation. (b) Design a transistor inverter circuit (NOT gate) with the following specifications. V CC = V BB = 10V, i csat = 10mA; h femin = 30; the input is varying between 0 and 10V. Assume typical junction voltages of npn silicon transistor. [16] 2 of 2

3 Code No: 07A30401 Set No. 2 II B.Tech I Semester Regular Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) A symmetrical square wave whose peak-to-peak amptitude id 2V and whose average value is zero as applied to on Rc integrating circuit. The time constant is equals to half -period of th esquare wave find the peak to peak value of the output amplitude (b) Describe the relationship between rise time and RCtime constant of a low pass RC circuit. [8+8] 2. (a) Determine V o for the network shown in fugure 2a for the given waveform.assume ideal diodes. Figure 2a (b) Explain negative peak clipper with and without reference voltage. [8+8] 3. (a) For a common emitter circuit V cc = 10V, RC = 1kΩ I B =0.2A. Determine i. The valve of h FE (min) for saturation to occor ii. If R c is changed to 220Ω, will the transistor be saturated (b) Explain the phenomenon of latching in a transistor. [8+8] 4. Draw the circuit diagram for Schmitt trigger and explain its operation. What are the applications of the above circuit? Derive the expressions for UTP and LTP. [16] 5. Explain the basic principal of Miller and Bootstrap time base generators and also derive the equations for sweep speed error. [16] 6. (a) With the help of a circuit diagram and waveforms explain frequency division of an a stable multivibrator with pulse signals. 1 of 2

4 Code No: 07A30401 Set No. 2 (b) Explain with the help of block diagram and waveforms for acheiving division of relaxation devices without phase jitter. [8+8] 7. (a) Distinguish between sampling gates and logic gates? (b) Explain the operation of a chopper amplifier with neat block diagram and waveforms. (c) Distinguish between unidirectional and bidirectional gates. [4+8+4] 8. (a) Draw the circuit diagram of diode-transistor logic NOR gate and explain its operation. (b) Draw the output waveform X for the given inputs figure 8b Figure 8b 2 of 2

5 Code No: 07A30401 Set No. 3 II B.Tech I Semester Regular Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Explain about RLC Ringing Circuit (b) Explain RC double differentiator circuit. [8+8] 2. (a) T=1000 µ sec V= 10 V Duty cycle = 0.2 i. Sketch waveform with voltage levels at steady state figure 2(a)iii ii. Forward and reverse direction tilt iii. A f / A r Figure 2(a)iii (b) Write a short note on non- linear wave shaping. [12+4] 3. Explain the following (a) Storage and transition times of the diode as a switch (b) Switching times of the transistor. [8+8] 4. What is a monostable multivibrator? Explain with the help of a neat circuit diagram the principle of operation of a monostable multivibrator, and derive an expression for pulse width. Draw the wave forms at collector and Bases of both transistors. [16] 5. (a) Define sweep time and restoration time of a voltage time base waveform. What is the difference between sweep and sawtooth waveforms? (b) In the transistor bootstrap circuit, V cc = 25V, V EE = 15V, R = 10kΩ, R E = 15kΩ, R B = 150 kω, C= 0.05 µf, C 1 = 100 µf. The gating waveform has a duration T G =300 µsec. The transistor parameters are h ie = 1.1 kω, h re = kω, h fe = 50, h oe = 1/40 1 of 2

6 Code No: 07A30401 Set No. 3 i. Draw the waveforms of i c, and v o, labeling all current and voltage levels. ii. What is the slope error of the sweep? iii. What is the sweep speed and the maximum value of the sweep voltage? iv. What is the retrace time T r for C to discharge completely? v. Calculate the recovery time T 1 for C 1 to recharge completely. [16] 6. (a) With the help of a circuit diagram and waveforms, explain frequency division of an astable multivibrator with pulse signals. (b) The relaxation oscillator, when running freely, generates an output signal of peak - to - peak amplitude 100V and frequency 1 khz. Synchronizing pulses are applied of such amplitude that at each pulse the breakdown voltage is lowered by 20V. Over what frequency range may the sync pulse frequency be varied if 1 : 1 synchronization is to result? If 5 : 1 synchronization is to be obtained (f P /f S = 5), over what range of frequency may the pulse source be varied? [16] 7. (a) Explain the operation of a six - diode gate. (b) Write the applications of sampling gates. (c) Briefly describe the chopper amplifier and sampling scope. [16] 8. (a) Compare the Resistor Transistor logic and Diode Transistor logic families (b) Explain the wired AND logic with the help of circuit diagram. [8+8] 2 of 2

7 Code No: 07A30401 Set No. 4 II B.Tech I Semester Regular Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering and Electronics & Instrumentation Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Obtain the response of RC high pass cirucit for an exponential i/p lignal (b) A square wave whose peak-to-peak valve is IV, exterds I 0.5V w.r.t. to ground. The half period is O.iSec this voltage impressed upon an RC differentating circuit whose time constant is 0.2 sec. Determine the maximum and minimum valves of the l/p voltages int eh steady state. [8+8] 2. (a) The input voltage v i to the two level clipper shown in figure 2a varies linearly from 0 to 75 V. Sketch the output voltage v o to the same time scale as the input voltage. Assume Ideal diodes. Figure 2a (b) Explain positive peak voltage limiters below reference level. [12+4] 3. (a) Explain with relevant diagram the various transistor switching times (b) Explain the storage and transition times of the diode as a switch. [8+8] 4. Explain about various switching conditions of Schmitt trigger. [16] 5. (a) What are the methods of generating a time base waveform? Explain each method. (b) Derive the expression Mathematical relationship between sweep speed error, Displacement error and transmission error for an exponential sweep circuit. [16] 6. (a) Describe frequency division employing a transistor a stable multivibrator with waveforms. (b) Describe frequency division employing a transistor monostable multivibrator with waveforms. [8+8] 1 of 2

8 Code No: 07A30401 Set No (a) Describe the working of a four diode gate with necessary diagrams and equations. (b) For the four diode gate, R L = R C = 100k Ω and that R 2 = 2kΩ, R F = 50Ω. For V s = 25V, compute gain A, V min and (V c ) min. Compute (V n ) min for V = V min. [16] 8. (a) Define positive and negative logic system (b) Define fan-in, fan-out (c) Draw and explain the circuit diagram of a diode OR gate for positive logic. [4+4+8] 2 of 2

9 Code No: RR Set No. 1 II B.Tech II Semester Supplimentary Examinations, Apr/May 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) The periodic wave form shown is applied to an RC integrating circuit whose time constant is 10 µ sec. Sketch the output. (figure 1b) [8] (b) Calculate the maximum and minimum values of output voltage with respect to ground. [8] Figure 1b 2. (a) Give the circuits of series clipper circuits and explain their operation with the help of transfer characteristics. [8] (b) For the circuit shown in the figure 2b : sketch the input and output waveforms if R = 1 KΩ [8] V R = 10 V, V i = 20 Sin ωt R f = 100 Ω R r = V γ = 0 Figure 2b 3. (a) Explain the behavior of a BJT as a switch. Give Applications. [8] (b) Write a short note on switching times of a transistor. [8] 4. (a) Explain how a Schmitt trigger can be used as a comparator and as a squaring circuit. [8] (b) What do you understand by hysterisis? What is hysterisis voltage? Explain how hystersis can be eliminated in a Schmitt trigger. [8] 1 of 2

10 Code No: RR Set No (a) Distinguish between voltage and current time base generators. [6] (b) In the current-sweep circuit, how linearity can be corrected through adjustment of driving waveform. Illustrate with an example. [10] 6. (a) Bring out the importance of synchronization and frequency division. [8] (b) The relaxation oscillator when running freely, generates an output sweep amplitude of 100V and frequency 1kHz. Synchronizing pulses are applied such that at each pulse the breakdown voltage is lowered by 20V. Over what frequency range may the synchronizing pulse frequency be varied if 1:1 synchronization is to result? [8] 7. (a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for multiple inputs. [8] (b) Explain with circuit diagram the operation of a two input sampling gate which does not have any loading effect on control signal. [8] 8. What is meant by blocking oscillator? Explain the principle of operation of monostable blocking oscillator with base timing. Sketch the current waveforms and derive an expression for current pulse width. [16] 2 of 2

11 Code No: RR Set No. 2 II B.Tech II Semester Supplimentary Examinations, Apr/May 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) The periodic ramp voltage shown is applied to a low pass RC circuit. Find the equations from which to determine the steady state output waveform (figure1a). [8] Figure 1a (b) If T 1 =T 2 =RC, find the maximum and minimum value of the output voltage and plot this waveform. [8] 2. (a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer characteristic. [6] (b) For the circuit shown in figure 2b: If R = 1KΩ, V R2 = 10V, V R1 = 7 V R f = 0 and R r = Figure 2b i. Sketch the transfer characteristic ii. If V i = 20 sin ωt sketch the input and output waveforms. [10] 3. (a) Explain how transistor can be used as a switch in the circuit, under what condition a transistor is said to be OFF and ON respectively. [6] (b) A germanium transistor is operated at room temperature in the CE configuration. The supply voltage is 6 V, the collector-circuit resistance is 200 Ω and the base current is 20 percent higher than the minimum value required to drive the transistor into saturation. Assume the following transistor parameters: 1 of 2

12 Code No: RR Set No. 2 I co =-5µA, I EO =-2µA, h FE =100, and r bb =250 Ω. Find V BE (Sat) and V CE (Sat). [10] 4. A Self-bised binary uses n-p-n silicon transistors having values of Vce(sat)=0.4v,Vbe(sat)=0.8 v and zero base to emitter voltage for cutoff. The circuit parameters are Vcc=20v, Rc=4.7kΩ, R 1 =30kΩ, R 2 =15kΩ and R e =390Ω. (a) Find the stable-state currents and voltages. [10] (b) Find the minimum value of h fe required to give the values in part(a) [2] (c) As the temperature is increased, what is the maximum value to which I CBO can increase before the condition is reached where neither transistor is OFF? [4] 5. (a) With a neat diagram explain the operation of a transistor TV sweep circuit. [8] (b) In the TV current sweep circuit L= 5mH and total current change required to sweep the beam across the screen is 100mA. Of the 63.5 microsec available for a horizontal sweep and retrace combined, 7.0 microsec is to be used for retrace. Calculate i. required supply voltage ii. the capacitance C and iii. the maximum voltage that appears across the transistor. [8] 6. (a) Explain how a sinusoidal oscillator can be used as a frequency divider. [8] (b) Write short notes on i. Phase delay and ii. Phase jitters [8] 7. Explain the operation of bi-directional sampling gate using diodes. Give the equivalent circuit and derive the expression for gain. Derive the expressions for minimum control voltages required. [16] 8. Explain the recovery and loading considerations in blocking oscillator and the effect of providing damping. Give an alternate circuit to have pulse period independent of RL. [16] 2 of 2

13 Code No: RR Set No. 3 II B.Tech II Semester Supplimentary Examinations, Apr/May 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) A symmetrical square wave whose peak-to-peak amplitude is 2V and whose average value is zero is applied to an RC integrating circuit. The time constant is half the period of the square wave. Find the peak-to-peak value of the output amplitude. [10] (b) Write a short note on RC low pass circuit. Draw the output if a step input is applied. [6] 2. (a) For the circuit shown in figure, sketch transfer characteristics, assume ideal diodes. (figure2a) [10] Figure 2a (b) Draw the basic circuit diagram of a DC restorer circuit and explain its operation. [6] 3. (a) Describe the switching times of BJT by considering the charge distribution across the base region. Explain this for cut off, active and saturation regions. [8] (b) Define the following terms: i. storage time ii. delay time iii. rise time iv. fall time. [8] 4. Describe multivibrators from the viewpoints of construction, priniciple of working, classification based on the output states, applications and specifications. Mention one specific application of each. [16] 5. (a) Distinguish between voltage and current time base generators. [6] 1 of 2

14 Code No: RR Set No. 3 (b) In the current-sweep circuit, how linearity can be corrected through adjustment of driving waveform. Illustrate with an example. [10] 6. (a) Bring out the importance of synchronization and frequency division. [8] (b) The relaxation oscillator when running freely, generates an output sweep amplitude of 100V and frequency 1kHz. Synchronizing pulses are applied such that at each pulse the breakdown voltage is lowered by 20V. Over what frequency range may the synchronizing pulse frequency be varied if 1:1 synchronization is to result? [8] 7. (a) What is a sampling gate? Explain the operation of series gate using JFET. Sketch the input and output waveforms. [8] (b) Illustrate the errors encountered in series sampling and what is the design procedure to minimize these errors? [8] 8. Explain the recovery and loading considerations in blocking oscillator and the effect of providing damping. Give an alternate circuit to have pulse period independent of RL. [16] 2 of 2

15 Code No: RR Set No. 4 II B.Tech II Semester Supplimentary Examinations, Apr/May 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Compute and draw to scale the output wave form for C=50pF, C=75pF, and C=25 pf if the input is a 20V step for the following circuit.(figure 1). [16] Figure 1 2. (a) Design a clipping circuit with ideal components, which can give the waveform shown in figure 2a for a sinusoidal input. [8] Figure 2a (b) Design a diode clamper to restore a d.c level of +3 Volts to an input signal of peak to peak value of 10 Volts. Assume drop across diode is 0.6 Volts. as shown in the figure (figure 2b)below [8] Figure 2b 1 of 2

16 Code No: RR Set No (a) Explain the phenomenon of latching in a transistor switch. [6] (b) A transistor has f T = 50 MHz, h FE =40, C b c=3pf and operates with V cc =12 V and R c =500 Ω. The transistor is operating initially in the neighbourhood of the cut-in point. What base current must be applied to drive the transistor to saturation in 1µ sec? [10] 4. (a) Discuss the different methods of triggering a flip-flop. Explain the role of commutating capacitors in a binary circuit. [10] (b) Draw the circuit diagram of a fixed bias binary with speed up capacitors. [6] 5. (a) Bring out the necessity and importance of Time base circuits. [6] (b) In the UJT sweep circuit, V BB = 20V, V yy = 50V, R=5k, C=0.01 micro F. UJT has η= 0.5. Calculate i. amplitude of sweep signal ii. Slope and displacement errors and iii. estimated recovery time. [10] 6. (a) Explain how a sinusoidal oscillator can be used as a frequency divider. [8] (b) Write short notes on i. Phase delay and ii. Phase jitters [8] 7. (a) Explain the operation of unidirectional diode sampling gate with neat sketch of waveforms. Illustrate the effect of different levels of control voltage on gate output. [10] (b) Discuss the advantages and disadvantages. [6] 8. What is meant by blocking oscillator? Explain the principle of operation of monostable blocking oscillator with base timing. Sketch the current waveforms and derive an expression for current pulse width. [16] 2 of 2

17 Code No: RR Set No. 1 II B.Tech II Semester Supplementary Examinations, Aug/Sep 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. A symmetrical square wave whose average value is zero has a peak-to-peak amplitude of 20 V and a period of 2 µsec. This waveform is applied to a low pass circuit whose upper 3dB frequency is 1/2 π MHz. Calculate and sketch the steady state output waveform. What is the peak-to-peak output amplitude. [16] 2. (a) For the circuit shown in figure 2a an input voltage V i linearly varies from 0 to 150V is applied. Sketch the output waveform V 0 to the same time scale. Assume ideal diodes. [10] Figure 2a (b) State and prove clamping circuit theorem. [6] 3. (a) Describe the switching times of BJT by considering the charge distribution across the base region. Explain this for cut off, active and saturation regions. [8] (b) Define the following terms: i. storage time ii. delay time iii. rise time iv. fall time. [8] 4. (a) Discuss the symmetrical and Asymmetrical triggering in case of Bistable transistor multivibrator. [8] 1 of 3

18 Code No: RR Set No. 1 (b) For the given circuit,find UTP & LTP. What is this circuit called? Data given h fe (min)=40, V CE (sat)=0.1 V, U BE (sat)=0.7 V V r =0.5V, V BE (active)=0.6v. [8](figure 4b) Figure 4b 5. (a) If the amplifier gain is different from unity in a bootstrap circuit, what is the effect on the sweep voltage? What is the effect of amplifier bandwidth on the sweep output? [8] (b) With a neat circuit, explain a method of compensation used to improve the linearity of a bootstrap time base circuit. [8] 6. (a) Explain the principle of synchronization and synchronization with frequency division. [8] (b) Explain the method of pulse synchronization of relaxation devices, with examples. [8] 7. Explain the operation of bi-directional sampling gate using diodes. Give the equivalent circuit and derive the expression for gain. Derive the expressions for minimum control voltages required. [16] 8. Consider the triggered blocking oscillator circuit shown in figure 8 below., using a silicon transistor with V CE (sat) = 0.3V and V BE (sat) = 0.7V and h FE = 50. There are twice as many turns in the base winding as in the collector winding. The magnetizing inductance of the collector winding 3 mh, its leakage inductance is 50 µh and its shunt capacitance is 100 pf. During the pulse, calculate (a) the pulse amplitude at the collector [4] (b) the collector current [4] (c) the base current and [4] (d) the pulse width. [4] 2 of 3

19 Code No: RR Set No. 1 Figure 8 3 of 3

20 Code No: RR Set No. 2 II B.Tech II Semester Supplementary Examinations, Aug/Sep 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Draw the different output waveforms of a RC High Pass circuit when it is applied with different inputs like (a) Step-voltage input, [5] (b) pulse input [5] (c) square wave input. [6] Explain the same. 2. (a) Give the circuits of different types of shunt clippers and explain their operation with the help of their transfer characteristics. [8] (b) For the circuit shown in figure 2b: Sketch the input and output waveforms.[8] Figure 2b V R = 10V, V i = 20 Sin ωt R f = 100Ω R r = 10K, V γ = 0 and R= 1K, 3. (a) Describe the switching times of BJT by considering the charge distribution across the base region. Explain this for cut off, active and saturation regions. [8] (b) Define the following terms: i. storage time ii. delay time iii. rise time iv. fall time. [8] 4. With the help of a neat circuit diagram, explain the operation of an emitter-coupled monostable multi and derive an expression for the pulse width of the output [16] 1 of 2

21 Code No: RR Set No (a) Draw a neat circuit diagram of UJT relaxation oscillator and explain its operation. Can it be used as time-base circuit of a CRO? If so how and if not why? [8] (b) Draw a Miller time-base circuit with n-p-n transistors and explain its operation. Compare its performance with that of UJT relaxation oscillator. [8] 6. (a) Illustrate the terms synchronization and frequency division of a sweep generator. [8] (b) A free-running relaxation oscillator has sweep amplitude of 100 V and a period of 1 msec synchronizing pulses are applied to the device such that breakdown voltage is lowered by 50 V at each pulse. The synchronizing pulse frequency is 4 khz. What is the amplitude and frequency of synchronized oscillator waveform? [8] 7. Explain the operation of bi-directional sampling gate using diodes. Give the equivalent circuit and derive the expression for gain. Derive the expressions for minimum control voltages required. [16] 8. (a) Compare the diode controlled and RC controlled astable operated blocking oscillator. [6] (b) What are the advantages of RC controlled oscillator? [4] (c) List the applications of blocking oscillators. [6] 2 of 2

22 Code No: RR Set No. 3 II B.Tech II Semester Supplementary Examinations, Aug/Sep 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Verify V 1 = V 1+ e T/2RC V 1 = V 1+e T/ 2RC (figure1a) Figure 1a For a symmetrical square wave applied to a high pass RC circuit. [10] (b) Draw the RC high pass circuit and explain its working with step voltage input. [6] 2. (a) Design a clipping circuit with ideal components, which can give the waveform shown in figure 2a for a sinusoidal input. [8] Figure 2a (b) Design a diode clamper to restore a d.c level of +3 Volts to an input signal of peak to peak value of 10 Volts. Assume drop across diode is 0.6 Volts. as shown in the figure (figure 2b)below [8] 1 of 2 Figure 2b

23 Code No: RR Set No (a) Describe the switching times of BJT by considering the charge distribution across the base region. Explain this for cut off, active and saturation regions. [8] (b) Define the following terms: i. storage time ii. delay time iii. rise time iv. fall time. [8] 4. What is a monostable multivibrator? with the help of a neat circuit diagram explain the principle of operation of a monostable multi and derive an expression for pulse width. [16] 5. (a) Write important applications of time-base circuits. With reference to time base circuits define the following terms: [8] i. Flyback time ii. Transmission error. (b) What is meant by triggered sweep? What are the merits and demerits of triggered sweep circuits. [8] 6. (a) Explain the principle of synchronization and synchronization with frequency division. [8] (b) Explain the method of pulse synchronization of relaxation devices, with examples. [8] 7. (a) Explain how the diodes in a four-diode gate are replaced by short circuits.[8] (b) Calculate the control voltage for a four-diode gate. [8] 8. What is meant by blocking oscillator? Explain the principle of operation of monostable blocking oscillator with base timing. Sketch the current waveforms and derive an expression for current pulse width. [16] 2 of 2

24 Code No: RR Set No. 4 II B.Tech II Semester Supplementary Examinations, Aug/Sep 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electronics & Instrumentation Engineering, Bio-Medical Engineering and Electronics & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. A square wave whose peak-to-peak amplitude is 2V extends±1v with respect to ground. The duration of the positive section is 0.1 Sec and that of the negative section is 0.2 Sec. If this waveform is impressed upon an RC integrating circuit whose time constant is 0.2 sec. What are the steady state maximum and minimum values of the output waveform? [16] 2. (a) For the circuit shown in figure, sketch transfer characteristics, assume ideal diodes. (figure2a) [10] Figure 2a (b) Draw the basic circuit diagram of a DC restorer circuit and explain its operation. [6] 3. (a) Describe the switching times of BJT by considering the charge distribution across the base region. Explain this for cut off, active and saturation regions. [8] (b) Define the following terms: i. storage time ii. delay time iii. rise time iv. fall time. [8] 4. (a) Discuss about triggering of monostable multivibrators.does a monostable multivibrator need symmetrical triggering? explain. [8] (b) Explain how to use a monostable multi as voltage to time converter derive the expression for T in terms of V CC & V? [8] 1 of 2

25 Code No: RR Set No (a) Explain the principle of working of Miller sweep circuit. Derive the expression for sweep speed by taking Miller integrator circuit. [8] (b) Draw a simple single stage transistor Miller integration circuit and explain how it behaves as a time-base circuit. [8] 6. (a) Illustrate the terms synchronization and frequency division of a sweep generator. [8] (b) A free-running relaxation oscillator has sweep amplitude of 100 V and a period of 1 msec synchronizing pulses are applied to the device such that breakdown voltage is lowered by 50 V at each pulse. The synchronizing pulse frequency is 4 khz. What is the amplitude and frequency of synchronized oscillator waveform? [8] 7. (a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for multiple inputs. [8] (b) Explain with circuit diagram the operation of a two input sampling gate which does not have any loading effect on control signal. [8] 8. Explain the operation of an RC controlled free running blocking oscillator with neat sketch of circuit and voltage waveforms. Derive the expression for duty cycle. What are the advantages of the circuit? [16] 2 of 2

26 Code No: NR NR II B.Tech I Semester Supplementary Examinations, November 2006 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Telematics and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. The square wave shown in figure1 is fed to an RC coupling network. What are the voltage waveforms across R and across C if (a) RC is very large, say RC = 10T [8] (b) RC is very small, say RC=T/10? [8] Figure 1 2. (a) Give the circuits of different types of shunt clippers and explain their operation with the help of their transfer characteristics. [8] (b) For the circuit shown in figure 2b below: Sketch the input and output waveforms. [8] Figure 2b V R = 10V, V i = 20 Sin ωt R f = 100Ω R r = 10K, V γ = 0 and R= 1K, 3. (a) Explain the behavior of a BJT as a switch. Give Applications. [8] (b) Write a short note on switching times of a transistor. [8] 1 of 2

27 Code No: NR NR 4. A collector-coupled monostable multi using silicon n-p-n transistors has the Following parameters: V cc =12v,V BB =3v, R c1 =R c2 =1.8kΩ,R 1 =R 2 =18KΩ,h fe =25,rbb =400 and C=1200pf. Neglect I CBO.Use V CE (sat)=0.2v, V BE (sat)=0.7v and Vr=0.6V. (a) Calculate and plot the waveforms at each base and collector. [12] (b) Find the overshoot. [2] (c) Find the output pulse width. [2] 5. (a) Bring out the necessity and importance of Time base circuits. [6] (b) In the UJT sweep circuit, V BB = 20V, V yy = 50V, R=5k, C=0.01 micro F. UJT has η= 0.5. Calculate i. amplitude of sweep signal ii. Slope and displacement errors and iii. estimated recovery time. [10] 6. (a) Illustrate the terms synchronization and frequency division of a sweep generator. [8] (b) A free-running relaxation oscillator has sweep amplitude of 100 V and a period of 1 msec synchronizing pulses are applied to the device such that breakdown voltage is lowered by 50 V at each pulse. The synchronizing pulse frequency is 4 khz. What is the amplitude and frequency of synchronized oscillator waveform? [8] 7. (a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for multiple inputs. [8] (b) Explain with circuit diagram the operation of a two input sampling gate which does not have any loading effect on control signal. [8] 8. What is meant by blocking oscillator? Explain the principle of operation of monostable blocking oscillator with base timing. Sketch the current waveforms and derive an expression for current pulse width. [16] 2 of 2

28 Code No: V0421/R07 II B.Tech II Semester, Regular Examinations, Apr 2011 SET - 1 PULSE AND DIGITAL CIRCUITS (Com. to ECE, BME, ECC) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. a) Verify that one of the levels of the voltage across Capacitor V 2 = (V/2) (e 2x 1) / (e 2x +1) = (V/2) tan hx when a symmetrical square wave with time period of T is applied to a low pass RC circuit. Here x = T/(4RC). b) A 1 khz symmetrical square wave of ±10 V is applied to an RC circuit having 1 ms time constant. Calculate and plot the output for the RC configuration as i) high-pass circuit ii) Low pass circuit. 2. a) Explain transfer characteristics of the emitter coupled clipper and derive the necessary equations. b) Draw the basic circuit diagram of positive peak clamper circuit and explain its operation. 3. Write the following in detail: a) Diode switching times, b) Switching characteristics of a transistor and c) FET as a switch a) With the aid of circuit diagram, obtain the mathematical relation that a collector coupled astable multivibrator can function as a voltage to frequency converter. b) Consider a symmetrical collector coupled astable multivibrator using n-p-n Si transistors. The circuit and device parameters are: V CC = 6 V, R C = 560, R = 5.6 k, C = 50 pf, h FE = 40 and r bb = 100. Calculate i) the waveforms at the base and collector of one transistor and plot to the scale. Also find the recovery time and frequency of oscillations. 5. a) Draw and explain the typical waveform of a time-base voltage generator. Explain various types of errors encountered in time base generators. b) Explain the principle of working of exponential sweep circuit with neat circuit diagram and also derive the equations for slope, transmission and displacement error. 6. a) How an astable multivibrator can be synchronized? Illustrate with waveforms. b) A symmetrical astable multivibrator using Germanium transistors and operating from a 10 V collector supply voltage has a free period of 1ms. Triggering pulses whose spacing is 750 µ s are applied to one base through a small capacitor from a high impedance source. Find the minimum triggering pulse amplitude required to achieve 1:1 synchronization. Assume that the timing portion of the base waveform is linear. 7. a) Sketch circuit of a simple diode bidirectional sampling gate and describe its functioning with neat waveforms. Obtain the expressions for gain A, and the two minimum control voltage levels. b) Describe the operation of chopper amplifier. Give the operation of the transistor as a chopper switch in ON state and in OFF state. 8. a) Realize a two input TTL NAND gate truth table and explain its operation with suitable circuit diagram. b) With the help of neat circuit diagram and truth table, explain the working of diode logic AND gate, and RTL AND gate. 1 of 1

29 Code No: V0421/R07 SET - 2 II B.Tech II Semester, Regular Examinations, Apr 2011 PULSE AND DIGITAL CIRCUITS (Com. to ECE, BME, ECC) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. a) Prove that an RC low pass circuit behaves like an integrator if RC>15T, where T is the time period of the input sinusoidal signal. b) A 10 Hz square wave is applied to an RC high pass circuit. Calculate and draw the output waveform voltage levels under the following conditions: The lower 3-dB frequency is i) 0.3 Hz ii) 3 Hz iii) 30 Hz. 2. a) Explain the operation of a clamping circuit whose output signal has negative offset. What modifications are needed if the output voltage of the clamper circuit has positive offset? b) Design a diode clamper circuit to restore the positive peaks of 1 khz input signal to a voltage level equal to 5V. Assume that the diode voltage during forward bias condition is 0.7 V. 3. a) Define rise time, storage time, fall time, and turn off time in the case of transistor as a switch. b) Design a common emitter transistor switch operating with two power supplies V CC = 18 V, - V BB = -12 V. The transistor is expected to operate at I C = 8 ma, and I B = 0.75 ma. The static current gain is 25. Assume Si transistor, and R 2 = 5R a) Draw the self biased symmetrical binary circuit and derive the necessary relations for steady state analysis of the circuit. b) Discuss about different triggering methods used in multivibrator circuits. 5. a) What are the methods available for generating time-base waveforms? Explain the operation of one of them. b) Design a relaxation oscillator to have 2 khz output frequency using UJT for the given specifications: Supply voltage: 20 V, Intrinsic stand off ratio: 0.70, Peak Current = 2 µ A, Valley current: 1mA, and V v = 3V. Assume necessary data. 6. a) What do you mean by synchronization? b) What is the condition to be met for pulse synchronization? c) Compare sine wave synchronization with pulse synchronization. 7. a) With neat diagrams, explain the principle of operation of four diode bidirectional sampling gate. Compare the performance of the circuit with that of six diode bidirectional sampling gate. b) Describe the errors encountered in series sampling and what is the design procedure that is adopted to minimize these errors. 8. a) With the help of neat circuit diagram and truth table, explain the working of a three input DTL NAND gate. b) What do you mean by fan in and fan out? Discuss about the DTL NAND gate circuit which can improve Fan out of the gate. 1 of 1

30 Code No: V0421/R07 SET - 3 II B.Tech II Semester, Regular Examinations, Apr 2011 PULSE AND DIGITAL CIRCUITS (Com. to ECE, BME, ECC) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. a) Derive the expression for percentage tilt (P) of a square wave output of RC high pass circuit. b) An ideal 1 µ s pulse is fed to a low pass circuit. Calculate and plot the output waveform under the following conditions: the upper 3-dB frequency is i) 10 MHz ii) 0.1 MHz iii) 0.01 MHz. 2. a) Draw a circuit diagram for getting a slicing the input sinusoidal signal to 2V on either side of the signal. Assume that the amplitude of the applied signal is more than ±2V. b) Draw the transfer characteristics of double ended clipping circuit and explain its operation with suitable circuit diagram. 3. a) A rectangular pulse of voltage is applied to the base of a transistor driving it from cutoff to saturation. Discuss the changes in the output potential. Explain the various times involved in the switching process. b) Design a transistor circuit that acts as switch for the given specifications: V CC = 20 V, I C = 5 ma. It is a Si transistor having h FEmin = 20. Assume necessary data a) Explain the operation of an emitter bistable multivibrator circuit with suitable sketches. b) Design a Schmitt trigger circuit to have UTP = 6 V, LTP = 3 V using silicon transistors whose h FE(min) = 40. Assume necessary data. 5. a) With the help of suitable sketches, explain the working of constant current sweep generator. b) Design a transistor ramp generator to provide an output amplitude of 12V over a time period of 2 ms. The input signal is a negative going pulse with an amplitude of 5 V, a pulse width of 2ms and the time interval between pulses is 0.5 ms. The total load resistance is 2 k ohms and the ramp is to be linear within 1%. The supply is to be ±15 V, and h FEmin = 50. Assume necessary data. 6. a) Illustrate the terms Synchronization and frequency division of a sweep generator. b) A free running relaxation oscillator has sweep amplitude of 100 V and a period of 1 ms synchronizing pulses are applied to the device such that breakdown voltage is lowered by 50 V at each pulse. The synchronizing pulse frequency is 4 khz. What is the amplitude and frequency of synchronized oscillator waveform? 7. a) Illustrate with neat circuit diagram, the operation of unidirectional sampling gate for multiple inputs. b) Explain the operation of a two input sampling gate which does not have any loading effect on control signal. c) Give the importance of chopper amplifier. 8. Explain the following: a) Realization of AND, and OR gates using universal gates. b) What do you mean by fan in and fan out? Discuss about the DTL NAND gate circuit which can improve fan out of the gate. 1 of 1

31 Code No: V0421/R07 SET - 4 II B.Tech II Semester, Regular Examinations, Apr 2011 PULSE AND DIGITAL CIRCUITS (Com. to ECE, BME, ECC) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. a) Derive suitable expression for output voltage of an RC high pass circuit if an exponential input is applied as an input. b) A 10 Hz symmetrical square wave whose peak to peak amplitude of 2 V is applied to a high pass RC circuit whose lower 3-dB frequency is 5 Hz. Calculate and sketch the output waveform for the first two cycles. What is the peak to peak output amplitude under steady state conditions? 2. a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer characteristic. b) Draw the circuit diagram of emitter coupled clipper. Draw its transfer characteristics indicating all intercepts, slopes and voltage levels derive the necessary equations. 3. a) Describe the sequence of events that lead to reverse recovery time, storage time, and transition time in a semiconductor diode. b) A common emitter circuit with Si transistor has V CC = 15 V, R C = 15 k ohms, and I B = 0.3 ma. Determine the value of h FE(min) for saturation to occur. If R C is changed to 500 ohms, will the transistor be saturated? 4. a) Explain the operation of an emitter coupled monostable multivibrator circuit. b) Design a collector coupled monostable multivibrator circuit for the given specifications: V CC = 8V, V BE = -1.5V, I C(sat) = 2 ma, period of the quasi stable state is 2.0 µs. h FE(min) = 20, the ON transistor (Si) has base current which is 50% in excess of minimum base current. Assume R 2 = 2R 1, and I CBO = 0. Assume suitable data. 5. a) Explain the basic principles of the Miller and Bootstrap time base generators with suitable sketches. b) Obtain expression for slope error in the case of a constant current sweep circuit. 6. a) Explain the factors which influence the stability of a relaxation divider with the help of neat waveforms. b) A UJT sweep operates with Vv = 3V, Vp=16V and = 0.5. A sinusoidal synchronizing voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz, over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? 7. a) What is sampling gate? Explain how it differs from Logic gates? b) What is pedestal? How it effect the output of sampling gates? c) What are the drawbacks of two diode sampling gate? 8. a) Why totem pole is used in DTL? Draw the circuit diagram and explain a DTL gate with this. b) Verify the truth table of a two input RTL-NOR gate with the circuit diagram and explain its operation. 1 of 1

32 Code No: R Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is the period of an input E m sin ωt. (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8] 2. (a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer characteristic. (b) Draw the circuit diagram of emitter coupled clipper. Draw its transfer characteristics indicating all intercepts, slopes and voltage levels derive the necessary equations. [8+8] 3. (a) Explain the terms pertaining to transistor switching characteristics. i. Rise time. ii. Delay time. iii. Turn-on time. iv. Storage time. v. Fall time. vi. Turn-off time. (b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents. [6+10] 4. In the nonsaturated binary shown in figure 4, the avalanche diodes D1 and D2 are nominally identical, as are diodes D3 and D4. The breakdown voltage V?Z of D3 and D4 is larger than the breakdown voltage V Z of D1 and D2. Verify that the transistors do not enter the saturation region. Assume that D3 and D4 are always in the breakdown region and that either D1 or D2 but not both, is in the breakdown region. Then verify these assumptions. [16] 1 of 2

33 Code No: R Set No. 1 Figure 4 5. (a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage. (b) Derive the relation between the slope, transmission and displacement errors (c) Explain how UJT is used for sweep circuit? [6+4+6] 6. (a) What do you mean by synchronization? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization? [4+6+6] 7. (a) Why are sampling gates called Selection circuits? (b) What are the advantages of unidirectional sampling gates? (c) What are the applications of sampling gates? [6+4+6] 8. (a) With the help of circuit diagram explain the purpose of clamping diode in a positive diode AND gate. (b) Explain the effect of and diode capacitance on the output pulse of diode AND gate. [8+8] 2 of 2

34 Code No: R Set No. 2 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is the period of an input E m sin ωt. (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8] 2. (a) State and prove clamping -circuit theorem. (b) A clamping circuit and input wave form is shown in figure 2b calculate and plot to scale the steady state output [8+8] 3. Write Short notes on: Figure 2b (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. (a) Consider the symmetrical emitter triggering circuit of the figure 4 with Rc=3Re, R 1 =2R2, and V CC =6V. Indicate all the circuit voltages in the quiescent state and indicate also the voltages immediately after a 5-V positive step is applied. Assume that D3 and D4 are always in the breakdown region and that either D1 or D2 but not both in the breakdown region. 1 of 2

35 Code No: R Set No. 2 (b) Repeat part (a) for a 25-V step. What limits the maximum size of the input step? What limits the minimum size of the input step? [16] Figure 4 5. (a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage. (b) Derive the relation between the slope, transmission and displacement errors (c) Explain how UJT is used for sweep circuit? [6+4+6] 6. (a) Explain the factors which influence the stability of a relaxation divider with the help of a neat waveforms. (b) A UJT sweep operates with Vv = 3V, Vp=16V and η=0.5. A sinusoidal synchronizing voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz, over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? [8+8] 7. (a) What is sampling gate? Explain how it differ from Logic gates? (b) What is pedestal? How it effects the output of a sampling gates? (c) What are the drawbacks of two diode sampling gate? [6+6+4] 8. (a) Draw and explain the circuit diagram of integrated positive RTL NOR gate (b) Compare the RTL and DTL logic families in terms of Fan out, propagation delay, power dissipated per gate and noise immunity. [8+8] 2 of 2

36 Code No: R Set No. 3 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Verify V 2 = (V/2)(e 2x 1)/(e 2x +1) = (V/2) tanhx for a symmetrical square wave applied to a low pass RC circuit. (b) Derive the expression for percentage tilt(p) of a square wave output of RC high pass circuit. [8+8] 2. (a) Give the circuits of different types of shunt clippers and explain their operation with the help of their transfer characteristics. (b) Draw the diode differentiator comparator circuit and explain the operation of it when ramp input signal is applied. [8+8] 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Derive the Expressions for its UTP and LTP. (b) Explain how an Schmitt trigger circuit acts as a comparator. [12+4] 5. (a) Explain the basic principles of Miller and bootstrap time base generators. (b) A transistor bootstrap ramp generator is to produce a 15V, 5ms output to a 2kohms load resistor. The ramp is to be linear within 2%. Design a suitable circuit using V cc = 22V, V EE = -22V and transistor with h fe(min) = 25. The input pulse has an amplitude of -5V, pulse width = 5ms and space width = 2.5ms. [8+8] 6. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation oscillators and give its applications. (b) With the help of a circuit diagram and waveforms, explain the frequency division by an astable multivibrator? [8+8] 7. (a) Why are sampling gates called linear gates? (b) What are the other names of a gate signal? (c) Compare the unidirectional and bi-directional sampling gates. [6+4+6] 1 of 2

37 Code No: R Set No (a) Why totem pole is used in DTL? Draw the circuit diagram and explain a DTL gate with this. (b) Verify the truth table of RTL NOR gate with the circuit diagram of two inputs. [8+8] 2 of 2

38 Code No: R Set No. 4 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) What is the function of a comparator? Explain its operation. (b) Explain the response of a low pass circuit to an exponential input is applied. (c) Explain the response of RL circuit when a rectangular pulse is applied [4+6+6] 2. (a) For the circuit shown in figure 2a, V i is a sinusoidal voltage of peak 100 volts. Assume ideal diodes. Sketch one cycle of output voltage. Determine the maximum diode Current. Figure 2a (b) Explain positive peak clipping with reference voltage. [12+4] 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. In the monostable circuit of the given figure 4 the resistor R is connected to an auxiliary supply V 1 instead of V Y Y. If A2 is in saturation or clamp and if A1 is OFF in the stable state, verify that the gate time T is given by Eq. T =τln(v YY +I 1 R Y Vσ)/(V YY Vγ) with V Y Y replaced by V 1. [16] 1 of 3

39 Code No: R Set No. 4 Figure 4 5. (a) How are linearly varying current waveforms generated? (b) In the boot strap circuit shown in figure5 V cc = 25 V, V EE = -15 V, R = 10 K ohms, R B = 150 K ohms, C = 0.05 µf. The gating waveform has a duration of 300 µs. The transistor parameters are h ie = 1.1Kohms, h re = 2.5 x 10 4 K ohmsh fe =50 h oe = 1/40K ohms. i. Draw the waveform of IC1 and Vo, labeling all current and voltage levels, ii. What is the slope error of the sweep? iii. What is the sweep speed and the maximum value of the sweep voltage? iv. What is the retrace time Tr for C to discharge completely? v. Calculate the recovery time T1 for C1 to recharge completely. [6+10] Figure 5 2 of 3

40 Code No: R Set No (a) Explain how monostable multivibrator is used as frequency divider? (b) Draw and explain the block diagram of frequency divider without phase jitter. [8+8] 7. (a) Why are sampling gates called linear gates? (b) What are the other names of a gate signal? (c) Compare the unidirectional and bi-directional sampling gates. [6+4+6] 8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 3 of 3

41 Code No: R Set No. 1 II B.Tech I Semester Supplimentary Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Derive the expression for rise time of integrating circuit and prove that it is proportional to time constant and inversely proportional to upper 3 db frequency. (b) Explain the operation of RC low pass circuit for exponential input is applied. [8+8] 2. (a) T=1000 µ sec V= 10 V Duty cycle = 0.2 i. Sketch waveform with voltage levels at steady state figure 2(a)iii ii. Forward and reverse direction tilt iii. A f / A r Figure 2(a)iii (b) Write a short note on non- linear wave shaping. [12+4] 3. (a) Explain the behaviour of a BJT as a switch in electronic circuits. Give an example. (b) Write a short note on the switching times of transistor. [8+8] 4. What is a monostable multivibrator? Explain with the help of a neat circuit diagram the principle of operation of a monostable multi, and derive an expression for pulse width. Draw the wave forms at collector and Bases of both transistors. [16] 5. (a) With the help of a neat circuit diagram and waveforms explain the working of a transistor Miller time base generator. 1 of 2

42 Code No: R Set No. 1 (b) Find the component values of a bootstrap sweep generator, given Vcc=18V, Ic(sat) = 2mA and hfe(min)=30. [8+8] 6. (a) Explain the factors which influence the stability of a relaxation divider with the help of a neat waveforms. (b) A UJT sweep operates with Vv = 3V, Vp=16V and η=0.5. A sinusoidal synchronizing voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz, over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? [8+8] 7. (a) What is sampling gate? Explain how it differ from Logic gates? (b) What is pedestal? How it effects the output of a sampling gates? (c) What are the drawbacks of two diode sampling gate? [6+6+4] 8. (a) With the help of circuit diagram explain the purpose of clamping diode in a positive diode AND gate. (b) Explain the effect of and diode capacitance on the output pulse of diode AND gate. [8+8] 2 of 2

43 Code No: R Set No. 2 II B.Tech I Semester Supplimentary Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) A square wave whose peak-to-peak value is 1V, extends ±0.5V with reference to ground. The half period is 0.1 sec This voltage impressed upon an R.C. differentiating circuit whose time constant is 0.2 sec. Determine the maximum and minimum values of the output voltage in the steady state. (b) Draw the response of high pass circuit for square wave and derive the expression for percentage tilt. [8+8] 2. (a) For the circuit shown in figure 2a V S is a sinusoidal voltage of peak 75 volts. Assuming ideal diodes. Sketch one cycle of output voltage. Determine the maximum diode currents. Figure 2a (b) What are the uses of clipper circuits. [12+4] 3. (a) Explain the terms pertaining to transistor switching characteristics. i. Rise time. ii. Delay time. iii. Turn-on time. iv. Storage time. v. Fall time. vi. Turn-off time. (b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents. [6+10] 4. Draw and explain about the response of Schmitt circuit for the following. (a) for loop gain 1 1 of 3

44 Code No: R Set No. 2 (b) loop gain >1. [16] 5. (a) How are linearly varying current waveforms generated? (b) In the boot strap circuit shown in figure5 V cc = 25 V, V EE = -15 V, R = 10 K ohms, R B = 150 K ohms, C = 0.05 µf. The gating waveform has a duration of 300 µs. The transistor parameters are h ie = 1.1Kohms, h re = 2.5 x 10 4 K ohmsh fe =50 h oe = 1/40K ohms. i. Draw the waveform of IC1 and Vo, labeling all current and voltage levels, ii. What is the slope error of the sweep? iii. What is the sweep speed and the maximum value of the sweep voltage? iv. What is the retrace time Tr for C to discharge completely? v. Calculate the recovery time T1 for C1 to recharge completely. [6+10] Figure 5 6. (a) What do you mean by synchronization? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization? [4+6+6] 7. (a) Explain the balance conditions in a bi-directional diode gate. (b) Explain the utility of sampling gate in a sampling scope. [8+8] 8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. 2 of 3

45 Code No: R Set No. 2 (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 3 of 3

46 Code No: R Set No. 3 II B.Tech I Semester Supplimentary Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Wtite short note on the following: (a) Attenuators (b) RC Double differentiator. (c) RLC ringing circuit. [5+6+5] 2. (a) A symmetrical 10 khz square wave whose peak -to-peak excursion are±10v with respect to ground is impressed upon the diode clamping circuit shown in figure 2a. The Diodes has R f = 100 Ω, R r = α and V γ = 0. Sketch the steady state output waveform Indicating clearly the voltage levels. Figure 2a (b) Explain positive peak voltage limiters above and below reference level. [8+8] 3. (a) Sketch neatly the waveforms of current & voltages for a transistor switch with capacitance loading circuit. (b) What are catching diodes? [12+4] 4. (a) Draw the circuit of a bistable multivibrator with symmetrical collector triggering. (b) Design a monostable circuit that produces a pulse width of 10msec. (Assume the required date) [8+8] 5. (a) With the help of a neat circuit diagram and waveforms explain the working of a transistor Miller time base generator. (b) Find the component values of a bootstrap sweep generator, given Vcc=18V, Ic(sat) = 2mA and hfe(min)=30. [8+8] 6. (a) What is relaxation oscillator? Explain how it is used for synchronization? Name some negative resistance devices used as relaxation oscillators. 1 of 2

47 Code No: R Set No. 3 (b) Explain how Astable multivibrator is used for frequency division? [8+8] 7. (a) Draw and explain a sampling diode whose response is not sensitive to the upper level of the control voltage. (b) Draw and explain a unidirectional gate which delivers an output only at a coincidence of a number of control voltages. [8+8] 8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 2 of 2

48 Code No: R Set No. 4 II B.Tech I Semester Supplimentary Examinations, November 2008 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is the period of an input E m sin ωt. (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8] 2. (a) For the circuit shown in figure 2a an input voltage V i linearly from 0 to 150V is applied. Sketch the output waveform V 0 to the same time scale. Assume ideal diodes. Figure 2a (b) What in meant by a d.c restoration circuit and explain? [12+4] 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. In the monostable circuit of the given figure 4 the resistor R is connected to an auxiliary supply V 1 instead of V Y Y. If A2 is in saturation or clamp and if A1 is OFF in the stable state, verify that the gate time T is given by Eq. T =τln(v YY +I 1 R Y Vσ)/(V YY Vγ) with V Y Y replaced by V 1. [16] 1 of 2

49 Code No: R Set No. 4 Figure 4 5. (a) Compare the principle of operation of Miller sweep circuit and Bootstrap sweep circuit (b) Explain how linearity is obtained by adjusting the driving waveform of current sweep circuit. [8+8] 6. (a) Draw the circuit diagram of an astable multivibrator to obtain frequency division by 5. Explain its working with waveforms. (b) What is phase jitter? Discuss the significance of it in a frequency divider. [8+8] 7. (a) What is sampling gate? Explain how it differ from Logic gates? (b) What is pedestal? How it effects the output of a sampling gates? (c) What are the drawbacks of two diode sampling gate? [6+6+4] 8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 2 of 2

50 Code No: R Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is the period of an input E m sin ωt. (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8] 2. (a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer characteristic. (b) Draw the circuit diagram of emitter coupled clipper. Draw its transfer characteristics indicating all intercepts, slopes and voltage levels derive the necessary equations. [8+8] 3. (a) Explain the terms pertaining to transistor switching characteristics. i. Rise time. ii. Delay time. iii. Turn-on time. iv. Storage time. v. Fall time. vi. Turn-off time. (b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents. [6+10] 4. In the nonsaturated binary shown in figure 4, the avalanche diodes D1 and D2 are nominally identical, as are diodes D3 and D4. The breakdown voltage V?Z of D3 and D4 is larger than the breakdown voltage V Z of D1 and D2. Verify that the transistors do not enter the saturation region. Assume that D3 and D4 are always in the breakdown region and that either D1 or D2 but not both, is in the breakdown region. Then verify these assumptions. [16] 1 of 2

51 Code No: R Set No. 1 Figure 4 5. (a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage. (b) Derive the relation between the slope, transmission and displacement errors (c) Explain how UJT is used for sweep circuit? [6+4+6] 6. (a) What do you mean by synchronization? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization? [4+6+6] 7. (a) Why are sampling gates called Selection circuits? (b) What are the advantages of unidirectional sampling gates? (c) What are the applications of sampling gates? [6+4+6] 8. (a) With the help of circuit diagram explain the purpose of clamping diode in a positive diode AND gate. (b) Explain the effect of and diode capacitance on the output pulse of diode AND gate. [8+8] 2 of 2

52 Code No: R Set No. 2 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T, Where T is the period of an input E m sin ωt. (b) What is the ratio of the rise time of the three sections in cascade to the rise time of Single section of low pass RC circuit. [8+8] 2. (a) State and prove clamping -circuit theorem. (b) A clamping circuit and input wave form is shown in figure 2b calculate and plot to scale the steady state output [8+8] 3. Write Short notes on: Figure 2b (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. (a) Consider the symmetrical emitter triggering circuit of the figure 4 with Rc=3Re, R 1 =2R2, and V CC =6V. Indicate all the circuit voltages in the quiescent state and indicate also the voltages immediately after a 5-V positive step is applied. Assume that D3 and D4 are always in the breakdown region and that either D1 or D2 but not both in the breakdown region. 1 of 2

53 Code No: R Set No. 2 (b) Repeat part (a) for a 25-V step. What limits the maximum size of the input step? What limits the minimum size of the input step? [16] Figure 4 5. (a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage. (b) Derive the relation between the slope, transmission and displacement errors (c) Explain how UJT is used for sweep circuit? [6+4+6] 6. (a) Explain the factors which influence the stability of a relaxation divider with the help of a neat waveforms. (b) A UJT sweep operates with Vv = 3V, Vp=16V and η=0.5. A sinusoidal synchronizing voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz, over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? [8+8] 7. (a) What is sampling gate? Explain how it differ from Logic gates? (b) What is pedestal? How it effects the output of a sampling gates? (c) What are the drawbacks of two diode sampling gate? [6+6+4] 8. (a) Draw and explain the circuit diagram of integrated positive RTL NOR gate (b) Compare the RTL and DTL logic families in terms of Fan out, propagation delay, power dissipated per gate and noise immunity. [8+8] 2 of 2

54 Code No: R Set No. 3 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Verify V 2 = (V/2)(e 2x 1)/(e 2x +1) = (V/2) tanhx for a symmetrical square wave applied to a low pass RC circuit. (b) Derive the expression for percentage tilt(p) of a square wave output of RC high pass circuit. [8+8] 2. (a) Give the circuits of different types of shunt clippers and explain their operation with the help of their transfer characteristics. (b) Draw the diode differentiator comparator circuit and explain the operation of it when ramp input signal is applied. [8+8] 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Derive the Expressions for its UTP and LTP. (b) Explain how an Schmitt trigger circuit acts as a comparator. [12+4] 5. (a) Explain the basic principles of Miller and bootstrap time base generators. (b) A transistor bootstrap ramp generator is to produce a 15V, 5ms output to a 2kohms load resistor. The ramp is to be linear within 2%. Design a suitable circuit using V cc = 22V, V EE = -22V and transistor with h fe(min) = 25. The input pulse has an amplitude of -5V, pulse width = 5ms and space width = 2.5ms. [8+8] 6. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation oscillators and give its applications. (b) With the help of a circuit diagram and waveforms, explain the frequency division by an astable multivibrator? [8+8] 7. (a) Why are sampling gates called linear gates? (b) What are the other names of a gate signal? (c) Compare the unidirectional and bi-directional sampling gates. [6+4+6] 1 of 2

55 Code No: R Set No (a) Why totem pole is used in DTL? Draw the circuit diagram and explain a DTL gate with this. (b) Verify the truth table of RTL NOR gate with the circuit diagram of two inputs. [8+8] 2 of 2

56 Code No: R Set No. 4 II B.Tech I Semester Regular Examinations, November 2007 PULSE AND DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) What is the function of a comparator? Explain its operation. (b) Explain the response of a low pass circuit to an exponential input is applied. (c) Explain the response of RL circuit when a rectangular pulse is applied [4+6+6] 2. (a) For the circuit shown in figure 2a, V i is a sinusoidal voltage of peak 100 volts. Assume ideal diodes. Sketch one cycle of output voltage. Determine the maximum diode Current. Figure 2a (b) Explain positive peak clipping with reference voltage. [12+4] 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. In the monostable circuit of the given figure 4 the resistor R is connected to an auxiliary supply V 1 instead of V Y Y. If A2 is in saturation or clamp and if A1 is OFF in the stable state, verify that the gate time T is given by Eq. T =τln(v YY +I 1 R Y Vσ)/(V YY Vγ) with V Y Y replaced by V 1. [16] 1 of 3

57 Code No: R Set No. 4 Figure 4 5. (a) How are linearly varying current waveforms generated? (b) In the boot strap circuit shown in figure5 V cc = 25 V, V EE = -15 V, R = 10 K ohms, R B = 150 K ohms, C = 0.05 µf. The gating waveform has a duration of 300 µs. The transistor parameters are h ie = 1.1Kohms, h re = 2.5 x 10 4 K ohmsh fe =50 h oe = 1/40K ohms. i. Draw the waveform of IC1 and Vo, labeling all current and voltage levels, ii. What is the slope error of the sweep? iii. What is the sweep speed and the maximum value of the sweep voltage? iv. What is the retrace time Tr for C to discharge completely? v. Calculate the recovery time T1 for C1 to recharge completely. [6+10] Figure 5 2 of 3

58 Code No: R Set No (a) Explain how monostable multivibrator is used as frequency divider? (b) Draw and explain the block diagram of frequency divider without phase jitter. [8+8] 7. (a) Why are sampling gates called linear gates? (b) What are the other names of a gate signal? (c) Compare the unidirectional and bi-directional sampling gates. [6+4+6] 8. (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 3 of 3

59 Code No: R Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Explain the response of a high pass circuit to an exponential input is applied. (b) Write short note on piping process. [8+8] 2. (a) Explain transfer characteristics of the emitter coupled clipper and derive the necessary equations. (b) Draw the basic circuit diagram of positive peak clamper circuit and explain its operation. [8+8] 3. Write Short notes on: (a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch. [4+8+4] 4. (a) Design a collector coupled transistor monostable multivibrator to produce a time delay of 100 µsec. Use transistors have h FE of 250. Use±12v sources, V CE(sat) = 0.3v, V BE(sat) = 0.7v and V BEcutoff = 0v (b) Show that the astable multivibrator works as voltage controlled oscillator. [10+6] 5. (a) Draw and explain the typical waveform of a time-base voltage. (b) Explain the principle of working of exponential sweep circuit with neat circuit diagram and also derive the equations for slope, transmission and displacement error. [6+10] 6. (a) Explain the factors which influence the stability of a relaxation divider with the help of a neat waveforms. (b) A UJT sweep operates with Vv = 3V, Vp=16V and η=0.5. A sinusoidal synchronizing voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz, over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? [8+8] 7. (a) What is sampling gate? Explain how it differ from Logic gates? (b) What is pedestal? How it effects the output of a sampling gates? (c) What are the drawbacks of two diode sampling gate? [6+6+4] 1 of 2

60 Code No: R Set No (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 2 of 2

61 Code No: R Set No. 2 II B.Tech I Semester Regular Examinations, November 2006 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) A square wave of 5 V amplitude with an ON time of 1 msec and an OFF time of 3 m sec is applied to a high pass RC circuit with R = 2K and C = 0.1 µ f. Sketch the steady state output waveform showing all the details (b) Explain the operation of RC high pass circuit when exponential input is applied. [8+8] 2. (a) Draw the circuit diagram of slicer circuit using Zener diodes and explain its operation with the help of its transfer characteristic. (b) Draw the circuit diagram of emitter coupled clipper. Draw its transfer characteristics indicating all intercepts, slopes and voltage levels derive the necessary equations. [8+8] 3. (a) Sketch neatly the waveforms of current & voltages for a transistor switch with capacitance loading circuit. (b) What are catching diodes? [12+4] 4. (a) Explain the reason for the occurrence of overshoot at the base of normally ON transistor of one shot. Derive an expression for overshoot. (b) Discuss a few applications of a monostable multivibrator. Explain how it differs with that of a binary. [8+8] 5. (a) How are linearly varying current waveforms generated? (b) In the boot strap circuit shown in figure5 V cc = 25 V, V EE = -15 V, R = 10 K ohms, R B = 150 K ohms, C = 0.05 µf. The gating waveform has a duration of 300 µs. The transistor parameters are h ie = 1.1Kohms, h re = 2.5 x 10 4 K ohmsh fe =50 h oe = 1/40K ohms. i. Draw the waveform of IC1 and Vo, labeling all current and voltage levels, ii. What is the slope error of the sweep? iii. What is the sweep speed and the maximum value of the sweep voltage? iv. What is the retrace time Tr for C to discharge completely? v. Calculate the recovery time T1 for C1 to recharge completely. [6+10] 1 of 3

62 Code No: R Set No. 2 Figure 5 6. (a) What do you mean by synchronization? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization? [4+6+6] 7. (a) Draw and explain an emitter coupled bi-directional sampling gate. (b) For the four diode gate shown in figure 7 with a divider resistance R used. V s =25V, R f =20 ohms, R L =R C =200K ohms and R= 100 ohms. Find V cmin, A and V nmin? [8+8] 2 of 3 Figure 7

63 Code No: R Set No (a) What are the basic logic gates which perform almost all the operations in Digital communication systems. (b) Give some applications of logic gates. (c) Define a positive and negative logic systems. (d) Draw a pulse train representing a in a synchronous positive logic digital system. [ ] 3 of 3

64 Code No: R Set No. 3 II B.Tech I Semester Regular Examinations, November 2006 PULSE & DIGITAL CIRCUITS ( Common to Electrical & Electronic Engineering, Electronics & Communication Engineering, Electronics & Instrumentation Engineering and Electronics & Telematics) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) An ideal 1 µ -Sec pulse is fed to a low pass circuit. Calculate and plot the output waveform under the following conditions: The upper 3-dB frequency is i. 10 MHz ii..1 MHz iii..0.1 MHz. (b) Explain RLC ringing circuit. [10+6] 2. (a) Design a clipping circuit with ideal components, which can give the waveform shown in figure 2a for a sinusoidal input. Figure 2a (b) State and prove clamping circuit theorem. [8+8] 3. (a) Sketch neatly the waveforms of current & voltages for a transistor switch with capacitance loading circuit. (b) What are catching diodes? [12+4] 4. (a) Explain the operation of Astable multivibrator with a circuit diagram with relevant waveforms. (b) A collector coupled monostable multi using n-p-n silicon transistor has the following parameters Vcc = 12v, V BB = 3v, R C = 2k, R1 = R2 = R = 20k, h FE = 30, r bb = 200 Ω and c = 1000pF. Calculate and plot to scale the wave slopes at each base and collector. Also find width of the o/p pulse. [8+8] 5. (a) What type of Voltage input is required to obtain a linear current sweep? (b) The transistor bootstrap circuit shown in Figure 5 has the following parameters V CC = 10 V, V EE = -10V, R B = 30 K ohms, C=0.002 µf, C 1 =0.25µF 1 of 2