I. Physikalisches Institut

Transcription

1 PEBS Electronics W. Karpinski I. Physikalisches Institut Aachen, 10 January Feb 2007 Waclaw Karpinski 1

2 Outline An overview of the PEBS Electronics Subdetector Readout: -TRD -Tracker -ECAL -ToF - TGB (Trigger Box) Summary 5 Feb 2007 Waclaw Karpinski 2

3 PEBS Electronics 5 Feb 2007 Waclaw Karpinski 3

4 AMS Electronics Subdetector DAQ Global DAQ Detector Custom ASIC CDP: Common Digital Sample Part & Hold Digitization M UX ADC DSP Gate Array Data Reduction AMSWire Gate Busy CDDC DSP GA Mem Command Distrib, Data Collect. CDDC AmsW AmsW MAIN DATA Comp HRDL LRDL Sequence Trigger Input Memories LRS Trigger (H)V Detect. Vdd (Analog) Vdd(Digital) Lin Reg Slave M&C 2x CAN DC-DC Converters (28 -> 5,3.3,+-2) (High Efficiency) Subd. Power 28V Filter (I/O) 28 V Global Power 120V M.Capell Jan 04 5 Feb 2007 Waclaw Karpinski 4

5 PEBS -TRD 16 layers, 7 chambers/layer =112 chambers 16 straw tubes per chamber 1792 channels in total the readout schema could be the same as in AMS2 the available spare boards can be used in PEBS-TRD readout 5 Feb 2007 Waclaw Karpinski 5

6 AMS2-TRD Readout UFE UTE UHVD = front end = tube end = high voltage distribution UPSFE UDR JINF UHVG = power supply for UFE = data reduction board = interface board for higher DAQ = high voltage generator 5 Feb 2007 Waclaw Karpinski 6

7 AMS2-TRD Readout U-Crate UPD not available for PEBS UDR2 UPSFE JINF UHVG 5 Feb 2007 Waclaw Karpinski 7

8 Front-End Electronics : UFE Airborn Connectors MA ESD-Protection IC and Network Ch 1-32 VA 1 Schematic Diagram of UFE +2.0 A -2.0 A Micro D-Sub Connector 21 pol A -2.0 A GND +2.0 D -2.0 D 65.8mm Ch VA 2 Σ V DC shift CAL 12 bit ADC AD D -2.0 D +2.0 D + SDATA+ - SDATA D SCLK+ + - SCLK- 118mm Dreset1, Dreset6, ShiN1, ShiN2, CLK_FF, Dreset5, hold, hold_b, test_on Hybrid Control Circuit & Logic Unit S SB H HB 5 Feb 2007 Waclaw Karpinski 8

9 Data Reduction UDR2 OUT DSP Gate Array Hot Side Cold Side Analog::Digital Isolation Barrier Digitized Data 7x 64x IN Performs: buffering of the raw data data reduction in the DSP data transmission to the Global DAQ 5 Feb 2007 Waclaw Karpinski 9

10 Structure of the PEBS -TRD Readout Equipment needed: 28x UFE, 4x UDR, 2x UPSF, 4xUHVD, 1x C&DI TRD Power Consumption = UFE(7W) + Ucrate(13W) + UPD(11W) =31W 5 Feb 2007 Waclaw Karpinski 10

11 PEBS -TRD CRATE UDR -data reduction board UPSFE -power supply for UFE C&DI - interface for higer DAQ UHVD - high voltage generator 5 Feb 2007 Waclaw Karpinski 11

12 PEBS -Tracker 4 disks á 46 modules = 184 Modules readout using SiPM arrays with 32 strips 4 SiPM arrays on each module end two Front End Hybrids/module á 128 channels in total channels arrangement of the SiPM arrays on the module end SiPM array with 16 channels 5 Feb 2007 Waclaw Karpinski 12

13 SiPM specifications - channel size: 1 mm x 0.25 mm - pixel size: x mm 2 = 135 pixels/channel 8 bit ADC - operating voltage: ~ 40V - gain = 0.8 x 10 6 preamplifier with large dynamic range necessary - SiPM gain varies with bias voltage: 40% / 1V Do we need gain adjustment for individual channels? If yes, it must be implemented on chip level (DAC) new chip design necessary significant increase of cost and development time - dark current =500 na/channel PEBS -Tracker - dark count ~.5 MHz (40V, T=22 C) fast shaping time required to reduce pile up ac coupling between detector and preamplifier or active leakage current compensation on the chip 5 Feb 2007 Waclaw Karpinski 13

14 SiPM- Behaviour Temperature depandance from Nakamura (KOBE) (7th ACFA workshop on Physics and Detector at the Linear Collider) gain shift by 1.5% / C gain variations with bias voltage by 80%/1V increase of noise rate by factor of 70%/10 C the operation temperature of SiPM should be well controlled the operation temperature should be low precise voltage control for good gain stability 5 Feb 2007 Waclaw Karpinski 14

15 ROCs possibly adequate for SiPM signal processing 5 Feb 2007 Waclaw Karpinski 15

16 Characteristics MAROC : 64 ch MAPMT chip for ATLAS lumi 64 PMT channels input ( Ω) Variable gain current conveyor (0-2) 6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16 64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron (50fC). Counting rate up to 2 MHz Common threshold loaded by internal 10bit DAC 1 multiplexed charge output with variable shaping ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pc) Crosstalk < 1% 64 PM inputs Variab le Gain Pream p. Gain correction 6 bits/channel Hold signal Variable Slow Shaper Bipolar Fast Shaper discriminator threshold 10 bits DAC S&H 10 bit DAC Synoptic diagramm of MAROC1 N. Seguin (LAL) Multiplexed charge output 64 Trigger outputs Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm 2 Dissipation 130 VDD=3.5V 5 Feb 2007 Waclaw Karpinski 16

17 18-channel 8-bit DAC (0-5V) 18-channel front-end readout : ILC SiPM Chip Variable gain charge preamplifier (0.67 to 10 V/pC) Variable shaping time CRRC2 shaper (12 to 180 ns) Track and hold 1 multiplexed output Power consumption : ~200mW (supply : 0-5V) Technology : AMS 0.8 µm CMOS Chip area : ~10mm² Package : QFP Feb 2007 Waclaw Karpinski 17

18 Channel architecture for SiPM readout in 8-bit DAC 0-5V 100MΩ 0.1pF 0.2pF 0.4pF 0.8pF 12kΩ ASIC 40kΩ 2.4pF 1.2pF 0.6pF 0.3pF 50Ω 10pF Rin = 10kΩ 8pF 4pF 2pF 1pF 4kΩ 24pF 12pF 100nF 6pF 3pF Charge Preamplifier : CR-RC² Shaper : Low noise : Variable time constant : 4 bits (12 to 180ns) 12ns photoelectron measurement (calibration mode) Variable gain : 180ns Mip measurement (physics mode) 4bits : 0.67 to 10 V/pC compatibility with ECAL read-out 5 Feb 2007 Waclaw Karpinski 18

19 Prospective for A-HCAL SiPM Chip Similar developments for AHCAL Chip fully dedicated to SiPMs Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing 8 bit DAC (0-5V) in Variable gain Preamplifier Capacitance for AC coupling T&H Shaper t p ~30-40ns Fast Shaper Analogue Memory Threshold 5 Feb 2007 Waclaw Karpinski 19 x1 Auto-trigger 12-bit DAC Discri Charge Ouput Time Ouput 12-bit ADC TDC

20 PEBS-Tracker Readout FE-Hybrid Ver.2 FE Hybrid consists of: - biasing network - 2 VA64 chips - 1 amplifier - readout control - expected power consumption 2 mw / channel - readout time ~85 µs/event 5 Feb 2007 Waclaw Karpinski 20

21 Tracker Front-End Hybrid SiPMs Arrays VA64-chip Biasing & AC coupling 5 Feb 2007 Waclaw Karpinski 21

22 Data Reduction TDR2 Boards The readout of PEBS-Tracker can be realized using modified TRD2 boards from AMS Architecture - on FE-Hybrid analog signal processing only - TRD2 performs digitization calibration and data reduction for 2048 channels 640x IN 384x IN Analog Receivers +80V 2x ADC ADC TDR2 Analog::Digital Isolation Barrier Data Reduction Data Compresion DSP Gate Array OUT 6 analogue inputs and 6 ADCs per board 5 Feb 2007 Waclaw Karpinski 22

23 PEBS-Tracker Readout 16 FE-Hybrids á 128 channels connected to 1 TDR =2048 channels/tdr 368 FEHs, 23 TDRs and 2 crates á 12 TRDs necessary for Tracker readout Power consumption: 85W on FEHs +94W in TDRs +47W in PSs = 226W 5 Feb 2007 Waclaw Karpinski 23

24 PEBS-Tracker Crate TDR -data reduction board TPSFE -power supply for Front End C&DI - interface for higer DAQ TBIAS - bias voltage generator 5 Feb 2007 Waclaw Karpinski 24

25 PEBS ECAL Electronics 80 Layers, 95 modules/layer Two modules will be readout by one SiPM 3800 channels in total Readout using SiPMs with the size 3mm x 3mm, ~8100 pixels / SiPM The same readout architecture as for the PEBS-Tracker Could be the same ASIC (VA64-SiPM) 3 mm 3 mm SiPM 5 Feb 2007 Waclaw Karpinski 25

26 PEBS ECAL Electronics Front-End Board with 6 VA64-SiPM chips One board collects the signals from one side of 2 super layers = 384 channels 5 Front-End Boards controlled by 1 modified TRD board = 1920 channels/tdr Power consumption: 7 W on FEHs +8 W in TDRs + 4 W in PSs = 19 W 5 Feb 2007 Waclaw Karpinski 26

27 PEBS-ECAL Crate EPSFE -power supply for Front End EBIAS - bias voltage generator TDR -data reduction board C&DI - interface for higer DAQ 5 Feb 2007 Waclaw Karpinski 27

28 Scintillator Electronics 4 ToF planes á 8 scintillator paddles 32 scintillators in total with - (4 SiPMs ) per end 256 channels or - one PM per end 64 PMs in total Provides: fast (~30ns) coincidence between at least 3 out of 4 ToF planes to select particles within the main PEBS acceptance measurement of the particle velocity including the direction of the particle, (resolution of 100ps) measurement of the absolute charge of particles rejection of protons with E<1GeV at the trigger level 5 Feb 2007 Waclaw Karpinski 28

29 PM vs SiPM High Voltage (2000V) Low voltage (30V-60V) Influenced by magnetic fields Tested up to 4 Tesla Influenced by vibrations Fragile and heavy Low noise Good temperature stability Better gain stability Not influenced by vibrations Light and robust High noise Sensitive to temperature variation Gain sensitive to voltage variation 5 Feb 2007 Waclaw Karpinski 29

30 AMS2 Scintillator Electronics TOF Readout in AMS2 for 24 PMTs (20 ToF and 4 ACC ) consists of: - SDR2: data collection and reduction & slow control - 4 x SFET2: charge and time measurement of TOF anodes (5 PMs/ board) - SFEA2: charge and time of ACC - SFEC: dynode charge - SPT2: pre-trigger unit fast trigger input - TSPD: DC/DC converters - SHV: high voltage box 5 Feb 2007 Waclaw Karpinski 30

31 5 Feb 2007 Waclaw Karpinski 31

32 PM-PEBS Scintillator Electronics TOF Readout in PEBS for 64 PMTs will consist of three crates: - 1 x SDR2: data collection and reduction & slow control - 5 x SFET2: charge and time measurement TOF anodes (5 PMs/ board) - 1 x SPT2: pre-trigger unit, fast trigger input - 3 x SHV boxes: high voltage generator - 3 x TSPD: DC/DC converters SHV-Box TSPD 5 Feb 2007 Waclaw Karpinski 32

33 Potential ROCs for ToF with SiPms 5 Feb 2007 Waclaw Karpinski 33

34 ASIC production for OPERA target tracker Readout ASIC for multi-anode Photomultiplier (Hamamatsu) OPERA_ROC (2002) 32 channels Variable gain preamp Autotrigger on ¼ p.e. BiCMOS 0.8µ chips 64 ch front-end board (BERN) (S. Blin, T. Caceres, CdLT, G. Martin, L. Raux) 5 Feb 2007 Waclaw Karpinski 34

35 Characteristics MAROC : 64 ch MAPMT chip for ATLAS lumi 64 PMT channels input ( Ω) Variable gain current conveyor (0-2) 6 bits : 2, 1, 1/2, 1/4, 1/8, 1/16 64 discriminator outputs (GTL) 100% sensitivity to 1/3 photoelectron (50fC). Counting rate up to 2 MHz Common threshold loaded by internal 10bit DAC 1 multiplexed charge output with variable shaping ns and Track & Hold. Dynamic range : 11 bits (2fC - 5 pc) Crosstalk < 1% 64 PM inputs Variab le Gain Pream p. Gain correction 6 bits/channel Hold signal Variable Slow Shaper Bipolar Fast Shaper discriminator threshold 10 bits DAC S&H 10 bit DAC Synoptic diagramm of MAROC1 N. Seguin (LAL) Multiplexed charge output 64 Trigger outputs Technology : AMS SiGe 0.35µm Submitted 13 june 05 Area 12 mm 2 Dissipation 130 VDD=3.5V 5 Feb 2007 Waclaw Karpinski 35

36 Next version MAROC2 Hold signal Photons 64 inputs Photomultiplier 64 channels Variable Gain Preamp. Variable Slow Shaper ns Bipolar Fast Shaper S&H S&H 64 Wilkinson 12 bit ADC Multiplexed Analog charge output Multiplexed Digital charge output Gain correction 64*6bits Unipolar Fast Shaper 80 MHz encoder 64 trigger outputs 3 discri thresholds (3*12 bits) New features: 3 DACs 12 bits LUCID Substrate separation Unipolar fast shaper 3 discriminators 80MHz encoding 12bits Wilkinson ADC 5 Feb 2007 Waclaw Karpinski 36

37 SPIROC for AHCAL SiPM Si PM Integrated Read Out Chip (Mar 07) Chip fully dedicated to SiPMs developped after ECAL chip Internal DAC for SiPM gain adjustment (5V range) Auto-trigger (fast shaper + Discriminator) Internal TDC, 1 ns step Internal 12 bit ADC Power pulsing 8 bit DAC (0-5V) in Variable gain Preamplifier Capacitance for AC coupling T&H Shaper t p ~30-40ns Fast Shaper Analogue Memory Threshold 5 Feb 2007 Waclaw Karpinski 37 x1 Auto-trigger 12-bit DAC Discri Charge Ouput Time Ouput 12-bit ADC TDC

38 SiPM-PEBS-TOF Crate C&DI - interface for higer DAQ SDR - data reduction board SFE - charge and time measurement SPT - pre-trigger SPSFE - voltage supply for Front End SBIAS - bias generator for SIPM 5 Feb 2007 Waclaw Karpinski 38

39 PEBS Trigger Electronics generates Fast Trigger: ns after the hit based on a coincidence between at least 3 out of 4 ToF planes evaluates signals from ToF and ECAL if any of predeterminated patterns of these signals occurs generates Level-1 trigger 1µs after the hit starts digitization and data flow for all subdetectors controls the BUSY signal to ensure that the event is collected from the complete detector 5 Feb 2007 Waclaw Karpinski 39

40 PEBS-Trigger Crate TLV1 - level 1 trigger TTBX - fast trigger, fast in/out and logic JINJ - intermediate DAQ, 1CDDC, 24 links to sleeves 4 links to masters 5 Feb 2007 Waclaw Karpinski 40

41 Summary 5 Feb 2007 Waclaw Karpinski 41

42 Summary Power Consumption (ToF readout with PMs) Subsystem Channels Power FE [W] Power DAQ [W] Power PS [W] Power Total [W] TRD Tracker ECAL TOF Trigger 5 Slow Control Main DAQ 45 PDS 60 Contingency Feb 2007 Waclaw Karpinski 42

43 Summary TRD Readout boards used in AMS02 can be utilized without any changes for PEBS-TRD readout For Tracker and ECAL Front End new developments are necessary: investigation of adequate readout chip Front-End Hybrids modifications of voltage supply boards for front end new design of bias voltage generator boards new backplanes Readout Architecture of TRD2 boards can be applied in PEBS Tracker and ECAL but the design of the readout boards must be slightly modified to much the detector granularity Two version of TOF electronics possible: readout using PMs; AMS2 TOF electronics can be easily adapted to PEBS needs readout using SiPMs; new designs necessary 5 Feb 2007 Waclaw Karpinski 43

44 Summary Expected total power dissipation amounts to ~ 600 W, including 100 W contingency Interfaces for power and interface for data transfer to Earth must be investigated 5 Feb 2007 Waclaw Karpinski 44